sim/mips/ChangeLog

   1 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
   2
   3         * interp.c (sim_pc_get): New function.
   4
   5 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
   8         * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
   9
  10 2015-03-24  Mike Frysinger  <vapier@gentoo.org>
  11
  12         * configure: Regenerate.
  13
  14 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
  15
  16         * configure: Regenerate.
  17
  18 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
  19
  20         * configure: Regenerate.
  21         * configure.ac (mips_extra_objs): Delete.
  22         * Makefile.in (MIPS_EXTRA_OBJS): Delete.
  23         (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
  24
  25 2015-03-23  Mike Frysinger  <vapier@gentoo.org>
  26
  27         * configure: Regenerate.
  28         * configure.ac: Delete sim_hw checks for dv-sockser.
  29
  30 2015-03-16  Mike Frysinger  <vapier@gentoo.org>
  31
  32         * config.in, configure: Regenerate.
  33         * tconfig.in: Rename file ...
  34         * tconfig.h: ... here.
  35
  36 2015-03-15  Mike Frysinger  <vapier@gentoo.org>
  37
  38         * tconfig.in: Delete includes.
  39         [HAVE_DV_SOCKSER]: Delete.
  40
  41 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
  42
  43         * Makefile.in (SIM_RUN_OBJS): Delete.
  44
  45 2015-03-14  Mike Frysinger  <vapier@gentoo.org>
  46
  47         * configure.ac (AC_CHECK_HEADERS): Delete.
  48         * aclocal.m4, configure: Regenerate.
  49
  50 2014-08-19  Alan Modra  <amodra@gmail.com>
  51
  52         * configure: Regenerate.
  53
  54 2014-08-15  Roland McGrath  <mcgrathr@google.com>
  55
  56         * configure: Regenerate.
  57         * config.in: Regenerate.
  58
  59 2014-03-04  Mike Frysinger  <vapier@gentoo.org>
  60
  61         * configure: Regenerate.
  62
  63 2013-09-23  Alan Modra  <amodra@gmail.com>
  64
  65         * configure: Regenerate.
  66
  67 2013-06-03  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * aclocal.m4, configure: Regenerate.
  70
  71 2013-05-10  Freddie Chopin  <freddie_chopin@op.pl>
  72
  73         * configure: Rebuild.
  74
  75 2013-03-26  Mike Frysinger  <vapier@gentoo.org>
  76
  77         * configure: Regenerate.
  78
  79 2013-03-23  Joel Sherrill  <joel.sherrill@oarcorp.com>
  80
  81         * configure.ac: Address use of dv-sockser.o.
  82         * tconfig.in: Conditionalize use of dv_sockser_install.
  83         * configure: Regenerated.
  84         * config.in: Regenerated.
  85
  86 2012-10-04  Chao-ying Fu  <fu@mips.com>
  87             Steve Ellcey  <sellcey@mips.com>
  88
  89         * mips/mips3264r2.igen (rdhwr): New.
  90
  91 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
  92
  93         * configure.ac: Always link against dv-sockser.o.
  94         * configure: Regenerate.
  95
  96 2012-06-15  Joel Brobecker  <brobecker@adacore.com>
  97
  98         * config.in, configure: Regenerate.
  99
 100 2012-05-18  Nick Clifton  <nickc@redhat.com>
 101
 102         PR 14072
 103         * interp.c: Include config.h before system header files.
 104
 105 2012-03-24  Mike Frysinger  <vapier@gentoo.org>
 106
 107         * aclocal.m4, config.in, configure: Regenerate.
 108
 109 2011-12-03  Mike Frysinger  <vapier@gentoo.org>
 110
 111         * aclocal.m4: New file.
 112         * configure: Regenerate.
 113
 114 2011-10-19  Mike Frysinger  <vapier@gentoo.org>
 115
 116         * configure: Regenerate after common/acinclude.m4 update.
 117
 118 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 119
 120         * configure.ac: Change include to common/acinclude.m4.
 121
 122 2011-10-17  Mike Frysinger  <vapier@gentoo.org>
 123
 124         * configure.ac: Change AC_PREREQ to 2.64.  Delete AC_CONFIG_HEADER
 125         call.  Replace common.m4 include with SIM_AC_COMMON.
 126         * configure: Regenerate.
 127
 128 2011-07-08  Hans-Peter Nilsson  <hp@axis.com>
 129
 130         * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
 131         $(SIM_EXTRA_DEPS).
 132         (tmp-mach-multi): Exit early when igen fails.
 133
 134 2011-07-05  Mike Frysinger  <vapier@gentoo.org>
 135
 136         * interp.c (sim_do_command): Delete.
 137
 138 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 139
 140         * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
 141         (tx3904sio_fifo_reset): Likewise.
 142         * interp.c (sim_monitor): Likewise.
 143
 144 2010-04-14  Mike Frysinger  <vapier@gentoo.org>
 145
 146         * interp.c (sim_write): Add const to buffer arg.
 147
 148 2010-01-18  Masaki Muranaka  <monaka@monami-software.com>  (tiny change)
 149
 150         * interp.c: Don't include sysdep.h
 151
 152 2010-01-09  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 153
 154         * configure: Regenerate.
 155
 156 2009-08-22  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 157
 158         * config.in: Regenerate.
 159         * configure: Likewise.
 160
 161         * configure: Regenerate.
 162
 163 2008-07-11  Hans-Peter Nilsson  <hp@axis.com>
 164
 165         * configure: Regenerate to track ../common/common.m4 changes.
 166         * config.in: Ditto.
 167
 168 2008-06-06  Vladimir Prus  <vladimir@codesourcery.com>
 169             Daniel Jacobowitz  <dan@codesourcery.com>
 170             Joseph Myers  <joseph@codesourcery.com>
 171
 172         * configure: Regenerate.
 173
 174 2007-10-22  Richard Sandiford  <rsandifo@nildram.co.uk>
 175
 176         * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
 177         that unconditionally allows fmt_ps.
 178         (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
 179         (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
 180         (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
 181         filter from 64,f to 32,f.
 182         (PREFX): Change filter from 64 to 32.
 183         (LDXC1, LUXC1): Provide separate mips32r2 implementations
 184         that use do_load_double instead of do_load.  Make both LUXC1
 185         versions unpredictable if SizeFGR () != 64.
 186         (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
 187         instead of do_store.  Remove unused variable.  Make both SUXC1
 188         versions unpredictable if SizeFGR () != 64.
 189
 190 2007-10-07  Richard Sandiford  <rsandifo@nildram.co.uk>
 191
 192         * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
 193         (sc, swxc1): Likewise.  Also fix big-endian and reverse-endian
 194         shifts for that case.
 195
 196 2007-09-04  Nick Clifton  <nickc@redhat.com>
 197
 198         * interp.c (options enum): Add OPTION_INFO_MEMORY.
 199         (display_mem_info): New static variable.
 200         (mips_option_handler): Handle OPTION_INFO_MEMORY.
 201         (mips_options): Add info-memory and memory-info.
 202         (sim_open): After processing the command line and board
 203         specification, check display_mem_info.  If it is set then
 204         call the real handler for the --memory-info command line
 205         switch.
 206
 207 2007-08-24  Joel Brobecker  <brobecker@adacore.com>
 208
 209         * configure.ac: Change license of multi-run.c to GPL version 3.
 210         * configure: Regenerate.
 211
 212 2007-06-28  Richard Sandiford  <richard@codesourcery.com>
 213
 214         * configure.ac, configure: Revert last patch.
 215
 216 2007-06-26  Richard Sandiford  <richard@codesourcery.com>
 217
 218         * configure.ac (sim_mipsisa3264_configs): New variable.
 219         (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
 220         every configuration support all four targets, using the triplet to
 221         determine the default.
 222         * configure: Regenerate.
 223
 224 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
 225
 226         * Makefile.in (m16run.o): New rule.
 227
 228 2007-05-15  Thiemo Seufer  <ths@mips.com>
 229
 230         * mips3264r2.igen (DSHD): Fix compile warning.
 231
 232 2007-05-14  Thiemo Seufer  <ths@mips.com>
 233
 234         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
 235         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
 236         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
 237         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
 238         for mips32r2.
 239
 240 2007-03-01  Thiemo Seufer  <ths@mips.com>
 241
 242         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
 243         and mips64.
 244
 245 2007-02-20  Thiemo Seufer  <ths@mips.com>
 246
 247         * dsp.igen: Update copyright notice.
 248         * dsp2.igen: Fix copyright notice.
 249
 250 2007-02-20  Thiemo Seufer  <ths@mips.com>
 251             Chao-Ying Fu  <fu@mips.com>
 252
 253         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
 254         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 255         Add dsp2 to sim_igen_machine.
 256         * configure: Regenerate.
 257         * dsp.igen (do_ph_op): Add MUL support when op = 2.
 258         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
 259         (mulq_rs.ph): Use do_ph_mulq.
 260         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
 261         * mips.igen: Add dsp2 model and include dsp2.igen.
 262         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
 263         for *mips32r2, *mips64r2, *dsp.
 264         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
 265         for *mips32r2, *mips64r2, *dsp2.
 266         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
 267
 268 2007-02-19  Thiemo Seufer  <ths@mips.com>
 269             Nigel Stephens  <nigel@mips.com>
 270
 271         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
 272         jumps with hazard barrier.
 273
 274 2007-02-19  Thiemo Seufer  <ths@mips.com>
 275             Nigel Stephens  <nigel@mips.com>
 276
 277         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
 278         after each call to sim_io_write.
 279
 280 2007-02-19  Thiemo Seufer  <ths@mips.com>
 281             Nigel Stephens  <nigel@mips.com>
 282
 283         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
 284         supported by this simulator.
 285         (decode_coproc): Recognise additional CP0 Config registers
 286         correctly.
 287
 288 2007-02-19  Thiemo Seufer  <ths@mips.com>
 289             Nigel Stephens  <nigel@mips.com>
 290             David Ung  <davidu@mips.com>
 291
 292         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
 293         uninterpreted formats. If fmt is one of the uninterpreted types
 294         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
 295         fmt_word, and fmt_uninterpreted_64 like fmt_long.
 296         (store_fpr): When writing an invalid odd register, set the
 297         matching even register to fmt_unknown, not the following register.
 298         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
 299         the the memory window at offset 0 set by --memory-size command
 300         line option.
 301         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
 302         point register.
 303         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
 304         register.
 305         (sim_monitor): When returning the memory size to the MIPS
 306         application, use the value in STATE_MEM_SIZE, not an arbitrary
 307         hardcoded value.
 308         (cop_lw): Don' mess around with FPR_STATE, just pass
 309         fmt_uninterpreted_32 to StoreFPR.
 310         (cop_sw): Similarly.
 311         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
 312         (cop_sd): Similarly.
 313         * mips.igen (not_word_value): Single version for mips32, mips64
 314         and mips16.
 315
 316 2007-02-19  Thiemo Seufer <ths@mips.com>
 317             Nigel Stephens  <nigel@mips.com>
 318
 319         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
 320         MBytes.
 321
 322 2007-02-17  Thiemo Seufer  <ths@mips.com>
 323
 324         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 325         configuration.
 326         * configure: Regenerate.
 327
 328 2007-02-17  Thiemo Seufer  <ths@mips.com>
 329
 330         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 331         Add mdmx to sim_igen_machine.
 332         (mipsisa64*-*-*): Likewise. Remove dsp.
 333         (mipsisa32*-*-*): Remove dsp.
 334         * configure: Regenerate.
 335
 336 2007-02-13  Thiemo Seufer  <ths@mips.com>
 337
 338         * configure.ac: Add mips*-sde-elf* target.
 339         * configure: Regenerate.
 340
 341 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 342
 343         * acconfig.h: Remove.
 344         * config.in, configure: Regenerate.
 345
 346 2006-11-07  Thiemo Seufer  <ths@mips.com>
 347
 348         * dsp.igen (do_w_op): Fix compiler warning.
 349
 350 2006-08-29  Thiemo Seufer  <ths@mips.com>
 351             David Ung  <davidu@mips.com>
 352
 353         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 354         sim_igen_machine.
 355         * configure: Regenerate.
 356         * mips.igen (model): Add smartmips.
 357         (MADDU): Increment ACX if carry.
 358         (do_mult): Clear ACX.
 359         (ROR,RORV): Add smartmips.
 360         (include): Include smartmips.igen.
 361         * sim-main.h (ACX): Set to REGISTERS[89].
 362         * smartmips.igen: New file.
 363
 364 2006-08-29  Thiemo Seufer  <ths@mips.com>
 365             David Ung  <davidu@mips.com>
 366
 367         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 368         mips3264r2.igen. Add missing dependency rules.
 369         * m16e.igen: Support for mips16e save/restore instructions.
 370
 371 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 372
 373         * configure: Regenerated.
 374
 375 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 376
 377         * configure: Regenerated.
 378
 379 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 380
 381         * configure: Regenerated.
 382
 383 2006-05-15 Chao-ying Fu  <fu@mips.com>
 384
 385         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 386
 387 2006-04-18  Nick Clifton  <nickc@redhat.com>
 388
 389         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 390         statement.
 391
 392 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 393
 394         * configure: Regenerate.
 395
 396 2005-12-14  Chao-ying Fu  <fu@mips.com>
 397
 398         * Makefile.in (SIM_OBJS): Add dsp.o.
 399         (dsp.o): New dependency.
 400         (IGEN_INCLUDE): Add dsp.igen.
 401         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 402         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 403         * configure: Regenerate.
 404         * mips.igen: Add dsp model and include dsp.igen.
 405         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 406         because these instructions are extended in DSP ASE.
 407         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 408         adding 6 DSP accumulator registers and 1 DSP control register.
 409         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 410         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 411         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 412         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 413         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 414         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 415         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 416         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 417         DSPCR_CCOND_SMASK): New define.
 418         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 419         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 420
 421 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 422
 423         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 424
 425 2005-06-16  David Ung  <davidu@mips.com>
 426             Nigel Stephens  <nigel@mips.com>
 427
 428         * mips.igen: New mips16e model and include m16e.igen.
 429         (check_u64): Add mips16e tag.
 430         * m16e.igen: New file for MIPS16e instructions.
 431         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 432         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 433         models.
 434         * configure: Regenerate.
 435
 436 2005-05-26  David Ung  <davidu@mips.com>
 437
 438         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 439         tags to all instructions which are applicable to the new ISAs.
 440         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 441         vr.igen.
 442         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 443         instructions.
 444         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 445         to mips.igen.
 446         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 447         * configure: Regenerate.
 448
 449 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 450
 451         * configure: Regenerate.
 452
 453 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 454
 455         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 456         explicit call to AC_CONFIG_HEADER.
 457         * configure: Regenerate.
 458
 459 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 460
 461         * configure.ac: Update to use ../common/common.m4.
 462         * configure: Re-generate.
 463
 464 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 465
 466         * configure: Regenerated to track ../common/aclocal.m4 changes.
 467
 468 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 469
 470         * configure.ac: Rename configure.in, require autoconf 2.59.
 471         * configure: Re-generate.
 472
 473 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 474
 475         * configure: Regenerate for ../common/aclocal.m4 update.
 476
 477 2004-09-24  Monika Chaddha  <monika@acmet.com>
 478
 479         Committed by Andrew Cagney.
 480         * m16.igen (CMP, CMPI): Fix assembler.
 481
 482 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 483
 484         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 485         * configure: Regenerate.
 486
 487 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 488
 489         * configure.in (sim_m16_machine): Include mipsIII.
 490         * configure: Regenerate.
 491
 492 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 493
 494         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 495         from COP0_BADVADDR.
 496         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 497
 498 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 499
 500         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 501
 502 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 503
 504         * mips.igen (check_fmt): Remove.
 505         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 506         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 507         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 508         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 509         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 510         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 511         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 512         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 513         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 514         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 515
 516 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 517
 518         * sb1.igen (check_sbx): New function.
 519         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 520
 521 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 522             Richard Sandiford  <rsandifo@redhat.com>
 523
 524         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 525         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 526         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 527         separate implementations for mipsIV and mipsV.  Use new macros to
 528         determine whether the restrictions apply.
 529
 530 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 531
 532         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 533         (check_mult_hilo): Improve comments.
 534         (check_div_hilo): Likewise.  Also, fork off a new version
 535         to handle mips32/mips64 (since there are no hazards to check
 536         in MIPS32/MIPS64).
 537
 538 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 539
 540         * mips.igen (do_dmultx): Fix check for negative operands.
 541
 542 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 543
 544         * Makefile.in (SHELL): Make sure this is defined.
 545         (various): Use $(SHELL) whenever we invoke move-if-change.
 546
 547 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 548
 549         * cp1.c: Tweak attribution slightly.
 550         * cp1.h: Likewise.
 551         * mdmx.c: Likewise.
 552         * mdmx.igen: Likewise.
 553         * mips3d.igen: Likewise.
 554         * sb1.igen: Likewise.
 555
 556 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 557
 558         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 559         unsigned operands.
 560
 561 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 562
 563         * interp.c (sim_open): Rename _bfd to bfd.
 564         (sim_create_inferior): Ditto.
 565
 566 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 567
 568         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 569
 570 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 571
 572         * mips.igen (EI, DI): Remove.
 573
 574 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 575
 576         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 577
 578 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 579             Andrew Cagney  <ac131313@redhat.com>
 580             Gavin Romig-Koch  <gavin@redhat.com>
 581             Graydon Hoare  <graydon@redhat.com>
 582             Aldy Hernandez  <aldyh@redhat.com>
 583             Dave Brolley  <brolley@redhat.com>
 584             Chris Demetriou  <cgd@broadcom.com>
 585
 586         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 587         (sim_mach_default): New variable.
 588         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 589         Add a new simulator generator, MULTI.
 590         * configure: Regenerate.
 591         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 592         (multi-run.o): New dependency.
 593         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 594         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 595         (tmp-multi): Combine them.
 596         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 597         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 598         (distclean-extra): New rule.
 599         * sim-main.h: Include bfd.h.
 600         (MIPS_MACH): New macro.
 601         * mips.igen (vr4120, vr5400, vr5500): New models.
 602         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 603         * vr.igen: Replace with new version.
 604
 605 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 606
 607         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 608         * configure: Regenerate.
 609
 610 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 611
 612         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 613         * mips.igen: Remove all invocations of check_branch_bug and
 614         mark_branch_bug.
 615
 616 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 617
 618         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 619
 620 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 621
 622         * mips.igen (do_load_double, do_store_double): New functions.
 623         (LDC1, SDC1): Rename to...
 624         (LDC1b, SDC1b): respectively.
 625         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 626
 627 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 628
 629         * cp1.c (fp_recip2): Modify initialization expression so that
 630         GCC will recognize it as constant.
 631
 632 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 633
 634         * mdmx.c (SD_): Delete.
 635         (Unpredictable): Re-define, for now, to directly invoke
 636         unpredictable_action().
 637         (mdmx_acc_op): Fix error in .ob immediate handling.
 638
 639 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 640
 641         * interp.c (sim_firmware_command): Initialize `address'.
 642
 643 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 644
 645         * configure: Regenerated to track ../common/aclocal.m4 changes.
 646
 647 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 648             Ed Satterthwaite  <ehs@broadcom.com>
 649
 650         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 651         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 652         * mips.igen: Include mips3d.igen.
 653         (mips3d): New model name for MIPS-3D ASE instructions.
 654         (CVT.W.fmt): Don't use this instruction for word (source) format
 655         instructions.
 656         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 657         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 658         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 659         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 660         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 661         (RSquareRoot1, RSquareRoot2): New macros.
 662         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 663         (fp_rsqrt2): New functions.
 664         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 665         * configure: Regenerate.
 666
 667 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 668             Ed Satterthwaite  <ehs@broadcom.com>
 669
 670         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 671         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 672         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 673         (convert): Note that this function is not used for paired-single
 674         format conversions.
 675         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 676         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 677         (check_fmt_p): Enable paired-single support.
 678         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 679         (PUU.PS): New instructions.
 680         (CVT.S.fmt): Don't use this instruction for paired-single format
 681         destinations.
 682         * sim-main.h (FP_formats): New value 'fmt_ps.'
 683         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 684         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 685
 686 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 687
 688         * mips.igen: Fix formatting of function calls in
 689         many FP operations.
 690
 691 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 692
 693         * mips.igen (MOVN, MOVZ): Trace result.
 694         (TNEI): Print "tnei" as the opcode name in traces.
 695         (CEIL.W): Add disassembly string for traces.
 696         (RSQRT.fmt): Make location of disassembly string consistent
 697         with other instructions.
 698
 699 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 700
 701         * mips.igen (X): Delete unused function.
 702
 703 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 704
 705         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 706
 707 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 708             Ed Satterthwaite  <ehs@broadcom.com>
 709
 710         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 711         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 712         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 713         (fp_nmsub): New prototypes.
 714         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 715         (NegMultiplySub): New defines.
 716         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 717         (MADD.D, MADD.S): Replace with...
 718         (MADD.fmt): New instruction.
 719         (MSUB.D, MSUB.S): Replace with...
 720         (MSUB.fmt): New instruction.
 721         (NMADD.D, NMADD.S): Replace with...
 722         (NMADD.fmt): New instruction.
 723         (NMSUB.D, MSUB.S): Replace with...
 724         (NMSUB.fmt): New instruction.
 725
 726 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 727             Ed Satterthwaite  <ehs@broadcom.com>
 728
 729         * cp1.c: Fix more comment spelling and formatting.
 730         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 731         (denorm_mode): New function.
 732         (fpu_unary, fpu_binary): Round results after operation, collect
 733         status from rounding operations, and update the FCSR.
 734         (convert): Collect status from integer conversions and rounding
 735         operations, and update the FCSR.  Adjust NaN values that result
 736         from conversions.  Convert to use sim_io_eprintf rather than
 737         fprintf, and remove some debugging code.
 738         * cp1.h (fenr_FS): New define.
 739
 740 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 741
 742         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 743         rounding mode to sim FP rounding mode flag conversion code into...
 744         (rounding_mode): New function.
 745
 746 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 747
 748         * cp1.c: Clean up formatting of a few comments.
 749         (value_fpr): Reformat switch statement.
 750
 751 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 752             Ed Satterthwaite  <ehs@broadcom.com>
 753
 754         * cp1.h: New file.
 755         * sim-main.h: Include cp1.h.
 756         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 757         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 758         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 759         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 760         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 761         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 762         * cp1.c: Don't include sim-fpu.h; already included by
 763         sim-main.h.  Clean up formatting of some comments.
 764         (NaN, Equal, Less): Remove.
 765         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 766         (fp_cmp): New functions.
 767         * mips.igen (do_c_cond_fmt): Remove.
 768         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 769         Compare.  Add result tracing.
 770         (CxC1): Remove, replace with...
 771         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 772         (DMxC1): Remove, replace with...
 773         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 774         (MxC1): Remove, replace with...
 775         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 776
 777 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 778
 779         * sim-main.h (FGRIDX): Remove, replace all uses with...
 780         (FGR_BASE): New macro.
 781         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 782         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 783         (NR_FGR, FGR): Likewise.
 784         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 785         * mips.igen: Likewise.
 786
 787 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 788
 789         * cp1.c: Add an FSF Copyright notice to this file.
 790
 791 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 792             Ed Satterthwaite  <ehs@broadcom.com>
 793
 794         * cp1.c (Infinity): Remove.
 795         * sim-main.h (Infinity): Likewise.
 796
 797         * cp1.c (fp_unary, fp_binary): New functions.
 798         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 799         (fp_sqrt): New functions, implemented in terms of the above.
 800         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 801         (Recip, SquareRoot): Remove (replaced by functions above).
 802         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 803         (fp_recip, fp_sqrt): New prototypes.
 804         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 805         (Recip, SquareRoot): Replace prototypes with #defines which
 806         invoke the functions above.
 807
 808 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 809
 810         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 811         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 812         file, remove PARAMS from prototypes.
 813         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 814         simulator state arguments.
 815         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 816         pass simulator state arguments.
 817         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 818         (store_fpr, convert): Remove 'sd' argument.
 819         (value_fpr): Likewise.  Convert to use 'SD' instead.
 820
 821 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 822
 823         * cp1.c (Min, Max): Remove #if 0'd functions.
 824         * sim-main.h (Min, Max): Remove.
 825
 826 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 827
 828         * cp1.c: fix formatting of switch case and default labels.
 829         * interp.c: Likewise.
 830         * sim-main.c: Likewise.
 831
 832 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 833
 834         * cp1.c: Clean up comments which describe FP formats.
 835          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 836
 837 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 838             Ed Satterthwaite  <ehs@broadcom.com>
 839
 840         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 841         Broadcom SiByte SB-1 processor configurations.
 842         * configure: Regenerate.
 843         * sb1.igen: New file.
 844         * mips.igen: Include sb1.igen.
 845         (sb1): New model.
 846         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 847         * mdmx.igen: Add "sb1" model to all appropriate functions and
 848         instructions.
 849         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 850         (ob_func, ob_acc): Reference the above.
 851         (qh_acc): Adjust to keep the same size as ob_acc.
 852         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 853         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 854
 855 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 856
 857         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 858
 859 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 860             Ed Satterthwaite  <ehs@broadcom.com>
 861
 862         * mips.igen (mdmx): New (pseudo-)model.
 863         * mdmx.c, mdmx.igen: New files.
 864         * Makefile.in (SIM_OBJS): Add mdmx.o.
 865         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 866         New typedefs.
 867         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 868         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 869         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 870         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 871         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 872         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 873         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 874         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 875         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 876         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 877         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 878         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 879         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 880         (qh_fmtsel): New macros.
 881         (_sim_cpu): New member "acc".
 882         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 883         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 884
 885 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 886
 887         * interp.c: Use 'deprecated' rather than 'depreciated.'
 888         * sim-main.h: Likewise.
 889
 890 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 891
 892         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 893         which wouldn't compile anyway.
 894         * sim-main.h (unpredictable_action): New function prototype.
 895         (Unpredictable): Define to call igen function unpredictable().
 896         (NotWordValue): New macro to call igen function not_word_value().
 897         (UndefinedResult): Remove.
 898         * interp.c (undefined_result): Remove.
 899         (unpredictable_action): New function.
 900         * mips.igen (not_word_value, unpredictable): New functions.
 901         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 902         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 903         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 904         NotWordValue() to check for unpredictable inputs, then
 905         Unpredictable() to handle them.
 906
 907 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 908
 909         * mips.igen: Fix formatting of calls to Unpredictable().
 910
 911 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 912
 913         * interp.c (sim_open): Revert previous change.
 914
 915 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 916
 917         * interp.c (sim_open): Disable chunk of code that wrote code in
 918         vector table entries.
 919
 920 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 921
 922         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 923         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 924         unused definitions.
 925
 926 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 927
 928         * cp1.c: Fix many formatting issues.
 929
 930 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 931
 932         * cp1.c (fpu_format_name): New function to replace...
 933         (DOFMT): This.  Delete, and update all callers.
 934         (fpu_rounding_mode_name): New function to replace...
 935         (RMMODE): This.  Delete, and update all callers.
 936
 937 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 938
 939         * interp.c: Move FPU support routines from here to...
 940         * cp1.c: Here.  New file.
 941         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 942         (cp1.o): New target.
 943
 944 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 945
 946         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 947         * mips.igen (mips32, mips64): New models, add to all instructions
 948         and functions as appropriate.
 949         (loadstore_ea, check_u64): New variant for model mips64.
 950         (check_fmt_p): New variant for models mipsV and mips64, remove
 951         mipsV model marking fro other variant.
 952         (SLL) Rename to...
 953         (SLLa) this.
 954         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 955         for mips32 and mips64.
 956         (DCLO, DCLZ): New instructions for mips64.
 957
 958 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 959
 960         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 961         immediate or code as a hex value with the "%#lx" format.
 962         (ANDI): Likewise, and fix printed instruction name.
 963
 964 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 965
 966         * sim-main.h (UndefinedResult, Unpredictable): New macros
 967         which currently do nothing.
 968
 969 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 970
 971         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 972         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 973         (status_CU3): New definitions.
 974
 975         * sim-main.h (ExceptionCause): Add new values for MIPS32
 976         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 977         for DebugBreakPoint and NMIReset to note their status in
 978         MIPS32 and MIPS64.
 979         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 980         (SignalExceptionCacheErr): New exception macros.
 981
 982 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 983
 984         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 985         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 986         is always enabled.
 987         (SignalExceptionCoProcessorUnusable): Take as argument the
 988         unusable coprocessor number.
 989
 990 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 991
 992         * mips.igen: Fix formatting of all SignalException calls.
 993
 994 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 995
 996         * sim-main.h (SIGNEXTEND): Remove.
 997
 998 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 999
1000         * mips.igen: Remove gencode comment from top of file, fix
1001         spelling in another comment.
1002
1003 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
1004
1005         * mips.igen (check_fmt, check_fmt_p): New functions to check
1006         whether specific floating point formats are usable.
1007         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1008         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1009         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1010         Use the new functions.
1011         (do_c_cond_fmt): Remove format checks...
1012         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1013
1014 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1015
1016         * mips.igen: Fix formatting of check_fpu calls.
1017
1018 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1019
1020         * mips.igen (FLOOR.L.fmt): Store correct destination register.
1021
1022 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
1023
1024         * mips.igen: Remove whitespace at end of lines.
1025
1026 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1027
1028         * mips.igen (loadstore_ea): New function to do effective
1029         address calculations.
1030         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1031         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1032         CACHE): Use loadstore_ea to do effective address computations.
1033
1034 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1035
1036         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1037         * mips.igen (LL, CxC1, MxC1): Likewise.
1038
1039 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
1040
1041         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1042         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1043         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1044         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1045         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1046         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1047         Don't split opcode fields by hand, use the opcode field values
1048         provided by igen.
1049
1050 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1051
1052         * mips.igen (do_divu): Fix spacing.
1053
1054         * mips.igen (do_dsllv): Move to be right before DSLLV,
1055         to match the rest of the do_<shift> functions.
1056
1057 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1058
1059         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1060         DSRL32, do_dsrlv): Trace inputs and results.
1061
1062 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
1063
1064         * mips.igen (CACHE): Provide instruction-printing string.
1065
1066         * interp.c (signal_exception): Comment tokens after #endif.
1067
1068 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1069
1070         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1071         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1072         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1073         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1074         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1075         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1076         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1077         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1078
1079 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1080
1081         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1082         instruction-printing string.
1083         (LWU): Use '64' as the filter flag.
1084
1085 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1086
1087         * mips.igen (SDXC1): Fix instruction-printing string.
1088
1089 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
1090
1091         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1092         filter flags "32,f".
1093
1094 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1095
1096         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1097         as the filter flag.
1098
1099 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1100
1101         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1102         add a comma) so that it more closely match the MIPS ISA
1103         documentation opcode partitioning.
1104         (PREF): Put useful names on opcode fields, and include
1105         instruction-printing string.
1106
1107 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1108
1109         * mips.igen (check_u64): New function which in the future will
1110         check whether 64-bit instructions are usable and signal an
1111         exception if not.  Currently a no-op.
1112         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1113         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1114         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1115         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1116
1117         * mips.igen (check_fpu): New function which in the future will
1118         check whether FPU instructions are usable and signal an exception
1119         if not.  Currently a no-op.
1120         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1121         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1122         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1123         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1124         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1125         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1126         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1127         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1128
1129 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1130
1131         * mips.igen (do_load_left, do_load_right): Move to be immediately
1132         following do_load.
1133         (do_store_left, do_store_right): Move to be immediately following
1134         do_store.
1135
1136 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
1137
1138         * mips.igen (mipsV): New model name.  Also, add it to
1139         all instructions and functions where it is appropriate.
1140
1141 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
1142
1143         * mips.igen: For all functions and instructions, list model
1144         names that support that instruction one per line.
1145
1146 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1147
1148         * mips.igen: Add some additional comments about supported
1149         models, and about which instructions go where.
1150         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1151         order as is used in the rest of the file.
1152
1153 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
1154
1155         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1156         indicating that ALU32_END or ALU64_END are there to check
1157         for overflow.
1158         (DADD): Likewise, but also remove previous comment about
1159         overflow checking.
1160
1161 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1162
1163         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1164         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1165         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1166         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1167         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1168         fields (i.e., add and move commas) so that they more closely
1169         match the MIPS ISA documentation opcode partitioning.
1170
1171 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
1172
1173         * mips.igen (ADDI): Print immediate value.
1174         (BREAK): Print code.
1175         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1176         (SLL): Print "nop" specially, and don't run the code
1177         that does the shift for the "nop" case.
1178
1179 2001-11-17  Fred Fish  <fnf@redhat.com>
1180
1181         * sim-main.h (float_operation): Move enum declaration outside
1182         of _sim_cpu struct declaration.
1183
1184 2001-04-12  Jim Blandy  <jimb@redhat.com>
1185
1186         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1187         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
1188         set of the FCSR.
1189         * sim-main.h (COCIDX): Remove definition; this isn't supported by
1190         PENDING_FILL, and you can get the intended effect gracefully by
1191         calling PENDING_SCHED directly.
1192
1193 2001-02-23  Ben Elliston  <bje@redhat.com>
1194
1195         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1196         already defined elsewhere.
1197
1198 2001-02-19  Ben Elliston  <bje@redhat.com>
1199
1200         * sim-main.h (sim_monitor): Return an int.
1201         * interp.c (sim_monitor): Add return values.
1202         (signal_exception): Handle error conditions from sim_monitor.
1203
1204 2001-02-08  Ben Elliston  <bje@redhat.com>
1205
1206         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1207         (store_memory): Likewise, pass cia to sim_core_write*.
1208
1209 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
1210
1211         On advice from Chris G. Demetriou <cgd@sibyte.com>:
1212         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1213
1214 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1215
1216         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1217         * Makefile.in: Don't delete *.igen when cleaning directory.
1218
1219 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1220
1221         * m16.igen (break): Call SignalException not sim_engine_halt.
1222
1223 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1224
1225         From Jason Eckhardt:
1226         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1227
1228 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1229
1230         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1231
1232 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1233
1234         * mips.igen (do_dmultx): Fix typo.
1235
1236 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * configure: Regenerated to track ../common/aclocal.m4 changes.
1239
1240 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1241
1242         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1243
1244 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1245
1246         * sim-main.h (GPR_CLEAR): Define macro.
1247
1248 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1249
1250         * interp.c (decode_coproc): Output long using %lx and not %s.
1251
1252 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1253
1254         * interp.c (sim_open): Sort & extend dummy memory regions for
1255         --board=jmr3904 for eCos.
1256
1257 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1258
1259         * configure: Regenerated.
1260
1261 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1262
1263         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1264         calls, conditional on the simulator being in verbose mode.
1265
1266 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1267
1268         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1269         cache don't get ReservedInstruction traps.
1270
1271 1999-11-29  Mark Salter  <msalter@cygnus.com>
1272
1273         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1274         to clear status bits in sdisr register. This is how the hardware works.
1275
1276         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1277         being used by cygmon.
1278
1279 1999-11-11  Andrew Haley  <aph@cygnus.com>
1280
1281         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1282         instructions.
1283
1284 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1285
1286         * mips.igen (MULT): Correct previous mis-applied patch.
1287
1288 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1289
1290         * mips.igen (delayslot32): Handle sequence like
1291         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1292         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1293         (MULT): Actually pass the third register...
1294
1295 1999-09-03  Mark Salter  <msalter@cygnus.com>
1296
1297         * interp.c (sim_open): Added more memory aliases for additional
1298         hardware being touched by cygmon on jmr3904 board.
1299
1300 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1301
1302         * configure: Regenerated to track ../common/aclocal.m4 changes.
1303
1304 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1305
1306         * interp.c (sim_store_register): Handle case where client - GDB -
1307         specifies that a 4 byte register is 8 bytes in size.
1308         (sim_fetch_register): Ditto.
1309
1310 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1311
1312         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1313         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1314         (idt_monitor_base): Base address for IDT monitor traps.
1315         (pmon_monitor_base): Ditto for PMON.
1316         (lsipmon_monitor_base): Ditto for LSI PMON.
1317         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1318         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1319         (sim_firmware_command): New function.
1320         (mips_option_handler): Call it for OPTION_FIRMWARE.
1321         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1322         option was given, add no monitor by default.  Add BREAK hooks only if
1323         monitors are also there.
1324
1325 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1326
1327         * interp.c (sim_monitor): Flush output before reading input.
1328
1329 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * tconfig.in (SIM_HANDLES_LMA): Always define.
1332
1333 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1334
1335         From Mark Salter <msalter@cygnus.com>:
1336         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1337         (sim_open): Add setup for BSP board.
1338
1339 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1340
1341         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1342         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1343         them as unimplemented.
1344
1345 1999-05-08  Felix Lee  <flee@cygnus.com>
1346
1347         * configure: Regenerated to track ../common/aclocal.m4 changes.
1348
1349 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1350
1351         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1352
1353 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1354
1355         * configure.in: Any mips64vr5*-*-* target should have
1356         -DTARGET_ENABLE_FR=1.
1357         (default_endian): Any mips64vr*el-*-* target should default to
1358         LITTLE_ENDIAN.
1359         * configure: Re-generate.
1360
1361 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1362
1363         * mips.igen (ldl): Extend from _16_, not 32.
1364
1365 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1366
1367         * interp.c (sim_store_register): Force registers written to by GDB
1368         into an un-interpreted state.
1369
1370 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1371
1372         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1373         CPU, start periodic background I/O polls.
1374         (tx3904sio_poll): New function: periodic I/O poller.
1375
1376 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1377
1378         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1379
1380 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1381
1382         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1383         case statement.
1384
1385 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1386
1387         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1388         (load_word): Call SIM_CORE_SIGNAL hook on error.
1389         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1390         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1391         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1392         * sim-main.h (COP0_BADVADDR): Define.
1393         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1394         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1395         (_sim_cpu): Add exc_* fields to store register value snapshots.
1396         * mips.igen (*): Replace memory-related SignalException* calls
1397         with references to SIM_CORE_SIGNAL hook.
1398
1399         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1400         fix.
1401         * sim-main.c (*): Minor warning cleanups.
1402
1403 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1404
1405         * m16.igen (DADDIU5): Correct type-o.
1406
1407 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1408
1409         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1410         variables.
1411
1412 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1413
1414         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1415         to include path.
1416         (interp.o): Add dependency on itable.h
1417         (oengine.c, gencode): Delete remaining references.
1418         (BUILT_SRC_FROM_GEN): Clean up.
1419
1420 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1421
1422         * vr4run.c: New.
1423         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1424         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1425         tmp-run-hack) : New.
1426         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1427         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1428         Drop the "64" qualifier to get the HACK generator working.
1429         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1430         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1431         qualifier to get the hack generator working.
1432         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1433         (DSLL): Use do_dsll.
1434         (DSLLV): Use do_dsllv.
1435         (DSRA): Use do_dsra.
1436         (DSRL): Use do_dsrl.
1437         (DSRLV): Use do_dsrlv.
1438         (BC1): Move *vr4100 to get the HACK generator working.
1439         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1440         get the HACK generator working.
1441         (MACC) Rename to get the HACK generator working.
1442         (DMACC,MACCS,DMACCS): Add the 64.
1443
1444 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1445
1446         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1447         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1448
1449 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1450
1451     * mips/interp.c (DEBUG): Cleanups.
1452
1453 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1454
1455         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1456         (tx3904sio_tickle): fflush after a stdout character output.
1457
1458 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1459
1460         * interp.c (sim_close): Uninstall modules.
1461
1462 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1463
1464         * sim-main.h, interp.c (sim_monitor): Change to global
1465         function.
1466
1467 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * configure.in (vr4100): Only include vr4100 instructions in
1470         simulator.
1471         * configure: Re-generate.
1472         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1473
1474 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1475
1476         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1477         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1478         true alternative.
1479
1480         * configure.in (sim_default_gen, sim_use_gen): Replace with
1481         sim_gen.
1482         (--enable-sim-igen): Delete config option. Always using IGEN.
1483         * configure: Re-generate.
1484
1485         * Makefile.in (gencode): Kill, kill, kill.
1486         * gencode.c: Ditto.
1487
1488 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1489
1490         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1491         bit mips16 igen simulator.
1492         * configure: Re-generate.
1493
1494         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1495         as part of vr4100 ISA.
1496         * vr.igen: Mark all instructions as 64 bit only.
1497
1498 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1499
1500         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1501         Pacify GCC.
1502
1503 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1504
1505         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1506         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1507         * configure: Re-generate.
1508
1509         * m16.igen (BREAK): Define breakpoint instruction.
1510         (JALX32): Mark instruction as mips16 and not r3900.
1511         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1512
1513         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1514
1515 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1516
1517         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1518         insn as a debug breakpoint.
1519
1520         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1521         pending.slot_size.
1522         (PENDING_SCHED): Clean up trace statement.
1523         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1524         (PENDING_FILL): Delay write by only one cycle.
1525         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1526
1527         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1528         of pending writes.
1529         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1530         32 & 64.
1531         (pending_tick): Move incrementing of index to FOR statement.
1532         (pending_tick): Only update PENDING_OUT after a write has occured.
1533
1534         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1535         build simulator.
1536         * configure: Re-generate.
1537
1538         * interp.c (sim_engine_run OLD): Delete explicit call to
1539         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1540
1541 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1542
1543         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1544         interrupt level number to match changed SignalExceptionInterrupt
1545         macro.
1546
1547 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1548
1549         * interp.c: #include "itable.h" if WITH_IGEN.
1550         (get_insn_name): New function.
1551         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1552         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1553
1554 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1555
1556         * configure: Rebuilt to inhale new common/aclocal.m4.
1557
1558 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1559
1560         * dv-tx3904sio.c: Include sim-assert.h.
1561
1562 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1563
1564         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1565         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1566         Reorganize target-specific sim-hardware checks.
1567         * configure: rebuilt.
1568         * interp.c (sim_open): For tx39 target boards, set
1569         OPERATING_ENVIRONMENT, add tx3904sio devices.
1570         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1571         ROM executables.  Install dv-sockser into sim-modules list.
1572
1573         * dv-tx3904irc.c: Compiler warning clean-up.
1574         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1575         frequent hw-trace messages.
1576
1577 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1578
1579         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1580
1581 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1582
1583         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1584
1585         * vr.igen: New file.
1586         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1587         * mips.igen: Define vr4100 model. Include vr.igen.
1588 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1589
1590         * mips.igen (check_mf_hilo): Correct check.
1591
1592 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1593
1594         * sim-main.h (interrupt_event): Add prototype.
1595
1596         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1597         register_ptr, register_value.
1598         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1599
1600         * sim-main.h (tracefh): Make extern.
1601
1602 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1603
1604         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1605         Reduce unnecessarily high timer event frequency.
1606         * dv-tx3904cpu.c: Ditto for interrupt event.
1607
1608 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1609
1610         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1611         to allay warnings.
1612         (interrupt_event): Made non-static.
1613
1614         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1615         interchange of configuration values for external vs. internal
1616         clock dividers.
1617
1618 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1619
1620         * mips.igen (BREAK): Moved code to here for
1621         simulator-reserved break instructions.
1622         * gencode.c (build_instruction): Ditto.
1623         * interp.c (signal_exception): Code moved from here.  Non-
1624         reserved instructions now use exception vector, rather
1625         than halting sim.
1626         * sim-main.h: Moved magic constants to here.
1627
1628 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1629
1630         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1631         register upon non-zero interrupt event level, clear upon zero
1632         event value.
1633         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1634         by passing zero event value.
1635         (*_io_{read,write}_buffer): Endianness fixes.
1636         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1637         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1638
1639         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1640         serial I/O and timer module at base address 0xFFFF0000.
1641
1642 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1643
1644         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1645         and BigEndianCPU.
1646
1647 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1648
1649         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1650         parts.
1651         * configure: Update.
1652
1653 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1654
1655         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1656         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1657         * configure.in: Include tx3904tmr in hw_device list.
1658         * configure: Rebuilt.
1659         * interp.c (sim_open): Instantiate three timer instances.
1660         Fix address typo of tx3904irc instance.
1661
1662 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1663
1664         * interp.c (signal_exception): SystemCall exception now uses
1665         the exception vector.
1666
1667 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1668
1669         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1670         to allay warnings.
1671
1672 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1673
1674         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1675
1676 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1677
1678         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1679
1680         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1681         sim-main.h. Declare a struct hw_descriptor instead of struct
1682         hw_device_descriptor.
1683
1684 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1685
1686         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1687         right bits and then re-align left hand bytes to correct byte
1688         lanes.  Fix incorrect computation in do_store_left when loading
1689         bytes from second word.
1690
1691 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1692
1693         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1694         * interp.c (sim_open): Only create a device tree when HW is
1695         enabled.
1696
1697         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1698         * interp.c (signal_exception): Ditto.
1699
1700 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1701
1702         * gencode.c: Mark BEGEZALL as LIKELY.
1703
1704 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1705
1706         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1707         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1708
1709 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1710
1711         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1712         modules.  Recognize TX39 target with "mips*tx39" pattern.
1713         * configure: Rebuilt.
1714         * sim-main.h (*): Added many macros defining bits in
1715         TX39 control registers.
1716         (SignalInterrupt): Send actual PC instead of NULL.
1717         (SignalNMIReset): New exception type.
1718         * interp.c (board): New variable for future use to identify
1719         a particular board being simulated.
1720         (mips_option_handler,mips_options): Added "--board" option.
1721         (interrupt_event): Send actual PC.
1722         (sim_open): Make memory layout conditional on board setting.
1723         (signal_exception): Initial implementation of hardware interrupt
1724         handling.  Accept another break instruction variant for simulator
1725         exit.
1726         (decode_coproc): Implement RFE instruction for TX39.
1727         (mips.igen): Decode RFE instruction as such.
1728         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1729         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1730         bbegin to implement memory map.
1731         * dv-tx3904cpu.c: New file.
1732         * dv-tx3904irc.c: New file.
1733
1734 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1735
1736         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1737
1738 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1739
1740         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1741         with calls to check_div_hilo.
1742
1743 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1744
1745         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1746         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1747         Add special r3900 version of do_mult_hilo.
1748         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1749         with calls to check_mult_hilo.
1750         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1751         with calls to check_div_hilo.
1752
1753 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1754
1755         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1756         Document a replacement.
1757
1758 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1759
1760         * interp.c (sim_monitor): Make mon_printf work.
1761
1762 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1763
1764         * sim-main.h (INSN_NAME): New arg `cpu'.
1765
1766 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1767
1768         * configure: Regenerated to track ../common/aclocal.m4 changes.
1769
1770 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1771
1772         * configure: Regenerated to track ../common/aclocal.m4 changes.
1773         * config.in: Ditto.
1774
1775 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1776
1777         * acconfig.h: New file.
1778         * configure.in: Reverted change of Apr 24; use sinclude again.
1779
1780 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1781
1782         * configure: Regenerated to track ../common/aclocal.m4 changes.
1783         * config.in: Ditto.
1784
1785 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1786
1787         * configure.in: Don't call sinclude.
1788
1789 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1790
1791         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1792
1793 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1794
1795         * mips.igen (ERET): Implement.
1796
1797         * interp.c (decode_coproc): Return sign-extended EPC.
1798
1799         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1800
1801         * interp.c (signal_exception): Do not ignore Trap.
1802         (signal_exception): On TRAP, restart at exception address.
1803         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1804         (signal_exception): Update.
1805         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1806         so that TRAP instructions are caught.
1807
1808 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1809
1810         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1811         contains HI/LO access history.
1812         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1813         (HIACCESS, LOACCESS): Delete, replace with
1814         (HIHISTORY, LOHISTORY): New macros.
1815         (CHECKHILO): Delete all, moved to mips.igen
1816
1817         * gencode.c (build_instruction): Do not generate checks for
1818         correct HI/LO register usage.
1819
1820         * interp.c (old_engine_run): Delete checks for correct HI/LO
1821         register usage.
1822
1823         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1824         check_mf_cycles): New functions.
1825         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1826         do_divu, domultx, do_mult, do_multu): Use.
1827
1828         * tx.igen ("madd", "maddu"): Use.
1829
1830 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1831
1832         * mips.igen (DSRAV): Use function do_dsrav.
1833         (SRAV): Use new function do_srav.
1834
1835         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1836         (B): Sign extend 11 bit immediate.
1837         (EXT-B*): Shift 16 bit immediate left by 1.
1838         (ADDIU*): Don't sign extend immediate value.
1839
1840 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1841
1842         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1843
1844         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1845         functions.
1846
1847         * mips.igen (delayslot32, nullify_next_insn): New functions.
1848         (m16.igen): Always include.
1849         (do_*): Add more tracing.
1850
1851         * m16.igen (delayslot16): Add NIA argument, could be called by a
1852         32 bit MIPS16 instruction.
1853
1854         * interp.c (ifetch16): Move function from here.
1855         * sim-main.c (ifetch16): To here.
1856
1857         * sim-main.c (ifetch16, ifetch32): Update to match current
1858         implementations of LH, LW.
1859         (signal_exception): Don't print out incorrect hex value of illegal
1860         instruction.
1861
1862 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1863
1864         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1865         instruction.
1866
1867         * m16.igen: Implement MIPS16 instructions.
1868
1869         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1870         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1871         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1872         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1873         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1874         bodies of corresponding code from 32 bit insn to these.  Also used
1875         by MIPS16 versions of functions.
1876
1877         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1878         (IMEM16): Drop NR argument from macro.
1879
1880 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1881
1882         * Makefile.in (SIM_OBJS): Add sim-main.o.
1883
1884         * sim-main.h (address_translation, load_memory, store_memory,
1885         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1886         as INLINE_SIM_MAIN.
1887         (pr_addr, pr_uword64): Declare.
1888         (sim-main.c): Include when H_REVEALS_MODULE_P.
1889
1890         * interp.c (address_translation, load_memory, store_memory,
1891         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1892         from here.
1893         * sim-main.c: To here. Fix compilation problems.
1894
1895         * configure.in: Enable inlining.
1896         * configure: Re-config.
1897
1898 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1899
1900         * configure: Regenerated to track ../common/aclocal.m4 changes.
1901
1902 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1903
1904         * mips.igen: Include tx.igen.
1905         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1906         * tx.igen: New file, contains MADD and MADDU.
1907
1908         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1909         the hardwired constant `7'.
1910         (store_memory): Ditto.
1911         (LOADDRMASK): Move definition to sim-main.h.
1912
1913         mips.igen (MTC0): Enable for r3900.
1914         (ADDU): Add trace.
1915
1916         mips.igen (do_load_byte): Delete.
1917         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1918         do_store_right): New functions.
1919         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1920
1921         configure.in: Let the tx39 use igen again.
1922         configure: Update.
1923
1924 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1925
1926         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1927         not an address sized quantity.  Return zero for cache sizes.
1928
1929 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1930
1931         * mips.igen (r3900): r3900 does not support 64 bit integer
1932         operations.
1933
1934 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1935
1936         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1937         than igen one.
1938         * configure : Rebuild.
1939
1940 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1941
1942         * configure: Regenerated to track ../common/aclocal.m4 changes.
1943
1944 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1945
1946         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1947
1948 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1949
1950         * configure: Regenerated to track ../common/aclocal.m4 changes.
1951         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1952
1953 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1954
1955         * configure: Regenerated to track ../common/aclocal.m4 changes.
1956
1957 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1958
1959         * interp.c (Max, Min): Comment out functions. Not yet used.
1960
1961 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1962
1963         * configure: Regenerated to track ../common/aclocal.m4 changes.
1964
1965 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1966
1967         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1968         configurable settings for stand-alone simulator.
1969
1970         * configure.in: Added X11 search, just in case.
1971
1972         * configure: Regenerated.
1973
1974 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1975
1976         * interp.c (sim_write, sim_read, load_memory, store_memory):
1977         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1978
1979 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1980
1981         * sim-main.h (GETFCC): Return an unsigned value.
1982
1983 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1984
1985         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1986         (DADD): Result destination is RD not RT.
1987
1988 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1989
1990         * sim-main.h (HIACCESS, LOACCESS): Always define.
1991
1992         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1993
1994         * interp.c (sim_info): Delete.
1995
1996 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1997
1998         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1999         (mips_option_handler): New argument `cpu'.
2000         (sim_open): Update call to sim_add_option_table.
2001
2002 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2003
2004         * mips.igen (CxC1): Add tracing.
2005
2006 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2007
2008         * sim-main.h (Max, Min): Declare.
2009
2010         * interp.c (Max, Min): New functions.
2011
2012         * mips.igen (BC1): Add tracing.
2013
2014 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
2015
2016         * interp.c Added memory map for stack in vr4100
2017
2018 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
2019
2020         * interp.c (load_memory): Add missing "break"'s.
2021
2022 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2023
2024         * interp.c (sim_store_register, sim_fetch_register): Pass in
2025         length parameter.  Return -1.
2026
2027 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
2028
2029         * interp.c: Added hardware init hook, fixed warnings.
2030
2031 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2032
2033         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2034
2035 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2036
2037         * interp.c (ifetch16): New function.
2038
2039         * sim-main.h (IMEM32): Rename IMEM.
2040         (IMEM16_IMMED): Define.
2041         (IMEM16): Define.
2042         (DELAY_SLOT): Update.
2043
2044         * m16run.c (sim_engine_run): New file.
2045
2046         * m16.igen: All instructions except LB.
2047         (LB): Call do_load_byte.
2048         * mips.igen (do_load_byte): New function.
2049         (LB): Call do_load_byte.
2050
2051         * mips.igen: Move spec for insn bit size and high bit from here.
2052         * Makefile.in (tmp-igen, tmp-m16): To here.
2053
2054         * m16.dc: New file, decode mips16 instructions.
2055
2056         * Makefile.in (SIM_NO_ALL): Define.
2057         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2058
2059 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2060
2061         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2062         point unit to 32 bit registers.
2063         * configure: Re-generate.
2064
2065 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2066
2067         * configure.in (sim_use_gen): Make IGEN the default simulator
2068         generator for generic 32 and 64 bit mips targets.
2069         * configure: Re-generate.
2070
2071 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2072
2073         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2074         bitsize.
2075
2076         * interp.c (sim_fetch_register, sim_store_register): Read/write
2077         FGR from correct location.
2078         (sim_open): Set size of FGR's according to
2079         WITH_TARGET_FLOATING_POINT_BITSIZE.
2080
2081         * sim-main.h (FGR): Store floating point registers in a separate
2082         array.
2083
2084 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2085
2086         * configure: Regenerated to track ../common/aclocal.m4 changes.
2087
2088 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2089
2090         * interp.c (ColdReset): Call PENDING_INVALIDATE.
2091
2092         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2093
2094         * interp.c (pending_tick): New function.  Deliver pending writes.
2095
2096         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2097         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2098         it can handle mixed sized quantites and single bits.
2099
2100 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2101
2102         * interp.c (oengine.h): Do not include when building with IGEN.
2103         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2104         (sim_info): Ditto for PROCESSOR_64BIT.
2105         (sim_monitor): Replace ut_reg with unsigned_word.
2106         (*): Ditto for t_reg.
2107         (LOADDRMASK): Define.
2108         (sim_open): Remove defunct check that host FP is IEEE compliant,
2109         using software to emulate floating point.
2110         (value_fpr, ...): Always compile, was conditional on HASFPU.
2111
2112 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2113
2114         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2115         size.
2116
2117         * interp.c (SD, CPU): Define.
2118         (mips_option_handler): Set flags in each CPU.
2119         (interrupt_event): Assume CPU 0 is the one being iterrupted.
2120         (sim_close): Do not clear STATE, deleted anyway.
2121         (sim_write, sim_read): Assume CPU zero's vm should be used for
2122         data transfers.
2123         (sim_create_inferior): Set the PC for all processors.
2124         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2125         argument.
2126         (mips16_entry): Pass correct nr of args to store_word, load_word.
2127         (ColdReset): Cold reset all cpu's.
2128         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2129         (sim_monitor, load_memory, store_memory, signal_exception): Use
2130         `CPU' instead of STATE_CPU.
2131
2132
2133         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2134         SD or CPU_.
2135
2136         * sim-main.h (signal_exception): Add sim_cpu arg.
2137         (SignalException*): Pass both SD and CPU to signal_exception.
2138         * interp.c (signal_exception): Update.
2139
2140         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2141         Ditto
2142         (sync_operation, prefetch, cache_op, store_memory, load_memory,
2143         address_translation): Ditto
2144         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2145
2146 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * configure: Regenerated to track ../common/aclocal.m4 changes.
2149
2150 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2151
2152         * interp.c (sim_engine_run): Add `nr_cpus' argument.
2153
2154         * mips.igen (model): Map processor names onto BFD name.
2155
2156         * sim-main.h (CPU_CIA): Delete.
2157         (SET_CIA, GET_CIA): Define
2158
2159 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
2160
2161         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2162         regiser.
2163
2164         * configure.in (default_endian): Configure a big-endian simulator
2165         by default.
2166         * configure: Re-generate.
2167
2168 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
2169
2170         * configure: Regenerated to track ../common/aclocal.m4 changes.
2171
2172 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
2173
2174         * interp.c (sim_monitor): Handle Densan monitor outbyte
2175         and inbyte functions.
2176
2177 1997-12-29  Felix Lee  <flee@cygnus.com>
2178
2179         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2180
2181 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
2182
2183         * Makefile.in (tmp-igen): Arrange for $zero to always be
2184         reset to zero after every instruction.
2185
2186 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2187
2188         * configure: Regenerated to track ../common/aclocal.m4 changes.
2189         * config.in: Ditto.
2190
2191 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
2192
2193         * mips.igen (MSUB): Fix to work like MADD.
2194         * gencode.c (MSUB): Similarly.
2195
2196 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
2197
2198         * configure: Regenerated to track ../common/aclocal.m4 changes.
2199
2200 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2201
2202         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2203
2204 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2205
2206         * sim-main.h (sim-fpu.h): Include.
2207
2208         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2209         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2210         using host independant sim_fpu module.
2211
2212 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2213
2214         * interp.c (signal_exception): Report internal errors with SIGABRT
2215         not SIGQUIT.
2216
2217         * sim-main.h (C0_CONFIG): New register.
2218         (signal.h): No longer include.
2219
2220         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2221
2222 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2223
2224         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2225
2226 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2227
2228         * mips.igen: Tag vr5000 instructions.
2229         (ANDI): Was missing mipsIV model, fix assembler syntax.
2230         (do_c_cond_fmt): New function.
2231         (C.cond.fmt): Handle mips I-III which do not support CC field
2232         separatly.
2233         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2234         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2235         in IV3.2 spec.
2236         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2237         vr5000 which saves LO in a GPR separatly.
2238
2239         * configure.in (enable-sim-igen): For vr5000, select vr5000
2240         specific instructions.
2241         * configure: Re-generate.
2242
2243 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2244
2245         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2246
2247         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2248         fmt_uninterpreted_64 bit cases to switch.  Convert to
2249         fmt_formatted,
2250
2251         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2252
2253         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2254         as specified in IV3.2 spec.
2255         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2256
2257 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2258
2259         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2260         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2261         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2262         PENDING_FILL versions of instructions.  Simplify.
2263         (X): New function.
2264         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2265         instructions.
2266         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2267         a signed value.
2268         (MTHI, MFHI): Disable code checking HI-LO.
2269
2270         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2271         global.
2272         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2273
2274 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2275
2276         * gencode.c (build_mips16_operands): Replace IPC with cia.
2277
2278         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2279         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2280         IPC to `cia'.
2281         (UndefinedResult): Replace function with macro/function
2282         combination.
2283         (sim_engine_run): Don't save PC in IPC.
2284
2285         * sim-main.h (IPC): Delete.
2286
2287
2288         * interp.c (signal_exception, store_word, load_word,
2289         address_translation, load_memory, store_memory, cache_op,
2290         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2291         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2292         current instruction address - cia - argument.
2293         (sim_read, sim_write): Call address_translation directly.
2294         (sim_engine_run): Rename variable vaddr to cia.
2295         (signal_exception): Pass cia to sim_monitor
2296
2297         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2298         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2299         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2300
2301         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2302         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2303         SIM_ASSERT.
2304
2305         * interp.c (signal_exception): Pass restart address to
2306         sim_engine_restart.
2307
2308         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2309         idecode.o): Add dependency.
2310
2311         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2312         Delete definitions
2313         (DELAY_SLOT): Update NIA not PC with branch address.
2314         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2315
2316         * mips.igen: Use CIA not PC in branch calculations.
2317         (illegal): Call SignalException.
2318         (BEQ, ADDIU): Fix assembler.
2319
2320 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2321
2322         * m16.igen (JALX): Was missing.
2323
2324         * configure.in (enable-sim-igen): New configuration option.
2325         * configure: Re-generate.
2326
2327         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2328
2329         * interp.c (load_memory, store_memory): Delete parameter RAW.
2330         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2331         bypassing {load,store}_memory.
2332
2333         * sim-main.h (ByteSwapMem): Delete definition.
2334
2335         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2336
2337         * interp.c (sim_do_command, sim_commands): Delete mips specific
2338         commands.  Handled by module sim-options.
2339
2340         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2341         (WITH_MODULO_MEMORY): Define.
2342
2343         * interp.c (sim_info): Delete code printing memory size.
2344
2345         * interp.c (mips_size): Nee sim_size, delete function.
2346         (power2): Delete.
2347         (monitor, monitor_base, monitor_size): Delete global variables.
2348         (sim_open, sim_close): Delete code creating monitor and other
2349         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2350         manage memory regions.
2351         (load_memory, store_memory): Use sim-core for memory model.
2352
2353         * interp.c (address_translation): Delete all memory map code
2354         except line forcing 32 bit addresses.
2355
2356 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2357
2358         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2359         trace options.
2360
2361         * interp.c (logfh, logfile): Delete globals.
2362         (sim_open, sim_close): Delete code opening & closing log file.
2363         (mips_option_handler): Delete -l and -n options.
2364         (OPTION mips_options): Ditto.
2365
2366         * interp.c (OPTION mips_options): Rename option trace to dinero.
2367         (mips_option_handler): Update.
2368
2369 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * interp.c (fetch_str): New function.
2372         (sim_monitor): Rewrite using sim_read & sim_write.
2373         (sim_open): Check magic number.
2374         (sim_open): Write monitor vectors into memory using sim_write.
2375         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2376         (sim_read, sim_write): Simplify - transfer data one byte at a
2377         time.
2378         (load_memory, store_memory): Clarify meaning of parameter RAW.
2379
2380         * sim-main.h (isHOST): Defete definition.
2381         (isTARGET): Mark as depreciated.
2382         (address_translation): Delete parameter HOST.
2383
2384         * interp.c (address_translation): Delete parameter HOST.
2385
2386 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2387
2388         * mips.igen:
2389
2390         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2391         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2392
2393 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2394
2395         * mips.igen: Add model filter field to records.
2396
2397 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2398
2399         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2400
2401         interp.c (sim_engine_run): Do not compile function sim_engine_run
2402         when WITH_IGEN == 1.
2403
2404         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2405         target architecture.
2406
2407         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2408         igen. Replace with configuration variables sim_igen_flags /
2409         sim_m16_flags.
2410
2411         * m16.igen: New file.  Copy mips16 insns here.
2412         * mips.igen: From here.
2413
2414 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2415
2416         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2417         to top.
2418         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2419
2420 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2421
2422         * gencode.c (build_instruction): Follow sim_write's lead in using
2423         BigEndianMem instead of !ByteSwapMem.
2424
2425 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2426
2427         * configure.in (sim_gen): Dependent on target, select type of
2428         generator.  Always select old style generator.
2429
2430         configure: Re-generate.
2431
2432         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2433         targets.
2434         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2435         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2436         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2437         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2438         SIM_@sim_gen@_*, set by autoconf.
2439
2440 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2441
2442         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2443
2444         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2445         CURRENT_FLOATING_POINT instead.
2446
2447         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2448         (address_translation): Raise exception InstructionFetch when
2449         translation fails and isINSTRUCTION.
2450
2451         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2452         sim_engine_run): Change type of of vaddr and paddr to
2453         address_word.
2454         (address_translation, prefetch, load_memory, store_memory,
2455         cache_op): Change type of vAddr and pAddr to address_word.
2456
2457         * gencode.c (build_instruction): Change type of vaddr and paddr to
2458         address_word.
2459
2460 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2461
2462         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2463         macro to obtain result of ALU op.
2464
2465 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2466
2467         * interp.c (sim_info): Call profile_print.
2468
2469 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2470
2471         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2472
2473         * sim-main.h (WITH_PROFILE): Do not define, defined in
2474         common/sim-config.h.  Use sim-profile module.
2475         (simPROFILE): Delete defintion.
2476
2477         * interp.c (PROFILE): Delete definition.
2478         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2479         (sim_close): Delete code writing profile histogram.
2480         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2481         Delete.
2482         (sim_engine_run): Delete code profiling the PC.
2483
2484 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2485
2486         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2487
2488         * interp.c (sim_monitor): Make register pointers of type
2489         unsigned_word*.
2490
2491         * sim-main.h: Make registers of type unsigned_word not
2492         signed_word.
2493
2494 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2495
2496         * interp.c (sync_operation): Rename from SyncOperation, make
2497         global, add SD argument.
2498         (prefetch): Rename from Prefetch, make global, add SD argument.
2499         (decode_coproc): Make global.
2500
2501         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2502
2503         * gencode.c (build_instruction): Generate DecodeCoproc not
2504         decode_coproc calls.
2505
2506         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2507         (SizeFGR): Move to sim-main.h
2508         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2509         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2510         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2511         sim-main.h.
2512         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2513         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2514         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2515         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2516         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2517         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2518
2519         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2520         exception.
2521         (sim-alu.h): Include.
2522         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2523         (sim_cia): Typedef to instruction_address.
2524
2525 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2526
2527         * Makefile.in (interp.o): Rename generated file engine.c to
2528         oengine.c.
2529
2530         * interp.c: Update.
2531
2532 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2533
2534         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2535
2536 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2537
2538         * gencode.c (build_instruction): For "FPSQRT", output correct
2539         number of arguments to Recip.
2540
2541 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2542
2543         * Makefile.in (interp.o): Depends on sim-main.h
2544
2545         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2546
2547         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2548         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2549         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2550         STATE, DSSTATE): Define
2551         (GPR, FGRIDX, ..): Define.
2552
2553         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2554         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2555         (GPR, FGRIDX, ...): Delete macros.
2556
2557         * interp.c: Update names to match defines from sim-main.h
2558
2559 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2560
2561         * interp.c (sim_monitor): Add SD argument.
2562         (sim_warning): Delete.  Replace calls with calls to
2563         sim_io_eprintf.
2564         (sim_error): Delete. Replace calls with sim_io_error.
2565         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2566         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2567         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2568         argument.
2569         (mips_size): Rename from sim_size. Add SD argument.
2570
2571         * interp.c (simulator): Delete global variable.
2572         (callback): Delete global variable.
2573         (mips_option_handler, sim_open, sim_write, sim_read,
2574         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2575         sim_size,sim_monitor): Use sim_io_* not callback->*.
2576         (sim_open): ZALLOC simulator struct.
2577         (PROFILE): Do not define.
2578
2579 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2580
2581         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2582         support.h with corresponding code.
2583
2584         * sim-main.h (word64, uword64), support.h: Move definition to
2585         sim-main.h.
2586         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2587
2588         * support.h: Delete
2589         * Makefile.in: Update dependencies
2590         * interp.c: Do not include.
2591
2592 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2593
2594         * interp.c (address_translation, load_memory, store_memory,
2595         cache_op): Rename to from AddressTranslation et.al., make global,
2596         add SD argument
2597
2598         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2599         CacheOp): Define.
2600
2601         * interp.c (SignalException): Rename to signal_exception, make
2602         global.
2603
2604         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2605
2606         * sim-main.h (SignalException, SignalExceptionInterrupt,
2607         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2608         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2609         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2610         Define.
2611
2612         * interp.c, support.h: Use.
2613
2614 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2615
2616         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2617         to value_fpr / store_fpr. Add SD argument.
2618         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2619         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2620
2621         * sim-main.h (ValueFPR, StoreFPR): Define.
2622
2623 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2624
2625         * interp.c (sim_engine_run): Check consistency between configure
2626         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2627         and HASFPU.
2628
2629         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2630         (mips_fpu): Configure WITH_FLOATING_POINT.
2631         (mips_endian): Configure WITH_TARGET_ENDIAN.
2632         * configure: Update.
2633
2634 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2635
2636         * configure: Regenerated to track ../common/aclocal.m4 changes.
2637
2638 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2639
2640         * configure: Regenerated.
2641
2642 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2643
2644         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2645
2646 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2647
2648         * gencode.c (print_igen_insn_models): Assume certain architectures
2649         include all mips* instructions.
2650         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2651         instruction.
2652
2653         * Makefile.in (tmp.igen): Add target. Generate igen input from
2654         gencode file.
2655
2656         * gencode.c (FEATURE_IGEN): Define.
2657         (main): Add --igen option.  Generate output in igen format.
2658         (process_instructions): Format output according to igen option.
2659         (print_igen_insn_format): New function.
2660         (print_igen_insn_models): New function.
2661         (process_instructions): Only issue warnings and ignore
2662         instructions when no FEATURE_IGEN.
2663
2664 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2665
2666         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2667         MIPS targets.
2668
2669 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2670
2671         * configure: Regenerated to track ../common/aclocal.m4 changes.
2672
2673 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2674
2675         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2676         SIM_RESERVED_BITS): Delete, moved to common.
2677         (SIM_EXTRA_CFLAGS): Update.
2678
2679 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2680
2681         * configure.in: Configure non-strict memory alignment.
2682         * configure: Regenerated to track ../common/aclocal.m4 changes.
2683
2684 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2685
2686         * configure: Regenerated to track ../common/aclocal.m4 changes.
2687
2688 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2689
2690         * gencode.c (SDBBP,DERET): Added (3900) insns.
2691         (RFE): Turn on for 3900.
2692         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2693         (dsstate): Made global.
2694         (SUBTARGET_R3900): Added.
2695         (CANCELDELAYSLOT): New.
2696         (SignalException): Ignore SystemCall rather than ignore and
2697         terminate.  Add DebugBreakPoint handling.
2698         (decode_coproc): New insns RFE, DERET; and new registers Debug
2699         and DEPC protected by SUBTARGET_R3900.
2700         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2701         bits explicitly.
2702         * Makefile.in,configure.in: Add mips subtarget option.
2703         * configure: Update.
2704
2705 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2706
2707         * gencode.c: Add r3900 (tx39).
2708
2709
2710 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2711
2712         * gencode.c (build_instruction): Don't need to subtract 4 for
2713         JALR, just 2.
2714
2715 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2716
2717         * interp.c: Correct some HASFPU problems.
2718
2719 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2720
2721         * configure: Regenerated to track ../common/aclocal.m4 changes.
2722
2723 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2724
2725         * interp.c (mips_options): Fix samples option short form, should
2726         be `x'.
2727
2728 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2729
2730         * interp.c (sim_info): Enable info code.  Was just returning.
2731
2732 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2733
2734         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2735         MFC0.
2736
2737 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2738
2739         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2740         constants.
2741         (build_instruction): Ditto for LL.
2742
2743 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2744
2745         * configure: Regenerated to track ../common/aclocal.m4 changes.
2746
2747 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2748
2749         * configure: Regenerated to track ../common/aclocal.m4 changes.
2750         * config.in: Ditto.
2751
2752 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2753
2754         * interp.c (sim_open): Add call to sim_analyze_program, update
2755         call to sim_config.
2756
2757 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2758
2759         * interp.c (sim_kill): Delete.
2760         (sim_create_inferior): Add ABFD argument. Set PC from same.
2761         (sim_load): Move code initializing trap handlers from here.
2762         (sim_open): To here.
2763         (sim_load): Delete, use sim-hload.c.
2764
2765         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2766
2767 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2768
2769         * configure: Regenerated to track ../common/aclocal.m4 changes.
2770         * config.in: Ditto.
2771
2772 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2773
2774         * interp.c (sim_open): Add ABFD argument.
2775         (sim_load): Move call to sim_config from here.
2776         (sim_open): To here.  Check return status.
2777
2778 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2779
2780         * gencode.c (build_instruction): Two arg MADD should
2781         not assign result to $0.
2782
2783 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2784
2785         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2786         * sim/mips/configure.in: Regenerate.
2787
2788 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2789
2790         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2791         signed8, unsigned8 et.al. types.
2792
2793         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2794         hosts when selecting subreg.
2795
2796 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2797
2798         * interp.c (sim_engine_run): Reset the ZERO register to zero
2799         regardless of FEATURE_WARN_ZERO.
2800         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2801
2802 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2803
2804         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2805         (SignalException): For BreakPoints ignore any mode bits and just
2806         save the PC.
2807         (SignalException): Always set the CAUSE register.
2808
2809 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2810
2811         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2812         exception has been taken.
2813
2814         * interp.c: Implement the ERET and mt/f sr instructions.
2815
2816 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2817
2818         * interp.c (SignalException): Don't bother restarting an
2819         interrupt.
2820
2821 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2822
2823         * interp.c (SignalException): Really take an interrupt.
2824         (interrupt_event): Only deliver interrupts when enabled.
2825
2826 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2827
2828         * interp.c (sim_info): Only print info when verbose.
2829         (sim_info) Use sim_io_printf for output.
2830
2831 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2832
2833         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2834         mips architectures.
2835
2836 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2837
2838         * interp.c (sim_do_command): Check for common commands if a
2839         simulator specific command fails.
2840
2841 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2842
2843         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2844         and simBE when DEBUG is defined.
2845
2846 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2847
2848         * interp.c (interrupt_event): New function.  Pass exception event
2849         onto exception handler.
2850
2851         * configure.in: Check for stdlib.h.
2852         * configure: Regenerate.
2853
2854         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2855         variable declaration.
2856         (build_instruction): Initialize memval1.
2857         (build_instruction): Add UNUSED attribute to byte, bigend,
2858         reverse.
2859         (build_operands): Ditto.
2860
2861         * interp.c: Fix GCC warnings.
2862         (sim_get_quit_code): Delete.
2863
2864         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2865         * Makefile.in: Ditto.
2866         * configure: Re-generate.
2867
2868         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2869
2870 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2871
2872         * interp.c (mips_option_handler): New function parse argumes using
2873         sim-options.
2874         (myname): Replace with STATE_MY_NAME.
2875         (sim_open): Delete check for host endianness - performed by
2876         sim_config.
2877         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2878         (sim_open): Move much of the initialization from here.
2879         (sim_load): To here.  After the image has been loaded and
2880         endianness set.
2881         (sim_open): Move ColdReset from here.
2882         (sim_create_inferior): To here.
2883         (sim_open): Make FP check less dependant on host endianness.
2884
2885         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2886         run.
2887         * interp.c (sim_set_callbacks): Delete.
2888
2889         * interp.c (membank, membank_base, membank_size): Replace with
2890         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2891         (sim_open): Remove call to callback->init. gdb/run do this.
2892
2893         * interp.c: Update
2894
2895         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2896
2897         * interp.c (big_endian_p): Delete, replaced by
2898         current_target_byte_order.
2899
2900 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2901
2902         * interp.c (host_read_long, host_read_word, host_swap_word,
2903         host_swap_long): Delete. Using common sim-endian.
2904         (sim_fetch_register, sim_store_register): Use H2T.
2905         (pipeline_ticks): Delete.  Handled by sim-events.
2906         (sim_info): Update.
2907         (sim_engine_run): Update.
2908
2909 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2910
2911         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2912         reason from here.
2913         (SignalException): To here. Signal using sim_engine_halt.
2914         (sim_stop_reason): Delete, moved to common.
2915
2916 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2917
2918         * interp.c (sim_open): Add callback argument.
2919         (sim_set_callbacks): Delete SIM_DESC argument.
2920         (sim_size): Ditto.
2921
2922 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2923
2924         * Makefile.in (SIM_OBJS): Add common modules.
2925
2926         * interp.c (sim_set_callbacks): Also set SD callback.
2927         (set_endianness, xfer_*, swap_*): Delete.
2928         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2929         Change to functions using sim-endian macros.
2930         (control_c, sim_stop): Delete, use common version.
2931         (simulate): Convert into.
2932         (sim_engine_run): This function.
2933         (sim_resume): Delete.
2934
2935         * interp.c (simulation): New variable - the simulator object.
2936         (sim_kind): Delete global - merged into simulation.
2937         (sim_load): Cleanup.  Move PC assignment from here.
2938         (sim_create_inferior): To here.
2939
2940         * sim-main.h: New file.
2941         * interp.c (sim-main.h): Include.
2942
2943 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2944
2945         * configure: Regenerated to track ../common/aclocal.m4 changes.
2946
2947 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2948
2949         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2950
2951 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2952
2953         * gencode.c (build_instruction): DIV instructions: check
2954         for division by zero and integer overflow before using
2955         host's division operation.
2956
2957 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2958
2959         * Makefile.in (SIM_OBJS): Add sim-load.o.
2960         * interp.c: #include bfd.h.
2961         (target_byte_order): Delete.
2962         (sim_kind, myname, big_endian_p): New static locals.
2963         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2964         after argument parsing.  Recognize -E arg, set endianness accordingly.
2965         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2966         load file into simulator.  Set PC from bfd.
2967         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2968         (set_endianness): Use big_endian_p instead of target_byte_order.
2969
2970 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2971
2972         * interp.c (sim_size): Delete prototype - conflicts with
2973         definition in remote-sim.h.  Correct definition.
2974
2975 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2976
2977         * configure: Regenerated to track ../common/aclocal.m4 changes.
2978         * config.in: Ditto.
2979
2980 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2981
2982         * interp.c (sim_open): New arg `kind'.
2983
2984         * configure: Regenerated to track ../common/aclocal.m4 changes.
2985
2986 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2987
2988         * configure: Regenerated to track ../common/aclocal.m4 changes.
2989
2990 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2991
2992         * interp.c (sim_open): Set optind to 0 before calling getopt.
2993
2994 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2995
2996         * configure: Regenerated to track ../common/aclocal.m4 changes.
2997
2998 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2999
3000         * interp.c : Replace uses of pr_addr with pr_uword64
3001         where the bit length is always 64 independent of SIM_ADDR.
3002         (pr_uword64) : added.
3003
3004 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
3005
3006         * configure: Re-generate.
3007
3008 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
3009
3010         * configure: Regenerate to track ../common/aclocal.m4 changes.
3011
3012 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
3013
3014         * interp.c (sim_open): New SIM_DESC result.  Argument is now
3015         in argv form.
3016         (other sim_*): New SIM_DESC argument.
3017
3018 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
3019
3020         * interp.c: Fix printing of addresses for non-64-bit targets.
3021         (pr_addr): Add function to print address based on size.
3022
3023 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
3024
3025         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3026
3027 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
3028
3029         * gencode.c (build_mips16_operands): Correct computation of base
3030         address for extended PC relative instruction.
3031
3032 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
3033
3034         * interp.c (mips16_entry): Add support for floating point cases.
3035         (SignalException): Pass floating point cases to mips16_entry.
3036         (ValueFPR): Don't restrict fmt_single and fmt_word to even
3037         registers.
3038         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
3039         or fmt_word.
3040         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3041         and then set the state to fmt_uninterpreted.
3042         (COP_SW): Temporarily set the state to fmt_word while calling
3043         ValueFPR.
3044
3045 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
3046
3047         * gencode.c (build_instruction): The high order may be set in the
3048         comparison flags at any ISA level, not just ISA 4.
3049
3050 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
3051
3052         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3053         COMMON_{PRE,POST}_CONFIG_FRAG instead.
3054         * configure.in: sinclude ../common/aclocal.m4.
3055         * configure: Regenerated.
3056
3057 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
3058
3059         * configure: Rebuild after change to aclocal.m4.
3060
3061 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
3062
3063         * configure configure.in Makefile.in:  Update to new configure
3064         scheme which is more compatible with WinGDB builds.
3065         * configure.in:  Improve comment on how to run autoconf.
3066         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
3067         * Makefile.in:  Use autoconf substitution to install common
3068         makefile fragment.
3069
3070 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
3071
3072         * gencode.c (build_instruction): Use BigEndianCPU instead of
3073         ByteSwapMem.
3074
3075 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
3076
3077         * interp.c (sim_monitor): Make output to stdout visible in
3078         wingdb's I/O log window.
3079
3080 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
3081
3082         * support.h: Undo previous change to SIGTRAP
3083         and SIGQUIT values.
3084
3085 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
3086
3087         * interp.c (store_word, load_word): New static functions.
3088         (mips16_entry): New static function.
3089         (SignalException): Look for mips16 entry and exit instructions.
3090         (simulate): Use the correct index when setting fpr_state after
3091         doing a pending move.
3092
3093 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
3094
3095         * interp.c: Fix byte-swapping code throughout to work on
3096         both little- and big-endian hosts.
3097
3098 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
3099
3100         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3101         with gdb/config/i386/xm-windows.h.
3102
3103 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
3104
3105         * gencode.c (build_instruction): Work around MSVC++ code gen bug
3106         that messes up arithmetic shifts.
3107
3108 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
3109
3110         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
3111         SIGTRAP and SIGQUIT for _WIN32.
3112
3113 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
3114
3115         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3116         force a 64 bit multiplication.
3117         (build_instruction) [OR]: In mips16 mode, don't do anything if the
3118         destination register is 0, since that is the default mips16 nop
3119         instruction.
3120
3121 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
3122
3123         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3124         (build_endian_shift): Don't check proc64.
3125         (build_instruction): Always set memval to uword64.  Cast op2 to
3126         uword64 when shifting it left in memory instructions.  Always use
3127         the same code for stores--don't special case proc64.
3128
3129         * gencode.c (build_mips16_operands): Fix base PC value for PC
3130         relative operands.
3131         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3132         jal instruction.
3133         * interp.c (simJALDELAYSLOT): Define.
3134         (JALDELAYSLOT): Define.
3135         (INDELAYSLOT, INJALDELAYSLOT): Define.
3136         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3137
3138 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
3139
3140         * interp.c (sim_open): add flush_cache as a PMON routine
3141         (sim_monitor): handle flush_cache by ignoring it
3142
3143 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
3144
3145         * gencode.c (build_instruction): Use !ByteSwapMem instead of
3146         BigEndianMem.
3147         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3148         (BigEndianMem): Rename to ByteSwapMem and change sense.
3149         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3150         BigEndianMem references to !ByteSwapMem.
3151         (set_endianness): New function, with prototype.
3152         (sim_open): Call set_endianness.
3153         (sim_info): Use simBE instead of BigEndianMem.
3154         (xfer_direct_word, xfer_direct_long, swap_direct_word,
3155         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3156         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3157         ifdefs, keeping the prototype declaration.
3158         (swap_word): Rewrite correctly.
3159         (ColdReset): Delete references to CONFIG.  Delete endianness related
3160         code; moved to set_endianness.
3161
3162 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
3163
3164         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3165         * interp.c (CHECKHILO): Define away.
3166         (simSIGINT): New macro.
3167         (membank_size): Increase from 1MB to 2MB.
3168         (control_c): New function.
3169         (sim_resume): Rename parameter signal to signal_number.  Add local
3170         variable prev.  Call signal before and after simulate.
3171         (sim_stop_reason): Add simSIGINT support.
3172         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3173         functions always.
3174         (sim_warning): Delete call to SignalException.  Do call printf_filtered
3175         if logfh is NULL.
3176         (AddressTranslation): Add #ifdef DEBUG around debugging message and
3177         a call to sim_warning.
3178
3179 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
3180
3181         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3182         16 bit instructions.
3183
3184 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3185
3186         Add support for mips16 (16 bit MIPS implementation):
3187         * gencode.c (inst_type): Add mips16 instruction encoding types.
3188         (GETDATASIZEINSN): Define.
3189         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
3190         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
3191         mtlo.
3192         (MIPS16_DECODE): New table, for mips16 instructions.
3193         (bitmap_val): New static function.
3194         (struct mips16_op): Define.
3195         (mips16_op_table): New table, for mips16 operands.
3196         (build_mips16_operands): New static function.
3197         (process_instructions): If PC is odd, decode a mips16
3198         instruction.  Break out instruction handling into new
3199         build_instruction function.
3200         (build_instruction): New static function, broken out of
3201         process_instructions.  Check modifiers rather than flags for SHIFT
3202         bit count and m[ft]{hi,lo} direction.
3203         (usage): Pass program name to fprintf.
3204         (main): Remove unused variable this_option_optind.  Change
3205         ``*loptarg++'' to ``loptarg++''.
3206         (my_strtoul): Parenthesize && within ||.
3207         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3208         (simulate): If PC is odd, fetch a 16 bit instruction, and
3209         increment PC by 2 rather than 4.
3210         * configure.in: Add case for mips16*-*-*.
3211         * configure: Rebuild.
3212
3213 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
3214
3215         * interp.c: Allow -t to enable tracing in standalone simulator.
3216         Fix garbage output in trace file and error messages.
3217
3218 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
3219
3220         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3221         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3222         * configure.in: Simplify using macros in ../common/aclocal.m4.
3223         * configure: Regenerated.
3224         * tconfig.in: New file.
3225
3226 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3227
3228         * interp.c: Fix bugs in 64-bit port.
3229         Use ansi function declarations for msvc compiler.
3230         Initialize and test file pointer in trace code.
3231         Prevent duplicate definition of LAST_EMED_REGNUM.
3232
3233 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3234
3235         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3236
3237 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3238
3239         * interp.c (SignalException): Check for explicit terminating
3240         breakpoint value.
3241         * gencode.c: Pass instruction value through SignalException()
3242         calls for Trap, Breakpoint and Syscall.
3243
3244 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3245
3246         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3247         only used on those hosts that provide it.
3248         * configure.in: Add sqrt() to list of functions to be checked for.
3249         * config.in: Re-generated.
3250         * configure: Re-generated.
3251
3252 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3253
3254         * gencode.c (process_instructions): Call build_endian_shift when
3255         expanding STORE RIGHT, to fix swr.
3256         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3257         clear the high bits.
3258         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3259         Fix float to int conversions to produce signed values.
3260
3261 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3262
3263         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3264         (process_instructions): Correct handling of nor instruction.
3265         Correct shift count for 32 bit shift instructions. Correct sign
3266         extension for arithmetic shifts to not shift the number of bits in
3267         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3268         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3269         Fix madd.
3270         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3271         It's OK to have a mult follow a mult.  What's not OK is to have a
3272         mult follow an mfhi.
3273         (Convert): Comment out incorrect rounding code.
3274
3275 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3276
3277         * interp.c (sim_monitor): Improved monitor printf
3278         simulation. Tidied up simulator warnings, and added "--log" option
3279         for directing warning message output.
3280         * gencode.c: Use sim_warning() rather than WARNING macro.
3281
3282 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3283
3284         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3285         getopt1.o, rather than on gencode.c.  Link objects together.
3286         Don't link against -liberty.
3287         (gencode.o, getopt.o, getopt1.o): New targets.
3288         * gencode.c: Include <ctype.h> and "ansidecl.h".
3289         (AND): Undefine after including "ansidecl.h".
3290         (ULONG_MAX): Define if not defined.
3291         (OP_*): Don't define macros; now defined in opcode/mips.h.
3292         (main): Call my_strtoul rather than strtoul.
3293         (my_strtoul): New static function.
3294
3295 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3296
3297         * gencode.c (process_instructions):  Generate word64 and uword64
3298         instead of `long long' and `unsigned long long' data types.
3299         * interp.c:  #include sysdep.h to get signals, and define default
3300         for SIGBUS.
3301         * (Convert):  Work around for Visual-C++ compiler bug with type
3302         conversion.
3303         * support.h:  Make things compile under Visual-C++ by using
3304         __int64 instead of `long long'.  Change many refs to long long
3305         into word64/uword64 typedefs.
3306
3307 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3308
3309         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3310         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3311         (docdir): Removed.
3312         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3313         (AC_PROG_INSTALL): Added.
3314         (AC_PROG_CC): Moved to before configure.host call.
3315         * configure: Rebuilt.
3316
3317 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3318
3319         * configure.in: Define @SIMCONF@ depending on mips target.
3320         * configure: Rebuild.
3321         * Makefile.in (run): Add @SIMCONF@ to control simulator
3322         construction.
3323         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3324         * interp.c: Remove some debugging, provide more detailed error
3325         messages, update memory accesses to use LOADDRMASK.
3326
3327 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3328
3329         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3330         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3331         stamp-h.
3332         * configure: Rebuild.
3333         * config.in: New file, generated by autoheader.
3334         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3335         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3336         HAVE_ANINT and HAVE_AINT, as appropriate.
3337         * Makefile.in (run): Use @LIBS@ rather than -lm.
3338         (interp.o): Depend upon config.h.
3339         (Makefile): Just rebuild Makefile.
3340         (clean): Remove stamp-h.
3341         (mostlyclean): Make the same as clean, not as distclean.
3342         (config.h, stamp-h): New targets.
3343
3344 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3345
3346         * interp.c (ColdReset): Fix boolean test. Make all simulator
3347         globals static.
3348
3349 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3350
3351         * interp.c (xfer_direct_word, xfer_direct_long,
3352         swap_direct_word, swap_direct_long, xfer_big_word,
3353         xfer_big_long, xfer_little_word, xfer_little_long,
3354         swap_word,swap_long): Added.
3355         * interp.c (ColdReset): Provide function indirection to
3356         host<->simulated_target transfer routines.
3357         * interp.c (sim_store_register, sim_fetch_register): Updated to
3358         make use of indirected transfer routines.
3359
3360 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3361
3362         * gencode.c (process_instructions): Ensure FP ABS instruction
3363         recognised.
3364         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3365         system call support.
3366
3367 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3368
3369         * interp.c (sim_do_command): Complain if callback structure not
3370         initialised.
3371
3372 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3373
3374         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3375         support for Sun hosts.
3376         * Makefile.in (gencode): Ensure the host compiler and libraries
3377         used for cross-hosted build.
3378
3379 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3380
3381         * interp.c, gencode.c: Some more (TODO) tidying.
3382
3383 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3384
3385         * gencode.c, interp.c: Replaced explicit long long references with
3386         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3387         * support.h (SET64LO, SET64HI): Macros added.
3388
3389 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3390
3391         * configure: Regenerate with autoconf 2.7.
3392
3393 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3394
3395         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3396         * support.h: Remove superfluous "1" from #if.
3397         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3398
3399 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3400
3401         * interp.c (StoreFPR): Control UndefinedResult() call on
3402         WARN_RESULT manifest.
3403
3404 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3405
3406         * gencode.c: Tidied instruction decoding, and added FP instruction
3407         support.
3408
3409         * interp.c: Added dineroIII, and BSD profiling support. Also
3410         run-time FP handling.
3411
3412 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3413
3414         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3415         gencode.c, interp.c, support.h: created.