sim/mips/ChangeLog

   1 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
   2
   3         * configure: Regenerated.
   4
   5 2006-05-15 Chao-ying Fu  <fu@mips.com>
   6
   7         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
   8
   9 2006-04-18  Nick Clifton  <nickc@redhat.com>
  10
  11         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
  12         statement.
  13
  14 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
  15
  16         * configure: Regenerate.
  17
  18 2005-12-14  Chao-ying Fu  <fu@mips.com>
  19
  20         * Makefile.in (SIM_OBJS): Add dsp.o.
  21         (dsp.o): New dependency.
  22         (IGEN_INCLUDE): Add dsp.igen.
  23         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
  24         mipsisa64*-*-*): Add dsp to sim_igen_machine.
  25         * configure: Regenerate.
  26         * mips.igen: Add dsp model and include dsp.igen.
  27         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
  28         because these instructions are extended in DSP ASE.
  29         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
  30         adding 6 DSP accumulator registers and 1 DSP control register.
  31         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
  32         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
  33         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
  34         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
  35         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
  36         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
  37         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
  38         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
  39         DSPCR_CCOND_SMASK): New define.
  40         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
  41         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
  42
  43 2005-07-08  Ian Lance Taylor  <ian@airs.com>
  44
  45         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
  46
  47 2005-06-16  David Ung  <davidu@mips.com>
  48             Nigel Stephens  <nigel@mips.com>
  49
  50         * mips.igen: New mips16e model and include m16e.igen.
  51         (check_u64): Add mips16e tag.
  52         * m16e.igen: New file for MIPS16e instructions.
  53         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
  54         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
  55         models.
  56         * configure: Regenerate.
  57
  58 2005-05-26  David Ung  <davidu@mips.com>
  59
  60         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
  61         tags to all instructions which are applicable to the new ISAs.
  62         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
  63         vr.igen.
  64         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
  65         instructions.
  66         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
  67         to mips.igen.
  68         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
  69         * configure: Regenerate.
  70
  71 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
  72
  73         * configure: Regenerate.
  74
  75 2005-01-14  Andrew Cagney  <cagney@gnu.org>
  76
  77         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
  78         explicit call to AC_CONFIG_HEADER.
  79         * configure: Regenerate.
  80
  81 2005-01-12  Andrew Cagney  <cagney@gnu.org>
  82
  83         * configure.ac: Update to use ../common/common.m4.
  84         * configure: Re-generate.
  85
  86 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
  87
  88         * configure: Regenerated to track ../common/aclocal.m4 changes.
  89
  90 2005-01-07  Andrew Cagney  <cagney@gnu.org>
  91
  92         * configure.ac: Rename configure.in, require autoconf 2.59.
  93         * configure: Re-generate.
  94
  95 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
  96
  97         * configure: Regenerate for ../common/aclocal.m4 update.
  98
  99 2004-09-24  Monika Chaddha  <monika@acmet.com>
 100
 101         Committed by Andrew Cagney.
 102         * m16.igen (CMP, CMPI): Fix assembler.
 103
 104 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 105
 106         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 107         * configure: Regenerate.
 108
 109 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 110
 111         * configure.in (sim_m16_machine): Include mipsIII.
 112         * configure: Regenerate.
 113
 114 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 115
 116         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 117         from COP0_BADVADDR.
 118         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 119
 120 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 121
 122         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 123
 124 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 125
 126         * mips.igen (check_fmt): Remove.
 127         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 128         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 129         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 130         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 131         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 132         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 133         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 134         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 135         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 136         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 137
 138 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 139
 140         * sb1.igen (check_sbx): New function.
 141         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 142
 143 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 144             Richard Sandiford  <rsandifo@redhat.com>
 145
 146         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 147         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 148         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 149         separate implementations for mipsIV and mipsV.  Use new macros to
 150         determine whether the restrictions apply.
 151
 152 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 153
 154         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 155         (check_mult_hilo): Improve comments.
 156         (check_div_hilo): Likewise.  Also, fork off a new version
 157         to handle mips32/mips64 (since there are no hazards to check
 158         in MIPS32/MIPS64).
 159
 160 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 161
 162         * mips.igen (do_dmultx): Fix check for negative operands.
 163
 164 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 165
 166         * Makefile.in (SHELL): Make sure this is defined.
 167         (various): Use $(SHELL) whenever we invoke move-if-change.
 168
 169 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 170
 171         * cp1.c: Tweak attribution slightly.
 172         * cp1.h: Likewise.
 173         * mdmx.c: Likewise.
 174         * mdmx.igen: Likewise.
 175         * mips3d.igen: Likewise.
 176         * sb1.igen: Likewise.
 177
 178 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 179
 180         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 181         unsigned operands.
 182
 183 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 184
 185         * interp.c (sim_open): Rename _bfd to bfd.
 186         (sim_create_inferior): Ditto.
 187
 188 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 189
 190         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 191
 192 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 193
 194         * mips.igen (EI, DI): Remove.
 195
 196 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 197
 198         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 199
 200 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 201             Andrew Cagney  <ac131313@redhat.com>
 202             Gavin Romig-Koch  <gavin@redhat.com>
 203             Graydon Hoare  <graydon@redhat.com>
 204             Aldy Hernandez  <aldyh@redhat.com>
 205             Dave Brolley  <brolley@redhat.com>
 206             Chris Demetriou  <cgd@broadcom.com>
 207
 208         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 209         (sim_mach_default): New variable.
 210         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 211         Add a new simulator generator, MULTI.
 212         * configure: Regenerate.
 213         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 214         (multi-run.o): New dependency.
 215         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 216         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 217         (tmp-multi): Combine them.
 218         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 219         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 220         (distclean-extra): New rule.
 221         * sim-main.h: Include bfd.h.
 222         (MIPS_MACH): New macro.
 223         * mips.igen (vr4120, vr5400, vr5500): New models.
 224         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 225         * vr.igen: Replace with new version.
 226
 227 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 228
 229         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 230         * configure: Regenerate.
 231
 232 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 233
 234         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 235         * mips.igen: Remove all invocations of check_branch_bug and
 236         mark_branch_bug.
 237
 238 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 239
 240         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 241
 242 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 243
 244         * mips.igen (do_load_double, do_store_double): New functions.
 245         (LDC1, SDC1): Rename to...
 246         (LDC1b, SDC1b): respectively.
 247         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 248
 249 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 250
 251         * cp1.c (fp_recip2): Modify initialization expression so that
 252         GCC will recognize it as constant.
 253
 254 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 255
 256         * mdmx.c (SD_): Delete.
 257         (Unpredictable): Re-define, for now, to directly invoke
 258         unpredictable_action().
 259         (mdmx_acc_op): Fix error in .ob immediate handling.
 260
 261 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 262
 263         * interp.c (sim_firmware_command): Initialize `address'.
 264
 265 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 266
 267         * configure: Regenerated to track ../common/aclocal.m4 changes.
 268
 269 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 270             Ed Satterthwaite  <ehs@broadcom.com>
 271
 272         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 273         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 274         * mips.igen: Include mips3d.igen.
 275         (mips3d): New model name for MIPS-3D ASE instructions.
 276         (CVT.W.fmt): Don't use this instruction for word (source) format
 277         instructions.
 278         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 279         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 280         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 281         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 282         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 283         (RSquareRoot1, RSquareRoot2): New macros.
 284         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 285         (fp_rsqrt2): New functions.
 286         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 287         * configure: Regenerate.
 288
 289 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 290             Ed Satterthwaite  <ehs@broadcom.com>
 291
 292         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 293         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 294         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 295         (convert): Note that this function is not used for paired-single
 296         format conversions.
 297         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 298         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 299         (check_fmt_p): Enable paired-single support.
 300         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 301         (PUU.PS): New instructions.
 302         (CVT.S.fmt): Don't use this instruction for paired-single format
 303         destinations.
 304         * sim-main.h (FP_formats): New value 'fmt_ps.'
 305         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 306         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 307
 308 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 309
 310         * mips.igen: Fix formatting of function calls in
 311         many FP operations.
 312
 313 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 314
 315         * mips.igen (MOVN, MOVZ): Trace result.
 316         (TNEI): Print "tnei" as the opcode name in traces.
 317         (CEIL.W): Add disassembly string for traces.
 318         (RSQRT.fmt): Make location of disassembly string consistent
 319         with other instructions.
 320
 321 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 322
 323         * mips.igen (X): Delete unused function.
 324
 325 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 326
 327         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 328
 329 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 330             Ed Satterthwaite  <ehs@broadcom.com>
 331
 332         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 333         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 334         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 335         (fp_nmsub): New prototypes.
 336         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 337         (NegMultiplySub): New defines.
 338         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 339         (MADD.D, MADD.S): Replace with...
 340         (MADD.fmt): New instruction.
 341         (MSUB.D, MSUB.S): Replace with...
 342         (MSUB.fmt): New instruction.
 343         (NMADD.D, NMADD.S): Replace with...
 344         (NMADD.fmt): New instruction.
 345         (NMSUB.D, MSUB.S): Replace with...
 346         (NMSUB.fmt): New instruction.
 347
 348 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 349             Ed Satterthwaite  <ehs@broadcom.com>
 350
 351         * cp1.c: Fix more comment spelling and formatting.
 352         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 353         (denorm_mode): New function.
 354         (fpu_unary, fpu_binary): Round results after operation, collect
 355         status from rounding operations, and update the FCSR.
 356         (convert): Collect status from integer conversions and rounding
 357         operations, and update the FCSR.  Adjust NaN values that result
 358         from conversions.  Convert to use sim_io_eprintf rather than
 359         fprintf, and remove some debugging code.
 360         * cp1.h (fenr_FS): New define.
 361
 362 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 363
 364         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 365         rounding mode to sim FP rounding mode flag conversion code into...
 366         (rounding_mode): New function.
 367
 368 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 369
 370         * cp1.c: Clean up formatting of a few comments.
 371         (value_fpr): Reformat switch statement.
 372
 373 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 374             Ed Satterthwaite  <ehs@broadcom.com>
 375
 376         * cp1.h: New file.
 377         * sim-main.h: Include cp1.h.
 378         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 379         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 380         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 381         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 382         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 383         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 384         * cp1.c: Don't include sim-fpu.h; already included by
 385         sim-main.h.  Clean up formatting of some comments.
 386         (NaN, Equal, Less): Remove.
 387         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 388         (fp_cmp): New functions.
 389         * mips.igen (do_c_cond_fmt): Remove.
 390         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 391         Compare.  Add result tracing.
 392         (CxC1): Remove, replace with...
 393         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 394         (DMxC1): Remove, replace with...
 395         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 396         (MxC1): Remove, replace with...
 397         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 398
 399 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 400
 401         * sim-main.h (FGRIDX): Remove, replace all uses with...
 402         (FGR_BASE): New macro.
 403         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 404         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 405         (NR_FGR, FGR): Likewise.
 406         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 407         * mips.igen: Likewise.
 408
 409 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * cp1.c: Add an FSF Copyright notice to this file.
 412
 413 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 414             Ed Satterthwaite  <ehs@broadcom.com>
 415
 416         * cp1.c (Infinity): Remove.
 417         * sim-main.h (Infinity): Likewise.
 418
 419         * cp1.c (fp_unary, fp_binary): New functions.
 420         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 421         (fp_sqrt): New functions, implemented in terms of the above.
 422         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 423         (Recip, SquareRoot): Remove (replaced by functions above).
 424         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 425         (fp_recip, fp_sqrt): New prototypes.
 426         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 427         (Recip, SquareRoot): Replace prototypes with #defines which
 428         invoke the functions above.
 429
 430 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 431
 432         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 433         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 434         file, remove PARAMS from prototypes.
 435         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 436         simulator state arguments.
 437         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 438         pass simulator state arguments.
 439         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 440         (store_fpr, convert): Remove 'sd' argument.
 441         (value_fpr): Likewise.  Convert to use 'SD' instead.
 442
 443 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 444
 445         * cp1.c (Min, Max): Remove #if 0'd functions.
 446         * sim-main.h (Min, Max): Remove.
 447
 448 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 449
 450         * cp1.c: fix formatting of switch case and default labels.
 451         * interp.c: Likewise.
 452         * sim-main.c: Likewise.
 453
 454 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 455
 456         * cp1.c: Clean up comments which describe FP formats.
 457          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 458
 459 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 460             Ed Satterthwaite  <ehs@broadcom.com>
 461
 462         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 463         Broadcom SiByte SB-1 processor configurations.
 464         * configure: Regenerate.
 465         * sb1.igen: New file.
 466         * mips.igen: Include sb1.igen.
 467         (sb1): New model.
 468         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 469         * mdmx.igen: Add "sb1" model to all appropriate functions and
 470         instructions.
 471         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 472         (ob_func, ob_acc): Reference the above.
 473         (qh_acc): Adjust to keep the same size as ob_acc.
 474         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 475         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 476
 477 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 478
 479         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 480
 481 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 482             Ed Satterthwaite  <ehs@broadcom.com>
 483
 484         * mips.igen (mdmx): New (pseudo-)model.
 485         * mdmx.c, mdmx.igen: New files.
 486         * Makefile.in (SIM_OBJS): Add mdmx.o.
 487         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 488         New typedefs.
 489         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 490         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 491         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 492         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 493         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 494         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 495         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 496         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 497         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 498         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 499         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 500         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 501         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 502         (qh_fmtsel): New macros.
 503         (_sim_cpu): New member "acc".
 504         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 505         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 506
 507 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 508
 509         * interp.c: Use 'deprecated' rather than 'depreciated.'
 510         * sim-main.h: Likewise.
 511
 512 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 513
 514         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 515         which wouldn't compile anyway.
 516         * sim-main.h (unpredictable_action): New function prototype.
 517         (Unpredictable): Define to call igen function unpredictable().
 518         (NotWordValue): New macro to call igen function not_word_value().
 519         (UndefinedResult): Remove.
 520         * interp.c (undefined_result): Remove.
 521         (unpredictable_action): New function.
 522         * mips.igen (not_word_value, unpredictable): New functions.
 523         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 524         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 525         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 526         NotWordValue() to check for unpredictable inputs, then
 527         Unpredictable() to handle them.
 528
 529 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 530
 531         * mips.igen: Fix formatting of calls to Unpredictable().
 532
 533 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 534
 535         * interp.c (sim_open): Revert previous change.
 536
 537 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 538
 539         * interp.c (sim_open): Disable chunk of code that wrote code in
 540         vector table entries.
 541
 542 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 543
 544         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 545         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 546         unused definitions.
 547
 548 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 549
 550         * cp1.c: Fix many formatting issues.
 551
 552 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 553
 554         * cp1.c (fpu_format_name): New function to replace...
 555         (DOFMT): This.  Delete, and update all callers.
 556         (fpu_rounding_mode_name): New function to replace...
 557         (RMMODE): This.  Delete, and update all callers.
 558
 559 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 560
 561         * interp.c: Move FPU support routines from here to...
 562         * cp1.c: Here.  New file.
 563         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 564         (cp1.o): New target.
 565
 566 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 567
 568         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 569         * mips.igen (mips32, mips64): New models, add to all instructions
 570         and functions as appropriate.
 571         (loadstore_ea, check_u64): New variant for model mips64.
 572         (check_fmt_p): New variant for models mipsV and mips64, remove
 573         mipsV model marking fro other variant.
 574         (SLL) Rename to...
 575         (SLLa) this.
 576         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 577         for mips32 and mips64.
 578         (DCLO, DCLZ): New instructions for mips64.
 579
 580 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 581
 582         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 583         immediate or code as a hex value with the "%#lx" format.
 584         (ANDI): Likewise, and fix printed instruction name.
 585
 586 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 587
 588         * sim-main.h (UndefinedResult, Unpredictable): New macros
 589         which currently do nothing.
 590
 591 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 592
 593         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 594         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 595         (status_CU3): New definitions.
 596
 597         * sim-main.h (ExceptionCause): Add new values for MIPS32
 598         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 599         for DebugBreakPoint and NMIReset to note their status in
 600         MIPS32 and MIPS64.
 601         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 602         (SignalExceptionCacheErr): New exception macros.
 603
 604 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 605
 606         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 607         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 608         is always enabled.
 609         (SignalExceptionCoProcessorUnusable): Take as argument the
 610         unusable coprocessor number.
 611
 612 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 613
 614         * mips.igen: Fix formatting of all SignalException calls.
 615
 616 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 617
 618         * sim-main.h (SIGNEXTEND): Remove.
 619
 620 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 621
 622         * mips.igen: Remove gencode comment from top of file, fix
 623         spelling in another comment.
 624
 625 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 626
 627         * mips.igen (check_fmt, check_fmt_p): New functions to check
 628         whether specific floating point formats are usable.
 629         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 630         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 631         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 632         Use the new functions.
 633         (do_c_cond_fmt): Remove format checks...
 634         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 635
 636 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 637
 638         * mips.igen: Fix formatting of check_fpu calls.
 639
 640 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 641
 642         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 643
 644 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 645
 646         * mips.igen: Remove whitespace at end of lines.
 647
 648 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 649
 650         * mips.igen (loadstore_ea): New function to do effective
 651         address calculations.
 652         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 653         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 654         CACHE): Use loadstore_ea to do effective address computations.
 655
 656 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 657
 658         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 659         * mips.igen (LL, CxC1, MxC1): Likewise.
 660
 661 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 662
 663         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 664         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 665         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 666         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 667         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 668         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 669         Don't split opcode fields by hand, use the opcode field values
 670         provided by igen.
 671
 672 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 673
 674         * mips.igen (do_divu): Fix spacing.
 675
 676         * mips.igen (do_dsllv): Move to be right before DSLLV,
 677         to match the rest of the do_<shift> functions.
 678
 679 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 680
 681         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 682         DSRL32, do_dsrlv): Trace inputs and results.
 683
 684 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 685
 686         * mips.igen (CACHE): Provide instruction-printing string.
 687
 688         * interp.c (signal_exception): Comment tokens after #endif.
 689
 690 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 691
 692         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 693         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 694         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 695         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 696         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 697         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 698         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 699         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 700
 701 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 702
 703         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 704         instruction-printing string.
 705         (LWU): Use '64' as the filter flag.
 706
 707 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 708
 709         * mips.igen (SDXC1): Fix instruction-printing string.
 710
 711 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 712
 713         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 714         filter flags "32,f".
 715
 716 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 717
 718         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 719         as the filter flag.
 720
 721 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 722
 723         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 724         add a comma) so that it more closely match the MIPS ISA
 725         documentation opcode partitioning.
 726         (PREF): Put useful names on opcode fields, and include
 727         instruction-printing string.
 728
 729 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 730
 731         * mips.igen (check_u64): New function which in the future will
 732         check whether 64-bit instructions are usable and signal an
 733         exception if not.  Currently a no-op.
 734         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 735         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 736         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 737         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 738
 739         * mips.igen (check_fpu): New function which in the future will
 740         check whether FPU instructions are usable and signal an exception
 741         if not.  Currently a no-op.
 742         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 743         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 744         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 745         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 746         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 747         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 748         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 749         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 750
 751 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 752
 753         * mips.igen (do_load_left, do_load_right): Move to be immediately
 754         following do_load.
 755         (do_store_left, do_store_right): Move to be immediately following
 756         do_store.
 757
 758 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 759
 760         * mips.igen (mipsV): New model name.  Also, add it to
 761         all instructions and functions where it is appropriate.
 762
 763 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 764
 765         * mips.igen: For all functions and instructions, list model
 766         names that support that instruction one per line.
 767
 768 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 769
 770         * mips.igen: Add some additional comments about supported
 771         models, and about which instructions go where.
 772         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 773         order as is used in the rest of the file.
 774
 775 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 776
 777         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 778         indicating that ALU32_END or ALU64_END are there to check
 779         for overflow.
 780         (DADD): Likewise, but also remove previous comment about
 781         overflow checking.
 782
 783 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 784
 785         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 786         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 787         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 788         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 789         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 790         fields (i.e., add and move commas) so that they more closely
 791         match the MIPS ISA documentation opcode partitioning.
 792
 793 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 794
 795         * mips.igen (ADDI): Print immediate value.
 796         (BREAK): Print code.
 797         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 798         (SLL): Print "nop" specially, and don't run the code
 799         that does the shift for the "nop" case.
 800
 801 2001-11-17  Fred Fish  <fnf@redhat.com>
 802
 803         * sim-main.h (float_operation): Move enum declaration outside
 804         of _sim_cpu struct declaration.
 805
 806 2001-04-12  Jim Blandy  <jimb@redhat.com>
 807
 808         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 809         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 810         set of the FCSR.
 811         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 812         PENDING_FILL, and you can get the intended effect gracefully by
 813         calling PENDING_SCHED directly.
 814
 815 2001-02-23  Ben Elliston  <bje@redhat.com>
 816
 817         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 818         already defined elsewhere.
 819
 820 2001-02-19  Ben Elliston  <bje@redhat.com>
 821
 822         * sim-main.h (sim_monitor): Return an int.
 823         * interp.c (sim_monitor): Add return values.
 824         (signal_exception): Handle error conditions from sim_monitor.
 825
 826 2001-02-08  Ben Elliston  <bje@redhat.com>
 827
 828         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 829         (store_memory): Likewise, pass cia to sim_core_write*.
 830
 831 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 832
 833         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 834         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 835
 836 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 837
 838         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 839         * Makefile.in: Don't delete *.igen when cleaning directory.
 840
 841 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 842
 843         * m16.igen (break): Call SignalException not sim_engine_halt.
 844
 845 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 846
 847         From Jason Eckhardt:
 848         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 849
 850 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 851
 852         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 853
 854 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 855
 856         * mips.igen (do_dmultx): Fix typo.
 857
 858 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 859
 860         * configure: Regenerated to track ../common/aclocal.m4 changes.
 861
 862 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 863
 864         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 865
 866 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 867
 868         * sim-main.h (GPR_CLEAR): Define macro.
 869
 870 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 871
 872         * interp.c (decode_coproc): Output long using %lx and not %s.
 873
 874 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 875
 876         * interp.c (sim_open): Sort & extend dummy memory regions for
 877         --board=jmr3904 for eCos.
 878
 879 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 880
 881         * configure: Regenerated.
 882
 883 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 884
 885         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 886         calls, conditional on the simulator being in verbose mode.
 887
 888 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 889
 890         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 891         cache don't get ReservedInstruction traps.
 892
 893 1999-11-29  Mark Salter  <msalter@cygnus.com>
 894
 895         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 896         to clear status bits in sdisr register. This is how the hardware works.
 897
 898         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 899         being used by cygmon.
 900
 901 1999-11-11  Andrew Haley  <aph@cygnus.com>
 902
 903         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 904         instructions.
 905
 906 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 907
 908         * mips.igen (MULT): Correct previous mis-applied patch.
 909
 910 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 911
 912         * mips.igen (delayslot32): Handle sequence like
 913         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 914         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 915         (MULT): Actually pass the third register...
 916
 917 1999-09-03  Mark Salter  <msalter@cygnus.com>
 918
 919         * interp.c (sim_open): Added more memory aliases for additional
 920         hardware being touched by cygmon on jmr3904 board.
 921
 922 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 923
 924         * configure: Regenerated to track ../common/aclocal.m4 changes.
 925
 926 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 927
 928         * interp.c (sim_store_register): Handle case where client - GDB -
 929         specifies that a 4 byte register is 8 bytes in size.
 930         (sim_fetch_register): Ditto.
 931
 932 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 933
 934         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 935         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 936         (idt_monitor_base): Base address for IDT monitor traps.
 937         (pmon_monitor_base): Ditto for PMON.
 938         (lsipmon_monitor_base): Ditto for LSI PMON.
 939         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 940         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 941         (sim_firmware_command): New function.
 942         (mips_option_handler): Call it for OPTION_FIRMWARE.
 943         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 944         option was given, add no monitor by default.  Add BREAK hooks only if
 945         monitors are also there.
 946
 947 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 948
 949         * interp.c (sim_monitor): Flush output before reading input.
 950
 951 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 952
 953         * tconfig.in (SIM_HANDLES_LMA): Always define.
 954
 955 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 956
 957         From Mark Salter <msalter@cygnus.com>:
 958         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 959         (sim_open): Add setup for BSP board.
 960
 961 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 962
 963         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 964         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 965         them as unimplemented.
 966
 967 1999-05-08  Felix Lee  <flee@cygnus.com>
 968
 969         * configure: Regenerated to track ../common/aclocal.m4 changes.
 970
 971 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 972
 973         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 974
 975 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 976
 977         * configure.in: Any mips64vr5*-*-* target should have
 978         -DTARGET_ENABLE_FR=1.
 979         (default_endian): Any mips64vr*el-*-* target should default to
 980         LITTLE_ENDIAN.
 981         * configure: Re-generate.
 982
 983 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 984
 985         * mips.igen (ldl): Extend from _16_, not 32.
 986
 987 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 988
 989         * interp.c (sim_store_register): Force registers written to by GDB
 990         into an un-interpreted state.
 991
 992 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 993
 994         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 995         CPU, start periodic background I/O polls.
 996         (tx3904sio_poll): New function: periodic I/O poller.
 997
 998 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 999
1000         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1001
1002 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1003
1004         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1005         case statement.
1006
1007 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1008
1009         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1010         (load_word): Call SIM_CORE_SIGNAL hook on error.
1011         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1012         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1013         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1014         * sim-main.h (COP0_BADVADDR): Define.
1015         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1016         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1017         (_sim_cpu): Add exc_* fields to store register value snapshots.
1018         * mips.igen (*): Replace memory-related SignalException* calls
1019         with references to SIM_CORE_SIGNAL hook.
1020
1021         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1022         fix.
1023         * sim-main.c (*): Minor warning cleanups.
1024
1025 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1026
1027         * m16.igen (DADDIU5): Correct type-o.
1028
1029 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1030
1031         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1032         variables.
1033
1034 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1035
1036         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1037         to include path.
1038         (interp.o): Add dependency on itable.h
1039         (oengine.c, gencode): Delete remaining references.
1040         (BUILT_SRC_FROM_GEN): Clean up.
1041
1042 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1043
1044         * vr4run.c: New.
1045         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1046         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1047         tmp-run-hack) : New.
1048         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1049         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1050         Drop the "64" qualifier to get the HACK generator working.
1051         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1052         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1053         qualifier to get the hack generator working.
1054         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1055         (DSLL): Use do_dsll.
1056         (DSLLV): Use do_dsllv.
1057         (DSRA): Use do_dsra.
1058         (DSRL): Use do_dsrl.
1059         (DSRLV): Use do_dsrlv.
1060         (BC1): Move *vr4100 to get the HACK generator working.
1061         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1062         get the HACK generator working.
1063         (MACC) Rename to get the HACK generator working.
1064         (DMACC,MACCS,DMACCS): Add the 64.
1065
1066 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1067
1068         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1069         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1070
1071 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1072
1073     * mips/interp.c (DEBUG): Cleanups.
1074
1075 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1076
1077         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1078         (tx3904sio_tickle): fflush after a stdout character output.
1079
1080 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1081
1082         * interp.c (sim_close): Uninstall modules.
1083
1084 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1085
1086         * sim-main.h, interp.c (sim_monitor): Change to global
1087         function.
1088
1089 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1090
1091         * configure.in (vr4100): Only include vr4100 instructions in
1092         simulator.
1093         * configure: Re-generate.
1094         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1095
1096 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1097
1098         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1099         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1100         true alternative.
1101
1102         * configure.in (sim_default_gen, sim_use_gen): Replace with
1103         sim_gen.
1104         (--enable-sim-igen): Delete config option. Always using IGEN.
1105         * configure: Re-generate.
1106
1107         * Makefile.in (gencode): Kill, kill, kill.
1108         * gencode.c: Ditto.
1109
1110 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1111
1112         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1113         bit mips16 igen simulator.
1114         * configure: Re-generate.
1115
1116         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1117         as part of vr4100 ISA.
1118         * vr.igen: Mark all instructions as 64 bit only.
1119
1120 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1121
1122         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1123         Pacify GCC.
1124
1125 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1126
1127         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1128         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1129         * configure: Re-generate.
1130
1131         * m16.igen (BREAK): Define breakpoint instruction.
1132         (JALX32): Mark instruction as mips16 and not r3900.
1133         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1134
1135         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1136
1137 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1138
1139         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1140         insn as a debug breakpoint.
1141
1142         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1143         pending.slot_size.
1144         (PENDING_SCHED): Clean up trace statement.
1145         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1146         (PENDING_FILL): Delay write by only one cycle.
1147         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1148
1149         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1150         of pending writes.
1151         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1152         32 & 64.
1153         (pending_tick): Move incrementing of index to FOR statement.
1154         (pending_tick): Only update PENDING_OUT after a write has occured.
1155
1156         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1157         build simulator.
1158         * configure: Re-generate.
1159
1160         * interp.c (sim_engine_run OLD): Delete explicit call to
1161         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1162
1163 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1164
1165         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1166         interrupt level number to match changed SignalExceptionInterrupt
1167         macro.
1168
1169 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1170
1171         * interp.c: #include "itable.h" if WITH_IGEN.
1172         (get_insn_name): New function.
1173         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1174         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1175
1176 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1177
1178         * configure: Rebuilt to inhale new common/aclocal.m4.
1179
1180 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1181
1182         * dv-tx3904sio.c: Include sim-assert.h.
1183
1184 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1185
1186         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1187         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1188         Reorganize target-specific sim-hardware checks.
1189         * configure: rebuilt.
1190         * interp.c (sim_open): For tx39 target boards, set
1191         OPERATING_ENVIRONMENT, add tx3904sio devices.
1192         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1193         ROM executables.  Install dv-sockser into sim-modules list.
1194
1195         * dv-tx3904irc.c: Compiler warning clean-up.
1196         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1197         frequent hw-trace messages.
1198
1199 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1200
1201         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1202
1203 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1204
1205         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1206
1207         * vr.igen: New file.
1208         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1209         * mips.igen: Define vr4100 model. Include vr.igen.
1210 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1211
1212         * mips.igen (check_mf_hilo): Correct check.
1213
1214 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1215
1216         * sim-main.h (interrupt_event): Add prototype.
1217
1218         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1219         register_ptr, register_value.
1220         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1221
1222         * sim-main.h (tracefh): Make extern.
1223
1224 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1225
1226         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1227         Reduce unnecessarily high timer event frequency.
1228         * dv-tx3904cpu.c: Ditto for interrupt event.
1229
1230 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1231
1232         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1233         to allay warnings.
1234         (interrupt_event): Made non-static.
1235
1236         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1237         interchange of configuration values for external vs. internal
1238         clock dividers.
1239
1240 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1241
1242         * mips.igen (BREAK): Moved code to here for
1243         simulator-reserved break instructions.
1244         * gencode.c (build_instruction): Ditto.
1245         * interp.c (signal_exception): Code moved from here.  Non-
1246         reserved instructions now use exception vector, rather
1247         than halting sim.
1248         * sim-main.h: Moved magic constants to here.
1249
1250 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1251
1252         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1253         register upon non-zero interrupt event level, clear upon zero
1254         event value.
1255         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1256         by passing zero event value.
1257         (*_io_{read,write}_buffer): Endianness fixes.
1258         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1259         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1260
1261         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1262         serial I/O and timer module at base address 0xFFFF0000.
1263
1264 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1265
1266         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1267         and BigEndianCPU.
1268
1269 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1270
1271         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1272         parts.
1273         * configure: Update.
1274
1275 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1276
1277         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1278         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1279         * configure.in: Include tx3904tmr in hw_device list.
1280         * configure: Rebuilt.
1281         * interp.c (sim_open): Instantiate three timer instances.
1282         Fix address typo of tx3904irc instance.
1283
1284 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1285
1286         * interp.c (signal_exception): SystemCall exception now uses
1287         the exception vector.
1288
1289 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1290
1291         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1292         to allay warnings.
1293
1294 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1297
1298 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1301
1302         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1303         sim-main.h. Declare a struct hw_descriptor instead of struct
1304         hw_device_descriptor.
1305
1306 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1307
1308         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1309         right bits and then re-align left hand bytes to correct byte
1310         lanes.  Fix incorrect computation in do_store_left when loading
1311         bytes from second word.
1312
1313 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1314
1315         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1316         * interp.c (sim_open): Only create a device tree when HW is
1317         enabled.
1318
1319         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1320         * interp.c (signal_exception): Ditto.
1321
1322 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1323
1324         * gencode.c: Mark BEGEZALL as LIKELY.
1325
1326 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1327
1328         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1329         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1330
1331 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1332
1333         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1334         modules.  Recognize TX39 target with "mips*tx39" pattern.
1335         * configure: Rebuilt.
1336         * sim-main.h (*): Added many macros defining bits in
1337         TX39 control registers.
1338         (SignalInterrupt): Send actual PC instead of NULL.
1339         (SignalNMIReset): New exception type.
1340         * interp.c (board): New variable for future use to identify
1341         a particular board being simulated.
1342         (mips_option_handler,mips_options): Added "--board" option.
1343         (interrupt_event): Send actual PC.
1344         (sim_open): Make memory layout conditional on board setting.
1345         (signal_exception): Initial implementation of hardware interrupt
1346         handling.  Accept another break instruction variant for simulator
1347         exit.
1348         (decode_coproc): Implement RFE instruction for TX39.
1349         (mips.igen): Decode RFE instruction as such.
1350         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1351         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1352         bbegin to implement memory map.
1353         * dv-tx3904cpu.c: New file.
1354         * dv-tx3904irc.c: New file.
1355
1356 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1357
1358         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1359
1360 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1361
1362         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1363         with calls to check_div_hilo.
1364
1365 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1366
1367         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1368         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1369         Add special r3900 version of do_mult_hilo.
1370         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1371         with calls to check_mult_hilo.
1372         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1373         with calls to check_div_hilo.
1374
1375 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1378         Document a replacement.
1379
1380 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1381
1382         * interp.c (sim_monitor): Make mon_printf work.
1383
1384 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1385
1386         * sim-main.h (INSN_NAME): New arg `cpu'.
1387
1388 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1389
1390         * configure: Regenerated to track ../common/aclocal.m4 changes.
1391
1392 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1393
1394         * configure: Regenerated to track ../common/aclocal.m4 changes.
1395         * config.in: Ditto.
1396
1397 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1398
1399         * acconfig.h: New file.
1400         * configure.in: Reverted change of Apr 24; use sinclude again.
1401
1402 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1403
1404         * configure: Regenerated to track ../common/aclocal.m4 changes.
1405         * config.in: Ditto.
1406
1407 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1408
1409         * configure.in: Don't call sinclude.
1410
1411 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1412
1413         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1414
1415 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1416
1417         * mips.igen (ERET): Implement.
1418
1419         * interp.c (decode_coproc): Return sign-extended EPC.
1420
1421         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1422
1423         * interp.c (signal_exception): Do not ignore Trap.
1424         (signal_exception): On TRAP, restart at exception address.
1425         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1426         (signal_exception): Update.
1427         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1428         so that TRAP instructions are caught.
1429
1430 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1431
1432         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1433         contains HI/LO access history.
1434         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1435         (HIACCESS, LOACCESS): Delete, replace with
1436         (HIHISTORY, LOHISTORY): New macros.
1437         (CHECKHILO): Delete all, moved to mips.igen
1438
1439         * gencode.c (build_instruction): Do not generate checks for
1440         correct HI/LO register usage.
1441
1442         * interp.c (old_engine_run): Delete checks for correct HI/LO
1443         register usage.
1444
1445         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1446         check_mf_cycles): New functions.
1447         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1448         do_divu, domultx, do_mult, do_multu): Use.
1449
1450         * tx.igen ("madd", "maddu"): Use.
1451
1452 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1453
1454         * mips.igen (DSRAV): Use function do_dsrav.
1455         (SRAV): Use new function do_srav.
1456
1457         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1458         (B): Sign extend 11 bit immediate.
1459         (EXT-B*): Shift 16 bit immediate left by 1.
1460         (ADDIU*): Don't sign extend immediate value.
1461
1462 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1463
1464         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1465
1466         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1467         functions.
1468
1469         * mips.igen (delayslot32, nullify_next_insn): New functions.
1470         (m16.igen): Always include.
1471         (do_*): Add more tracing.
1472
1473         * m16.igen (delayslot16): Add NIA argument, could be called by a
1474         32 bit MIPS16 instruction.
1475
1476         * interp.c (ifetch16): Move function from here.
1477         * sim-main.c (ifetch16): To here.
1478
1479         * sim-main.c (ifetch16, ifetch32): Update to match current
1480         implementations of LH, LW.
1481         (signal_exception): Don't print out incorrect hex value of illegal
1482         instruction.
1483
1484 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1485
1486         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1487         instruction.
1488
1489         * m16.igen: Implement MIPS16 instructions.
1490
1491         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1492         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1493         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1494         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1495         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1496         bodies of corresponding code from 32 bit insn to these.  Also used
1497         by MIPS16 versions of functions.
1498
1499         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1500         (IMEM16): Drop NR argument from macro.
1501
1502 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1503
1504         * Makefile.in (SIM_OBJS): Add sim-main.o.
1505
1506         * sim-main.h (address_translation, load_memory, store_memory,
1507         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1508         as INLINE_SIM_MAIN.
1509         (pr_addr, pr_uword64): Declare.
1510         (sim-main.c): Include when H_REVEALS_MODULE_P.
1511
1512         * interp.c (address_translation, load_memory, store_memory,
1513         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1514         from here.
1515         * sim-main.c: To here. Fix compilation problems.
1516
1517         * configure.in: Enable inlining.
1518         * configure: Re-config.
1519
1520 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1521
1522         * configure: Regenerated to track ../common/aclocal.m4 changes.
1523
1524 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1525
1526         * mips.igen: Include tx.igen.
1527         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1528         * tx.igen: New file, contains MADD and MADDU.
1529
1530         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1531         the hardwired constant `7'.
1532         (store_memory): Ditto.
1533         (LOADDRMASK): Move definition to sim-main.h.
1534
1535         mips.igen (MTC0): Enable for r3900.
1536         (ADDU): Add trace.
1537
1538         mips.igen (do_load_byte): Delete.
1539         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1540         do_store_right): New functions.
1541         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1542
1543         configure.in: Let the tx39 use igen again.
1544         configure: Update.
1545
1546 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1547
1548         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1549         not an address sized quantity.  Return zero for cache sizes.
1550
1551 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * mips.igen (r3900): r3900 does not support 64 bit integer
1554         operations.
1555
1556 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1557
1558         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1559         than igen one.
1560         * configure : Rebuild.
1561
1562 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1563
1564         * configure: Regenerated to track ../common/aclocal.m4 changes.
1565
1566 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1567
1568         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1569
1570 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1571
1572         * configure: Regenerated to track ../common/aclocal.m4 changes.
1573         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1574
1575 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1576
1577         * configure: Regenerated to track ../common/aclocal.m4 changes.
1578
1579 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1580
1581         * interp.c (Max, Min): Comment out functions. Not yet used.
1582
1583 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1584
1585         * configure: Regenerated to track ../common/aclocal.m4 changes.
1586
1587 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1588
1589         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1590         configurable settings for stand-alone simulator.
1591
1592         * configure.in: Added X11 search, just in case.
1593
1594         * configure: Regenerated.
1595
1596 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1597
1598         * interp.c (sim_write, sim_read, load_memory, store_memory):
1599         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1600
1601 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1602
1603         * sim-main.h (GETFCC): Return an unsigned value.
1604
1605 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1606
1607         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1608         (DADD): Result destination is RD not RT.
1609
1610 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1611
1612         * sim-main.h (HIACCESS, LOACCESS): Always define.
1613
1614         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1615
1616         * interp.c (sim_info): Delete.
1617
1618 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1619
1620         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1621         (mips_option_handler): New argument `cpu'.
1622         (sim_open): Update call to sim_add_option_table.
1623
1624 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1625
1626         * mips.igen (CxC1): Add tracing.
1627
1628 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1629
1630         * sim-main.h (Max, Min): Declare.
1631
1632         * interp.c (Max, Min): New functions.
1633
1634         * mips.igen (BC1): Add tracing.
1635
1636 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1637
1638         * interp.c Added memory map for stack in vr4100
1639
1640 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1641
1642         * interp.c (load_memory): Add missing "break"'s.
1643
1644 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1645
1646         * interp.c (sim_store_register, sim_fetch_register): Pass in
1647         length parameter.  Return -1.
1648
1649 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1650
1651         * interp.c: Added hardware init hook, fixed warnings.
1652
1653 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1656
1657 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1658
1659         * interp.c (ifetch16): New function.
1660
1661         * sim-main.h (IMEM32): Rename IMEM.
1662         (IMEM16_IMMED): Define.
1663         (IMEM16): Define.
1664         (DELAY_SLOT): Update.
1665
1666         * m16run.c (sim_engine_run): New file.
1667
1668         * m16.igen: All instructions except LB.
1669         (LB): Call do_load_byte.
1670         * mips.igen (do_load_byte): New function.
1671         (LB): Call do_load_byte.
1672
1673         * mips.igen: Move spec for insn bit size and high bit from here.
1674         * Makefile.in (tmp-igen, tmp-m16): To here.
1675
1676         * m16.dc: New file, decode mips16 instructions.
1677
1678         * Makefile.in (SIM_NO_ALL): Define.
1679         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1680
1681 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1682
1683         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1684         point unit to 32 bit registers.
1685         * configure: Re-generate.
1686
1687 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1688
1689         * configure.in (sim_use_gen): Make IGEN the default simulator
1690         generator for generic 32 and 64 bit mips targets.
1691         * configure: Re-generate.
1692
1693 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1694
1695         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1696         bitsize.
1697
1698         * interp.c (sim_fetch_register, sim_store_register): Read/write
1699         FGR from correct location.
1700         (sim_open): Set size of FGR's according to
1701         WITH_TARGET_FLOATING_POINT_BITSIZE.
1702
1703         * sim-main.h (FGR): Store floating point registers in a separate
1704         array.
1705
1706 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1707
1708         * configure: Regenerated to track ../common/aclocal.m4 changes.
1709
1710 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1711
1712         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1713
1714         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1715
1716         * interp.c (pending_tick): New function.  Deliver pending writes.
1717
1718         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1719         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1720         it can handle mixed sized quantites and single bits.
1721
1722 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1723
1724         * interp.c (oengine.h): Do not include when building with IGEN.
1725         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1726         (sim_info): Ditto for PROCESSOR_64BIT.
1727         (sim_monitor): Replace ut_reg with unsigned_word.
1728         (*): Ditto for t_reg.
1729         (LOADDRMASK): Define.
1730         (sim_open): Remove defunct check that host FP is IEEE compliant,
1731         using software to emulate floating point.
1732         (value_fpr, ...): Always compile, was conditional on HASFPU.
1733
1734 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1737         size.
1738
1739         * interp.c (SD, CPU): Define.
1740         (mips_option_handler): Set flags in each CPU.
1741         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1742         (sim_close): Do not clear STATE, deleted anyway.
1743         (sim_write, sim_read): Assume CPU zero's vm should be used for
1744         data transfers.
1745         (sim_create_inferior): Set the PC for all processors.
1746         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1747         argument.
1748         (mips16_entry): Pass correct nr of args to store_word, load_word.
1749         (ColdReset): Cold reset all cpu's.
1750         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1751         (sim_monitor, load_memory, store_memory, signal_exception): Use
1752         `CPU' instead of STATE_CPU.
1753
1754
1755         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1756         SD or CPU_.
1757
1758         * sim-main.h (signal_exception): Add sim_cpu arg.
1759         (SignalException*): Pass both SD and CPU to signal_exception.
1760         * interp.c (signal_exception): Update.
1761
1762         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1763         Ditto
1764         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1765         address_translation): Ditto
1766         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1767
1768 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1769
1770         * configure: Regenerated to track ../common/aclocal.m4 changes.
1771
1772 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1773
1774         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1775
1776         * mips.igen (model): Map processor names onto BFD name.
1777
1778         * sim-main.h (CPU_CIA): Delete.
1779         (SET_CIA, GET_CIA): Define
1780
1781 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1782
1783         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1784         regiser.
1785
1786         * configure.in (default_endian): Configure a big-endian simulator
1787         by default.
1788         * configure: Re-generate.
1789
1790 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1791
1792         * configure: Regenerated to track ../common/aclocal.m4 changes.
1793
1794 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1795
1796         * interp.c (sim_monitor): Handle Densan monitor outbyte
1797         and inbyte functions.
1798
1799 1997-12-29  Felix Lee  <flee@cygnus.com>
1800
1801         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1802
1803 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1804
1805         * Makefile.in (tmp-igen): Arrange for $zero to always be
1806         reset to zero after every instruction.
1807
1808 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1809
1810         * configure: Regenerated to track ../common/aclocal.m4 changes.
1811         * config.in: Ditto.
1812
1813 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1814
1815         * mips.igen (MSUB): Fix to work like MADD.
1816         * gencode.c (MSUB): Similarly.
1817
1818 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1819
1820         * configure: Regenerated to track ../common/aclocal.m4 changes.
1821
1822 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1823
1824         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1825
1826 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1827
1828         * sim-main.h (sim-fpu.h): Include.
1829
1830         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1831         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1832         using host independant sim_fpu module.
1833
1834 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * interp.c (signal_exception): Report internal errors with SIGABRT
1837         not SIGQUIT.
1838
1839         * sim-main.h (C0_CONFIG): New register.
1840         (signal.h): No longer include.
1841
1842         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1843
1844 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1845
1846         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1847
1848 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * mips.igen: Tag vr5000 instructions.
1851         (ANDI): Was missing mipsIV model, fix assembler syntax.
1852         (do_c_cond_fmt): New function.
1853         (C.cond.fmt): Handle mips I-III which do not support CC field
1854         separatly.
1855         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1856         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1857         in IV3.2 spec.
1858         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1859         vr5000 which saves LO in a GPR separatly.
1860
1861         * configure.in (enable-sim-igen): For vr5000, select vr5000
1862         specific instructions.
1863         * configure: Re-generate.
1864
1865 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1866
1867         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1868
1869         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1870         fmt_uninterpreted_64 bit cases to switch.  Convert to
1871         fmt_formatted,
1872
1873         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1874
1875         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1876         as specified in IV3.2 spec.
1877         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1878
1879 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1882         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1883         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1884         PENDING_FILL versions of instructions.  Simplify.
1885         (X): New function.
1886         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1887         instructions.
1888         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1889         a signed value.
1890         (MTHI, MFHI): Disable code checking HI-LO.
1891
1892         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1893         global.
1894         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1895
1896 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1897
1898         * gencode.c (build_mips16_operands): Replace IPC with cia.
1899
1900         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1901         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1902         IPC to `cia'.
1903         (UndefinedResult): Replace function with macro/function
1904         combination.
1905         (sim_engine_run): Don't save PC in IPC.
1906
1907         * sim-main.h (IPC): Delete.
1908
1909
1910         * interp.c (signal_exception, store_word, load_word,
1911         address_translation, load_memory, store_memory, cache_op,
1912         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1913         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1914         current instruction address - cia - argument.
1915         (sim_read, sim_write): Call address_translation directly.
1916         (sim_engine_run): Rename variable vaddr to cia.
1917         (signal_exception): Pass cia to sim_monitor
1918
1919         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1920         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1921         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1922
1923         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1924         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1925         SIM_ASSERT.
1926
1927         * interp.c (signal_exception): Pass restart address to
1928         sim_engine_restart.
1929
1930         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1931         idecode.o): Add dependency.
1932
1933         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1934         Delete definitions
1935         (DELAY_SLOT): Update NIA not PC with branch address.
1936         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1937
1938         * mips.igen: Use CIA not PC in branch calculations.
1939         (illegal): Call SignalException.
1940         (BEQ, ADDIU): Fix assembler.
1941
1942 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1943
1944         * m16.igen (JALX): Was missing.
1945
1946         * configure.in (enable-sim-igen): New configuration option.
1947         * configure: Re-generate.
1948
1949         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1950
1951         * interp.c (load_memory, store_memory): Delete parameter RAW.
1952         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1953         bypassing {load,store}_memory.
1954
1955         * sim-main.h (ByteSwapMem): Delete definition.
1956
1957         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1958
1959         * interp.c (sim_do_command, sim_commands): Delete mips specific
1960         commands.  Handled by module sim-options.
1961
1962         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1963         (WITH_MODULO_MEMORY): Define.
1964
1965         * interp.c (sim_info): Delete code printing memory size.
1966
1967         * interp.c (mips_size): Nee sim_size, delete function.
1968         (power2): Delete.
1969         (monitor, monitor_base, monitor_size): Delete global variables.
1970         (sim_open, sim_close): Delete code creating monitor and other
1971         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1972         manage memory regions.
1973         (load_memory, store_memory): Use sim-core for memory model.
1974
1975         * interp.c (address_translation): Delete all memory map code
1976         except line forcing 32 bit addresses.
1977
1978 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1979
1980         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1981         trace options.
1982
1983         * interp.c (logfh, logfile): Delete globals.
1984         (sim_open, sim_close): Delete code opening & closing log file.
1985         (mips_option_handler): Delete -l and -n options.
1986         (OPTION mips_options): Ditto.
1987
1988         * interp.c (OPTION mips_options): Rename option trace to dinero.
1989         (mips_option_handler): Update.
1990
1991 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1992
1993         * interp.c (fetch_str): New function.
1994         (sim_monitor): Rewrite using sim_read & sim_write.
1995         (sim_open): Check magic number.
1996         (sim_open): Write monitor vectors into memory using sim_write.
1997         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1998         (sim_read, sim_write): Simplify - transfer data one byte at a
1999         time.
2000         (load_memory, store_memory): Clarify meaning of parameter RAW.
2001
2002         * sim-main.h (isHOST): Defete definition.
2003         (isTARGET): Mark as depreciated.
2004         (address_translation): Delete parameter HOST.
2005
2006         * interp.c (address_translation): Delete parameter HOST.
2007
2008 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * mips.igen:
2011
2012         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2013         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2014
2015 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2016
2017         * mips.igen: Add model filter field to records.
2018
2019 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2020
2021         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2022
2023         interp.c (sim_engine_run): Do not compile function sim_engine_run
2024         when WITH_IGEN == 1.
2025
2026         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2027         target architecture.
2028
2029         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2030         igen. Replace with configuration variables sim_igen_flags /
2031         sim_m16_flags.
2032
2033         * m16.igen: New file.  Copy mips16 insns here.
2034         * mips.igen: From here.
2035
2036 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2037
2038         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2039         to top.
2040         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2041
2042 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2043
2044         * gencode.c (build_instruction): Follow sim_write's lead in using
2045         BigEndianMem instead of !ByteSwapMem.
2046
2047 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2048
2049         * configure.in (sim_gen): Dependent on target, select type of
2050         generator.  Always select old style generator.
2051
2052         configure: Re-generate.
2053
2054         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2055         targets.
2056         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2057         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2058         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2059         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2060         SIM_@sim_gen@_*, set by autoconf.
2061
2062 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2063
2064         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2065
2066         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2067         CURRENT_FLOATING_POINT instead.
2068
2069         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2070         (address_translation): Raise exception InstructionFetch when
2071         translation fails and isINSTRUCTION.
2072
2073         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2074         sim_engine_run): Change type of of vaddr and paddr to
2075         address_word.
2076         (address_translation, prefetch, load_memory, store_memory,
2077         cache_op): Change type of vAddr and pAddr to address_word.
2078
2079         * gencode.c (build_instruction): Change type of vaddr and paddr to
2080         address_word.
2081
2082 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2083
2084         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2085         macro to obtain result of ALU op.
2086
2087 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2088
2089         * interp.c (sim_info): Call profile_print.
2090
2091 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2092
2093         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2094
2095         * sim-main.h (WITH_PROFILE): Do not define, defined in
2096         common/sim-config.h.  Use sim-profile module.
2097         (simPROFILE): Delete defintion.
2098
2099         * interp.c (PROFILE): Delete definition.
2100         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2101         (sim_close): Delete code writing profile histogram.
2102         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2103         Delete.
2104         (sim_engine_run): Delete code profiling the PC.
2105
2106 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2107
2108         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2109
2110         * interp.c (sim_monitor): Make register pointers of type
2111         unsigned_word*.
2112
2113         * sim-main.h: Make registers of type unsigned_word not
2114         signed_word.
2115
2116 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2117
2118         * interp.c (sync_operation): Rename from SyncOperation, make
2119         global, add SD argument.
2120         (prefetch): Rename from Prefetch, make global, add SD argument.
2121         (decode_coproc): Make global.
2122
2123         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2124
2125         * gencode.c (build_instruction): Generate DecodeCoproc not
2126         decode_coproc calls.
2127
2128         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2129         (SizeFGR): Move to sim-main.h
2130         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2131         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2132         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2133         sim-main.h.
2134         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2135         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2136         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2137         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2138         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2139         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2140
2141         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2142         exception.
2143         (sim-alu.h): Include.
2144         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2145         (sim_cia): Typedef to instruction_address.
2146
2147 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2148
2149         * Makefile.in (interp.o): Rename generated file engine.c to
2150         oengine.c.
2151
2152         * interp.c: Update.
2153
2154 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2155
2156         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2157
2158 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2159
2160         * gencode.c (build_instruction): For "FPSQRT", output correct
2161         number of arguments to Recip.
2162
2163 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2164
2165         * Makefile.in (interp.o): Depends on sim-main.h
2166
2167         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2168
2169         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2170         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2171         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2172         STATE, DSSTATE): Define
2173         (GPR, FGRIDX, ..): Define.
2174
2175         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2176         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2177         (GPR, FGRIDX, ...): Delete macros.
2178
2179         * interp.c: Update names to match defines from sim-main.h
2180
2181 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2182
2183         * interp.c (sim_monitor): Add SD argument.
2184         (sim_warning): Delete.  Replace calls with calls to
2185         sim_io_eprintf.
2186         (sim_error): Delete. Replace calls with sim_io_error.
2187         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2188         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2189         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2190         argument.
2191         (mips_size): Rename from sim_size. Add SD argument.
2192
2193         * interp.c (simulator): Delete global variable.
2194         (callback): Delete global variable.
2195         (mips_option_handler, sim_open, sim_write, sim_read,
2196         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2197         sim_size,sim_monitor): Use sim_io_* not callback->*.
2198         (sim_open): ZALLOC simulator struct.
2199         (PROFILE): Do not define.
2200
2201 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2202
2203         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2204         support.h with corresponding code.
2205
2206         * sim-main.h (word64, uword64), support.h: Move definition to
2207         sim-main.h.
2208         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2209
2210         * support.h: Delete
2211         * Makefile.in: Update dependencies
2212         * interp.c: Do not include.
2213
2214 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2215
2216         * interp.c (address_translation, load_memory, store_memory,
2217         cache_op): Rename to from AddressTranslation et.al., make global,
2218         add SD argument
2219
2220         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2221         CacheOp): Define.
2222
2223         * interp.c (SignalException): Rename to signal_exception, make
2224         global.
2225
2226         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2227
2228         * sim-main.h (SignalException, SignalExceptionInterrupt,
2229         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2230         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2231         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2232         Define.
2233
2234         * interp.c, support.h: Use.
2235
2236 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2237
2238         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2239         to value_fpr / store_fpr. Add SD argument.
2240         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2241         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2242
2243         * sim-main.h (ValueFPR, StoreFPR): Define.
2244
2245 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2246
2247         * interp.c (sim_engine_run): Check consistency between configure
2248         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2249         and HASFPU.
2250
2251         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2252         (mips_fpu): Configure WITH_FLOATING_POINT.
2253         (mips_endian): Configure WITH_TARGET_ENDIAN.
2254         * configure: Update.
2255
2256 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2257
2258         * configure: Regenerated to track ../common/aclocal.m4 changes.
2259
2260 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2261
2262         * configure: Regenerated.
2263
2264 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2265
2266         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2267
2268 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2269
2270         * gencode.c (print_igen_insn_models): Assume certain architectures
2271         include all mips* instructions.
2272         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2273         instruction.
2274
2275         * Makefile.in (tmp.igen): Add target. Generate igen input from
2276         gencode file.
2277
2278         * gencode.c (FEATURE_IGEN): Define.
2279         (main): Add --igen option.  Generate output in igen format.
2280         (process_instructions): Format output according to igen option.
2281         (print_igen_insn_format): New function.
2282         (print_igen_insn_models): New function.
2283         (process_instructions): Only issue warnings and ignore
2284         instructions when no FEATURE_IGEN.
2285
2286 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2287
2288         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2289         MIPS targets.
2290
2291 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2292
2293         * configure: Regenerated to track ../common/aclocal.m4 changes.
2294
2295 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2296
2297         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2298         SIM_RESERVED_BITS): Delete, moved to common.
2299         (SIM_EXTRA_CFLAGS): Update.
2300
2301 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2302
2303         * configure.in: Configure non-strict memory alignment.
2304         * configure: Regenerated to track ../common/aclocal.m4 changes.
2305
2306 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2307
2308         * configure: Regenerated to track ../common/aclocal.m4 changes.
2309
2310 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2311
2312         * gencode.c (SDBBP,DERET): Added (3900) insns.
2313         (RFE): Turn on for 3900.
2314         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2315         (dsstate): Made global.
2316         (SUBTARGET_R3900): Added.
2317         (CANCELDELAYSLOT): New.
2318         (SignalException): Ignore SystemCall rather than ignore and
2319         terminate.  Add DebugBreakPoint handling.
2320         (decode_coproc): New insns RFE, DERET; and new registers Debug
2321         and DEPC protected by SUBTARGET_R3900.
2322         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2323         bits explicitly.
2324         * Makefile.in,configure.in: Add mips subtarget option.
2325         * configure: Update.
2326
2327 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2328
2329         * gencode.c: Add r3900 (tx39).
2330
2331
2332 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2333
2334         * gencode.c (build_instruction): Don't need to subtract 4 for
2335         JALR, just 2.
2336
2337 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2338
2339         * interp.c: Correct some HASFPU problems.
2340
2341 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2342
2343         * configure: Regenerated to track ../common/aclocal.m4 changes.
2344
2345 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2346
2347         * interp.c (mips_options): Fix samples option short form, should
2348         be `x'.
2349
2350 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2351
2352         * interp.c (sim_info): Enable info code.  Was just returning.
2353
2354 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2355
2356         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2357         MFC0.
2358
2359 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2360
2361         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2362         constants.
2363         (build_instruction): Ditto for LL.
2364
2365 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2366
2367         * configure: Regenerated to track ../common/aclocal.m4 changes.
2368
2369 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * configure: Regenerated to track ../common/aclocal.m4 changes.
2372         * config.in: Ditto.
2373
2374 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * interp.c (sim_open): Add call to sim_analyze_program, update
2377         call to sim_config.
2378
2379 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2380
2381         * interp.c (sim_kill): Delete.
2382         (sim_create_inferior): Add ABFD argument. Set PC from same.
2383         (sim_load): Move code initializing trap handlers from here.
2384         (sim_open): To here.
2385         (sim_load): Delete, use sim-hload.c.
2386
2387         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2388
2389 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2390
2391         * configure: Regenerated to track ../common/aclocal.m4 changes.
2392         * config.in: Ditto.
2393
2394 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2395
2396         * interp.c (sim_open): Add ABFD argument.
2397         (sim_load): Move call to sim_config from here.
2398         (sim_open): To here.  Check return status.
2399
2400 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2401
2402         * gencode.c (build_instruction): Two arg MADD should
2403         not assign result to $0.
2404
2405 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2406
2407         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2408         * sim/mips/configure.in: Regenerate.
2409
2410 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2411
2412         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2413         signed8, unsigned8 et.al. types.
2414
2415         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2416         hosts when selecting subreg.
2417
2418 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2419
2420         * interp.c (sim_engine_run): Reset the ZERO register to zero
2421         regardless of FEATURE_WARN_ZERO.
2422         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2423
2424 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2425
2426         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2427         (SignalException): For BreakPoints ignore any mode bits and just
2428         save the PC.
2429         (SignalException): Always set the CAUSE register.
2430
2431 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2432
2433         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2434         exception has been taken.
2435
2436         * interp.c: Implement the ERET and mt/f sr instructions.
2437
2438 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2439
2440         * interp.c (SignalException): Don't bother restarting an
2441         interrupt.
2442
2443 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2444
2445         * interp.c (SignalException): Really take an interrupt.
2446         (interrupt_event): Only deliver interrupts when enabled.
2447
2448 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2449
2450         * interp.c (sim_info): Only print info when verbose.
2451         (sim_info) Use sim_io_printf for output.
2452
2453 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2454
2455         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2456         mips architectures.
2457
2458 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2459
2460         * interp.c (sim_do_command): Check for common commands if a
2461         simulator specific command fails.
2462
2463 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2464
2465         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2466         and simBE when DEBUG is defined.
2467
2468 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2469
2470         * interp.c (interrupt_event): New function.  Pass exception event
2471         onto exception handler.
2472
2473         * configure.in: Check for stdlib.h.
2474         * configure: Regenerate.
2475
2476         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2477         variable declaration.
2478         (build_instruction): Initialize memval1.
2479         (build_instruction): Add UNUSED attribute to byte, bigend,
2480         reverse.
2481         (build_operands): Ditto.
2482
2483         * interp.c: Fix GCC warnings.
2484         (sim_get_quit_code): Delete.
2485
2486         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2487         * Makefile.in: Ditto.
2488         * configure: Re-generate.
2489
2490         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2491
2492 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2493
2494         * interp.c (mips_option_handler): New function parse argumes using
2495         sim-options.
2496         (myname): Replace with STATE_MY_NAME.
2497         (sim_open): Delete check for host endianness - performed by
2498         sim_config.
2499         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2500         (sim_open): Move much of the initialization from here.
2501         (sim_load): To here.  After the image has been loaded and
2502         endianness set.
2503         (sim_open): Move ColdReset from here.
2504         (sim_create_inferior): To here.
2505         (sim_open): Make FP check less dependant on host endianness.
2506
2507         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2508         run.
2509         * interp.c (sim_set_callbacks): Delete.
2510
2511         * interp.c (membank, membank_base, membank_size): Replace with
2512         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2513         (sim_open): Remove call to callback->init. gdb/run do this.
2514
2515         * interp.c: Update
2516
2517         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2518
2519         * interp.c (big_endian_p): Delete, replaced by
2520         current_target_byte_order.
2521
2522 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2523
2524         * interp.c (host_read_long, host_read_word, host_swap_word,
2525         host_swap_long): Delete. Using common sim-endian.
2526         (sim_fetch_register, sim_store_register): Use H2T.
2527         (pipeline_ticks): Delete.  Handled by sim-events.
2528         (sim_info): Update.
2529         (sim_engine_run): Update.
2530
2531 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2532
2533         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2534         reason from here.
2535         (SignalException): To here. Signal using sim_engine_halt.
2536         (sim_stop_reason): Delete, moved to common.
2537
2538 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2539
2540         * interp.c (sim_open): Add callback argument.
2541         (sim_set_callbacks): Delete SIM_DESC argument.
2542         (sim_size): Ditto.
2543
2544 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2545
2546         * Makefile.in (SIM_OBJS): Add common modules.
2547
2548         * interp.c (sim_set_callbacks): Also set SD callback.
2549         (set_endianness, xfer_*, swap_*): Delete.
2550         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2551         Change to functions using sim-endian macros.
2552         (control_c, sim_stop): Delete, use common version.
2553         (simulate): Convert into.
2554         (sim_engine_run): This function.
2555         (sim_resume): Delete.
2556
2557         * interp.c (simulation): New variable - the simulator object.
2558         (sim_kind): Delete global - merged into simulation.
2559         (sim_load): Cleanup.  Move PC assignment from here.
2560         (sim_create_inferior): To here.
2561
2562         * sim-main.h: New file.
2563         * interp.c (sim-main.h): Include.
2564
2565 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2566
2567         * configure: Regenerated to track ../common/aclocal.m4 changes.
2568
2569 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2570
2571         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2572
2573 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2574
2575         * gencode.c (build_instruction): DIV instructions: check
2576         for division by zero and integer overflow before using
2577         host's division operation.
2578
2579 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2580
2581         * Makefile.in (SIM_OBJS): Add sim-load.o.
2582         * interp.c: #include bfd.h.
2583         (target_byte_order): Delete.
2584         (sim_kind, myname, big_endian_p): New static locals.
2585         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2586         after argument parsing.  Recognize -E arg, set endianness accordingly.
2587         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2588         load file into simulator.  Set PC from bfd.
2589         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2590         (set_endianness): Use big_endian_p instead of target_byte_order.
2591
2592 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2593
2594         * interp.c (sim_size): Delete prototype - conflicts with
2595         definition in remote-sim.h.  Correct definition.
2596
2597 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2598
2599         * configure: Regenerated to track ../common/aclocal.m4 changes.
2600         * config.in: Ditto.
2601
2602 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2603
2604         * interp.c (sim_open): New arg `kind'.
2605
2606         * configure: Regenerated to track ../common/aclocal.m4 changes.
2607
2608 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2609
2610         * configure: Regenerated to track ../common/aclocal.m4 changes.
2611
2612 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2613
2614         * interp.c (sim_open): Set optind to 0 before calling getopt.
2615
2616 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2617
2618         * configure: Regenerated to track ../common/aclocal.m4 changes.
2619
2620 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2621
2622         * interp.c : Replace uses of pr_addr with pr_uword64
2623         where the bit length is always 64 independent of SIM_ADDR.
2624         (pr_uword64) : added.
2625
2626 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2627
2628         * configure: Re-generate.
2629
2630 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2631
2632         * configure: Regenerate to track ../common/aclocal.m4 changes.
2633
2634 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2635
2636         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2637         in argv form.
2638         (other sim_*): New SIM_DESC argument.
2639
2640 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2641
2642         * interp.c: Fix printing of addresses for non-64-bit targets.
2643         (pr_addr): Add function to print address based on size.
2644
2645 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2646
2647         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2648
2649 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2650
2651         * gencode.c (build_mips16_operands): Correct computation of base
2652         address for extended PC relative instruction.
2653
2654 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2655
2656         * interp.c (mips16_entry): Add support for floating point cases.
2657         (SignalException): Pass floating point cases to mips16_entry.
2658         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2659         registers.
2660         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2661         or fmt_word.
2662         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2663         and then set the state to fmt_uninterpreted.
2664         (COP_SW): Temporarily set the state to fmt_word while calling
2665         ValueFPR.
2666
2667 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2668
2669         * gencode.c (build_instruction): The high order may be set in the
2670         comparison flags at any ISA level, not just ISA 4.
2671
2672 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2673
2674         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2675         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2676         * configure.in: sinclude ../common/aclocal.m4.
2677         * configure: Regenerated.
2678
2679 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2680
2681         * configure: Rebuild after change to aclocal.m4.
2682
2683 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2684
2685         * configure configure.in Makefile.in:  Update to new configure
2686         scheme which is more compatible with WinGDB builds.
2687         * configure.in:  Improve comment on how to run autoconf.
2688         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2689         * Makefile.in:  Use autoconf substitution to install common
2690         makefile fragment.
2691
2692 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2693
2694         * gencode.c (build_instruction): Use BigEndianCPU instead of
2695         ByteSwapMem.
2696
2697 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2698
2699         * interp.c (sim_monitor): Make output to stdout visible in
2700         wingdb's I/O log window.
2701
2702 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2703
2704         * support.h: Undo previous change to SIGTRAP
2705         and SIGQUIT values.
2706
2707 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2708
2709         * interp.c (store_word, load_word): New static functions.
2710         (mips16_entry): New static function.
2711         (SignalException): Look for mips16 entry and exit instructions.
2712         (simulate): Use the correct index when setting fpr_state after
2713         doing a pending move.
2714
2715 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2716
2717         * interp.c: Fix byte-swapping code throughout to work on
2718         both little- and big-endian hosts.
2719
2720 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2721
2722         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2723         with gdb/config/i386/xm-windows.h.
2724
2725 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2726
2727         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2728         that messes up arithmetic shifts.
2729
2730 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2731
2732         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2733         SIGTRAP and SIGQUIT for _WIN32.
2734
2735 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2736
2737         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2738         force a 64 bit multiplication.
2739         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2740         destination register is 0, since that is the default mips16 nop
2741         instruction.
2742
2743 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2744
2745         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2746         (build_endian_shift): Don't check proc64.
2747         (build_instruction): Always set memval to uword64.  Cast op2 to
2748         uword64 when shifting it left in memory instructions.  Always use
2749         the same code for stores--don't special case proc64.
2750
2751         * gencode.c (build_mips16_operands): Fix base PC value for PC
2752         relative operands.
2753         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2754         jal instruction.
2755         * interp.c (simJALDELAYSLOT): Define.
2756         (JALDELAYSLOT): Define.
2757         (INDELAYSLOT, INJALDELAYSLOT): Define.
2758         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2759
2760 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2761
2762         * interp.c (sim_open): add flush_cache as a PMON routine
2763         (sim_monitor): handle flush_cache by ignoring it
2764
2765 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2766
2767         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2768         BigEndianMem.
2769         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2770         (BigEndianMem): Rename to ByteSwapMem and change sense.
2771         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2772         BigEndianMem references to !ByteSwapMem.
2773         (set_endianness): New function, with prototype.
2774         (sim_open): Call set_endianness.
2775         (sim_info): Use simBE instead of BigEndianMem.
2776         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2777         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2778         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2779         ifdefs, keeping the prototype declaration.
2780         (swap_word): Rewrite correctly.
2781         (ColdReset): Delete references to CONFIG.  Delete endianness related
2782         code; moved to set_endianness.
2783
2784 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2785
2786         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2787         * interp.c (CHECKHILO): Define away.
2788         (simSIGINT): New macro.
2789         (membank_size): Increase from 1MB to 2MB.
2790         (control_c): New function.
2791         (sim_resume): Rename parameter signal to signal_number.  Add local
2792         variable prev.  Call signal before and after simulate.
2793         (sim_stop_reason): Add simSIGINT support.
2794         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2795         functions always.
2796         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2797         if logfh is NULL.
2798         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2799         a call to sim_warning.
2800
2801 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2802
2803         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2804         16 bit instructions.
2805
2806 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2807
2808         Add support for mips16 (16 bit MIPS implementation):
2809         * gencode.c (inst_type): Add mips16 instruction encoding types.
2810         (GETDATASIZEINSN): Define.
2811         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2812         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2813         mtlo.
2814         (MIPS16_DECODE): New table, for mips16 instructions.
2815         (bitmap_val): New static function.
2816         (struct mips16_op): Define.
2817         (mips16_op_table): New table, for mips16 operands.
2818         (build_mips16_operands): New static function.
2819         (process_instructions): If PC is odd, decode a mips16
2820         instruction.  Break out instruction handling into new
2821         build_instruction function.
2822         (build_instruction): New static function, broken out of
2823         process_instructions.  Check modifiers rather than flags for SHIFT
2824         bit count and m[ft]{hi,lo} direction.
2825         (usage): Pass program name to fprintf.
2826         (main): Remove unused variable this_option_optind.  Change
2827         ``*loptarg++'' to ``loptarg++''.
2828         (my_strtoul): Parenthesize && within ||.
2829         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2830         (simulate): If PC is odd, fetch a 16 bit instruction, and
2831         increment PC by 2 rather than 4.
2832         * configure.in: Add case for mips16*-*-*.
2833         * configure: Rebuild.
2834
2835 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2836
2837         * interp.c: Allow -t to enable tracing in standalone simulator.
2838         Fix garbage output in trace file and error messages.
2839
2840 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2841
2842         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2843         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2844         * configure.in: Simplify using macros in ../common/aclocal.m4.
2845         * configure: Regenerated.
2846         * tconfig.in: New file.
2847
2848 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2849
2850         * interp.c: Fix bugs in 64-bit port.
2851         Use ansi function declarations for msvc compiler.
2852         Initialize and test file pointer in trace code.
2853         Prevent duplicate definition of LAST_EMED_REGNUM.
2854
2855 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2856
2857         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2858
2859 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2860
2861         * interp.c (SignalException): Check for explicit terminating
2862         breakpoint value.
2863         * gencode.c: Pass instruction value through SignalException()
2864         calls for Trap, Breakpoint and Syscall.
2865
2866 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2867
2868         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2869         only used on those hosts that provide it.
2870         * configure.in: Add sqrt() to list of functions to be checked for.
2871         * config.in: Re-generated.
2872         * configure: Re-generated.
2873
2874 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2875
2876         * gencode.c (process_instructions): Call build_endian_shift when
2877         expanding STORE RIGHT, to fix swr.
2878         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2879         clear the high bits.
2880         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2881         Fix float to int conversions to produce signed values.
2882
2883 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2884
2885         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2886         (process_instructions): Correct handling of nor instruction.
2887         Correct shift count for 32 bit shift instructions. Correct sign
2888         extension for arithmetic shifts to not shift the number of bits in
2889         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2890         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2891         Fix madd.
2892         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2893         It's OK to have a mult follow a mult.  What's not OK is to have a
2894         mult follow an mfhi.
2895         (Convert): Comment out incorrect rounding code.
2896
2897 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2898
2899         * interp.c (sim_monitor): Improved monitor printf
2900         simulation. Tidied up simulator warnings, and added "--log" option
2901         for directing warning message output.
2902         * gencode.c: Use sim_warning() rather than WARNING macro.
2903
2904 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2905
2906         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2907         getopt1.o, rather than on gencode.c.  Link objects together.
2908         Don't link against -liberty.
2909         (gencode.o, getopt.o, getopt1.o): New targets.
2910         * gencode.c: Include <ctype.h> and "ansidecl.h".
2911         (AND): Undefine after including "ansidecl.h".
2912         (ULONG_MAX): Define if not defined.
2913         (OP_*): Don't define macros; now defined in opcode/mips.h.
2914         (main): Call my_strtoul rather than strtoul.
2915         (my_strtoul): New static function.
2916
2917 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2918
2919         * gencode.c (process_instructions):  Generate word64 and uword64
2920         instead of `long long' and `unsigned long long' data types.
2921         * interp.c:  #include sysdep.h to get signals, and define default
2922         for SIGBUS.
2923         * (Convert):  Work around for Visual-C++ compiler bug with type
2924         conversion.
2925         * support.h:  Make things compile under Visual-C++ by using
2926         __int64 instead of `long long'.  Change many refs to long long
2927         into word64/uword64 typedefs.
2928
2929 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2930
2931         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2932         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2933         (docdir): Removed.
2934         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2935         (AC_PROG_INSTALL): Added.
2936         (AC_PROG_CC): Moved to before configure.host call.
2937         * configure: Rebuilt.
2938
2939 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2940
2941         * configure.in: Define @SIMCONF@ depending on mips target.
2942         * configure: Rebuild.
2943         * Makefile.in (run): Add @SIMCONF@ to control simulator
2944         construction.
2945         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2946         * interp.c: Remove some debugging, provide more detailed error
2947         messages, update memory accesses to use LOADDRMASK.
2948
2949 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2950
2951         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2952         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2953         stamp-h.
2954         * configure: Rebuild.
2955         * config.in: New file, generated by autoheader.
2956         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2957         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2958         HAVE_ANINT and HAVE_AINT, as appropriate.
2959         * Makefile.in (run): Use @LIBS@ rather than -lm.
2960         (interp.o): Depend upon config.h.
2961         (Makefile): Just rebuild Makefile.
2962         (clean): Remove stamp-h.
2963         (mostlyclean): Make the same as clean, not as distclean.
2964         (config.h, stamp-h): New targets.
2965
2966 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2967
2968         * interp.c (ColdReset): Fix boolean test. Make all simulator
2969         globals static.
2970
2971 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2972
2973         * interp.c (xfer_direct_word, xfer_direct_long,
2974         swap_direct_word, swap_direct_long, xfer_big_word,
2975         xfer_big_long, xfer_little_word, xfer_little_long,
2976         swap_word,swap_long): Added.
2977         * interp.c (ColdReset): Provide function indirection to
2978         host<->simulated_target transfer routines.
2979         * interp.c (sim_store_register, sim_fetch_register): Updated to
2980         make use of indirected transfer routines.
2981
2982 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2983
2984         * gencode.c (process_instructions): Ensure FP ABS instruction
2985         recognised.
2986         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2987         system call support.
2988
2989 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2990
2991         * interp.c (sim_do_command): Complain if callback structure not
2992         initialised.
2993
2994 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2995
2996         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2997         support for Sun hosts.
2998         * Makefile.in (gencode): Ensure the host compiler and libraries
2999         used for cross-hosted build.
3000
3001 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3002
3003         * interp.c, gencode.c: Some more (TODO) tidying.
3004
3005 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3006
3007         * gencode.c, interp.c: Replaced explicit long long references with
3008         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3009         * support.h (SET64LO, SET64HI): Macros added.
3010
3011 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3012
3013         * configure: Regenerate with autoconf 2.7.
3014
3015 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3016
3017         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3018         * support.h: Remove superfluous "1" from #if.
3019         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3020
3021 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3022
3023         * interp.c (StoreFPR): Control UndefinedResult() call on
3024         WARN_RESULT manifest.
3025
3026 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3027
3028         * gencode.c: Tidied instruction decoding, and added FP instruction
3029         support.
3030
3031         * interp.c: Added dineroIII, and BSD profiling support. Also
3032         run-time FP handling.
3033
3034 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3035
3036         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3037         gencode.c, interp.c, support.h: created.