1 2015-03-16 Mike Frysinger <vapier@gentoo.org>
3 * config.in, configure: Regenerate.
4 * tconfig.in: Rename file ...
7 2015-03-15 Mike Frysinger <vapier@gentoo.org>
9 * tconfig.in: Delete includes.
10 [HAVE_DV_SOCKSER]: Delete.
12 2015-03-14 Mike Frysinger <vapier@gentoo.org>
14 * Makefile.in (SIM_RUN_OBJS): Delete.
16 2015-03-14 Mike Frysinger <vapier@gentoo.org>
18 * configure.ac (AC_CHECK_HEADERS): Delete.
19 * aclocal.m4, configure: Regenerate.
21 2014-08-19 Alan Modra <amodra@gmail.com>
23 * configure: Regenerate.
25 2014-08-15 Roland McGrath <mcgrathr@google.com>
27 * configure: Regenerate.
28 * config.in: Regenerate.
30 2014-03-04 Mike Frysinger <vapier@gentoo.org>
32 * configure: Regenerate.
34 2013-09-23 Alan Modra <amodra@gmail.com>
36 * configure: Regenerate.
38 2013-06-03 Mike Frysinger <vapier@gentoo.org>
40 * aclocal.m4, configure: Regenerate.
42 2013-05-10 Freddie Chopin <freddie_chopin@op.pl>
46 2013-03-26 Mike Frysinger <vapier@gentoo.org>
48 * configure: Regenerate.
50 2013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
52 * configure.ac: Address use of dv-sockser.o.
53 * tconfig.in: Conditionalize use of dv_sockser_install.
54 * configure: Regenerated.
55 * config.in: Regenerated.
57 2012-10-04 Chao-ying Fu <fu@mips.com>
58 Steve Ellcey <sellcey@mips.com>
60 * mips/mips3264r2.igen (rdhwr): New.
62 2012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
64 * configure.ac: Always link against dv-sockser.o.
65 * configure: Regenerate.
67 2012-06-15 Joel Brobecker <brobecker@adacore.com>
69 * config.in, configure: Regenerate.
71 2012-05-18 Nick Clifton <nickc@redhat.com>
74 * interp.c: Include config.h before system header files.
76 2012-03-24 Mike Frysinger <vapier@gentoo.org>
78 * aclocal.m4, config.in, configure: Regenerate.
80 2011-12-03 Mike Frysinger <vapier@gentoo.org>
82 * aclocal.m4: New file.
83 * configure: Regenerate.
85 2011-10-19 Mike Frysinger <vapier@gentoo.org>
87 * configure: Regenerate after common/acinclude.m4 update.
89 2011-10-17 Mike Frysinger <vapier@gentoo.org>
91 * configure.ac: Change include to common/acinclude.m4.
93 2011-10-17 Mike Frysinger <vapier@gentoo.org>
95 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
96 call. Replace common.m4 include with SIM_AC_COMMON.
97 * configure: Regenerate.
99 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
101 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
103 (tmp-mach-multi): Exit early when igen fails.
105 2011-07-05 Mike Frysinger <vapier@gentoo.org>
107 * interp.c (sim_do_command): Delete.
109 2011-02-14 Mike Frysinger <vapier@gentoo.org>
111 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
112 (tx3904sio_fifo_reset): Likewise.
113 * interp.c (sim_monitor): Likewise.
115 2010-04-14 Mike Frysinger <vapier@gentoo.org>
117 * interp.c (sim_write): Add const to buffer arg.
119 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
121 * interp.c: Don't include sysdep.h
123 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
125 * configure: Regenerate.
127 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
129 * config.in: Regenerate.
130 * configure: Likewise.
132 * configure: Regenerate.
134 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
136 * configure: Regenerate to track ../common/common.m4 changes.
139 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
140 Daniel Jacobowitz <dan@codesourcery.com>
141 Joseph Myers <joseph@codesourcery.com>
143 * configure: Regenerate.
145 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
147 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
148 that unconditionally allows fmt_ps.
149 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
150 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
151 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
152 filter from 64,f to 32,f.
153 (PREFX): Change filter from 64 to 32.
154 (LDXC1, LUXC1): Provide separate mips32r2 implementations
155 that use do_load_double instead of do_load. Make both LUXC1
156 versions unpredictable if SizeFGR () != 64.
157 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
158 instead of do_store. Remove unused variable. Make both SUXC1
159 versions unpredictable if SizeFGR () != 64.
161 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
163 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
164 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
165 shifts for that case.
167 2007-09-04 Nick Clifton <nickc@redhat.com>
169 * interp.c (options enum): Add OPTION_INFO_MEMORY.
170 (display_mem_info): New static variable.
171 (mips_option_handler): Handle OPTION_INFO_MEMORY.
172 (mips_options): Add info-memory and memory-info.
173 (sim_open): After processing the command line and board
174 specification, check display_mem_info. If it is set then
175 call the real handler for the --memory-info command line
178 2007-08-24 Joel Brobecker <brobecker@adacore.com>
180 * configure.ac: Change license of multi-run.c to GPL version 3.
181 * configure: Regenerate.
183 2007-06-28 Richard Sandiford <richard@codesourcery.com>
185 * configure.ac, configure: Revert last patch.
187 2007-06-26 Richard Sandiford <richard@codesourcery.com>
189 * configure.ac (sim_mipsisa3264_configs): New variable.
190 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
191 every configuration support all four targets, using the triplet to
192 determine the default.
193 * configure: Regenerate.
195 2007-06-25 Richard Sandiford <richard@codesourcery.com>
197 * Makefile.in (m16run.o): New rule.
199 2007-05-15 Thiemo Seufer <ths@mips.com>
201 * mips3264r2.igen (DSHD): Fix compile warning.
203 2007-05-14 Thiemo Seufer <ths@mips.com>
205 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
206 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
207 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
208 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
211 2007-03-01 Thiemo Seufer <ths@mips.com>
213 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
216 2007-02-20 Thiemo Seufer <ths@mips.com>
218 * dsp.igen: Update copyright notice.
219 * dsp2.igen: Fix copyright notice.
221 2007-02-20 Thiemo Seufer <ths@mips.com>
222 Chao-Ying Fu <fu@mips.com>
224 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
225 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
226 Add dsp2 to sim_igen_machine.
227 * configure: Regenerate.
228 * dsp.igen (do_ph_op): Add MUL support when op = 2.
229 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
230 (mulq_rs.ph): Use do_ph_mulq.
231 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
232 * mips.igen: Add dsp2 model and include dsp2.igen.
233 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
234 for *mips32r2, *mips64r2, *dsp.
235 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
236 for *mips32r2, *mips64r2, *dsp2.
237 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
239 2007-02-19 Thiemo Seufer <ths@mips.com>
240 Nigel Stephens <nigel@mips.com>
242 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
243 jumps with hazard barrier.
245 2007-02-19 Thiemo Seufer <ths@mips.com>
246 Nigel Stephens <nigel@mips.com>
248 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
249 after each call to sim_io_write.
251 2007-02-19 Thiemo Seufer <ths@mips.com>
252 Nigel Stephens <nigel@mips.com>
254 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
255 supported by this simulator.
256 (decode_coproc): Recognise additional CP0 Config registers
259 2007-02-19 Thiemo Seufer <ths@mips.com>
260 Nigel Stephens <nigel@mips.com>
261 David Ung <davidu@mips.com>
263 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
264 uninterpreted formats. If fmt is one of the uninterpreted types
265 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
266 fmt_word, and fmt_uninterpreted_64 like fmt_long.
267 (store_fpr): When writing an invalid odd register, set the
268 matching even register to fmt_unknown, not the following register.
269 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
270 the the memory window at offset 0 set by --memory-size command
272 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
274 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
276 (sim_monitor): When returning the memory size to the MIPS
277 application, use the value in STATE_MEM_SIZE, not an arbitrary
279 (cop_lw): Don' mess around with FPR_STATE, just pass
280 fmt_uninterpreted_32 to StoreFPR.
282 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
284 * mips.igen (not_word_value): Single version for mips32, mips64
287 2007-02-19 Thiemo Seufer <ths@mips.com>
288 Nigel Stephens <nigel@mips.com>
290 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
293 2007-02-17 Thiemo Seufer <ths@mips.com>
295 * configure.ac (mips*-sde-elf*): Move in front of generic machine
297 * configure: Regenerate.
299 2007-02-17 Thiemo Seufer <ths@mips.com>
301 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
302 Add mdmx to sim_igen_machine.
303 (mipsisa64*-*-*): Likewise. Remove dsp.
304 (mipsisa32*-*-*): Remove dsp.
305 * configure: Regenerate.
307 2007-02-13 Thiemo Seufer <ths@mips.com>
309 * configure.ac: Add mips*-sde-elf* target.
310 * configure: Regenerate.
312 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
314 * acconfig.h: Remove.
315 * config.in, configure: Regenerate.
317 2006-11-07 Thiemo Seufer <ths@mips.com>
319 * dsp.igen (do_w_op): Fix compiler warning.
321 2006-08-29 Thiemo Seufer <ths@mips.com>
322 David Ung <davidu@mips.com>
324 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
326 * configure: Regenerate.
327 * mips.igen (model): Add smartmips.
328 (MADDU): Increment ACX if carry.
329 (do_mult): Clear ACX.
330 (ROR,RORV): Add smartmips.
331 (include): Include smartmips.igen.
332 * sim-main.h (ACX): Set to REGISTERS[89].
333 * smartmips.igen: New file.
335 2006-08-29 Thiemo Seufer <ths@mips.com>
336 David Ung <davidu@mips.com>
338 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
339 mips3264r2.igen. Add missing dependency rules.
340 * m16e.igen: Support for mips16e save/restore instructions.
342 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
344 * configure: Regenerated.
346 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
348 * configure: Regenerated.
350 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
352 * configure: Regenerated.
354 2006-05-15 Chao-ying Fu <fu@mips.com>
356 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
358 2006-04-18 Nick Clifton <nickc@redhat.com>
360 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
363 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
365 * configure: Regenerate.
367 2005-12-14 Chao-ying Fu <fu@mips.com>
369 * Makefile.in (SIM_OBJS): Add dsp.o.
370 (dsp.o): New dependency.
371 (IGEN_INCLUDE): Add dsp.igen.
372 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
373 mipsisa64*-*-*): Add dsp to sim_igen_machine.
374 * configure: Regenerate.
375 * mips.igen: Add dsp model and include dsp.igen.
376 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
377 because these instructions are extended in DSP ASE.
378 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
379 adding 6 DSP accumulator registers and 1 DSP control register.
380 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
381 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
382 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
383 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
384 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
385 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
386 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
387 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
388 DSPCR_CCOND_SMASK): New define.
389 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
390 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
392 2005-07-08 Ian Lance Taylor <ian@airs.com>
394 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
396 2005-06-16 David Ung <davidu@mips.com>
397 Nigel Stephens <nigel@mips.com>
399 * mips.igen: New mips16e model and include m16e.igen.
400 (check_u64): Add mips16e tag.
401 * m16e.igen: New file for MIPS16e instructions.
402 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
403 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
405 * configure: Regenerate.
407 2005-05-26 David Ung <davidu@mips.com>
409 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
410 tags to all instructions which are applicable to the new ISAs.
411 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
413 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
415 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
417 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
418 * configure: Regenerate.
420 2005-03-23 Mark Kettenis <kettenis@gnu.org>
422 * configure: Regenerate.
424 2005-01-14 Andrew Cagney <cagney@gnu.org>
426 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
427 explicit call to AC_CONFIG_HEADER.
428 * configure: Regenerate.
430 2005-01-12 Andrew Cagney <cagney@gnu.org>
432 * configure.ac: Update to use ../common/common.m4.
433 * configure: Re-generate.
435 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
437 * configure: Regenerated to track ../common/aclocal.m4 changes.
439 2005-01-07 Andrew Cagney <cagney@gnu.org>
441 * configure.ac: Rename configure.in, require autoconf 2.59.
442 * configure: Re-generate.
444 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
446 * configure: Regenerate for ../common/aclocal.m4 update.
448 2004-09-24 Monika Chaddha <monika@acmet.com>
450 Committed by Andrew Cagney.
451 * m16.igen (CMP, CMPI): Fix assembler.
453 2004-08-18 Chris Demetriou <cgd@broadcom.com>
455 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
456 * configure: Regenerate.
458 2004-06-25 Chris Demetriou <cgd@broadcom.com>
460 * configure.in (sim_m16_machine): Include mipsIII.
461 * configure: Regenerate.
463 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
465 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
467 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
469 2004-04-10 Chris Demetriou <cgd@broadcom.com>
471 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
473 2004-04-09 Chris Demetriou <cgd@broadcom.com>
475 * mips.igen (check_fmt): Remove.
476 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
477 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
478 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
479 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
480 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
481 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
482 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
483 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
484 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
485 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
487 2004-04-09 Chris Demetriou <cgd@broadcom.com>
489 * sb1.igen (check_sbx): New function.
490 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
492 2004-03-29 Chris Demetriou <cgd@broadcom.com>
493 Richard Sandiford <rsandifo@redhat.com>
495 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
496 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
497 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
498 separate implementations for mipsIV and mipsV. Use new macros to
499 determine whether the restrictions apply.
501 2004-01-19 Chris Demetriou <cgd@broadcom.com>
503 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
504 (check_mult_hilo): Improve comments.
505 (check_div_hilo): Likewise. Also, fork off a new version
506 to handle mips32/mips64 (since there are no hazards to check
509 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
511 * mips.igen (do_dmultx): Fix check for negative operands.
513 2003-05-16 Ian Lance Taylor <ian@airs.com>
515 * Makefile.in (SHELL): Make sure this is defined.
516 (various): Use $(SHELL) whenever we invoke move-if-change.
518 2003-05-03 Chris Demetriou <cgd@broadcom.com>
520 * cp1.c: Tweak attribution slightly.
523 * mdmx.igen: Likewise.
524 * mips3d.igen: Likewise.
525 * sb1.igen: Likewise.
527 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
529 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
532 2003-02-27 Andrew Cagney <cagney@redhat.com>
534 * interp.c (sim_open): Rename _bfd to bfd.
535 (sim_create_inferior): Ditto.
537 2003-01-14 Chris Demetriou <cgd@broadcom.com>
539 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
541 2003-01-14 Chris Demetriou <cgd@broadcom.com>
543 * mips.igen (EI, DI): Remove.
545 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
547 * Makefile.in (tmp-run-multi): Fix mips16 filter.
549 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
550 Andrew Cagney <ac131313@redhat.com>
551 Gavin Romig-Koch <gavin@redhat.com>
552 Graydon Hoare <graydon@redhat.com>
553 Aldy Hernandez <aldyh@redhat.com>
554 Dave Brolley <brolley@redhat.com>
555 Chris Demetriou <cgd@broadcom.com>
557 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
558 (sim_mach_default): New variable.
559 (mips64vr-*-*, mips64vrel-*-*): New configurations.
560 Add a new simulator generator, MULTI.
561 * configure: Regenerate.
562 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
563 (multi-run.o): New dependency.
564 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
565 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
566 (tmp-multi): Combine them.
567 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
568 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
569 (distclean-extra): New rule.
570 * sim-main.h: Include bfd.h.
571 (MIPS_MACH): New macro.
572 * mips.igen (vr4120, vr5400, vr5500): New models.
573 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
574 * vr.igen: Replace with new version.
576 2003-01-04 Chris Demetriou <cgd@broadcom.com>
578 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
579 * configure: Regenerate.
581 2002-12-31 Chris Demetriou <cgd@broadcom.com>
583 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
584 * mips.igen: Remove all invocations of check_branch_bug and
587 2002-12-16 Chris Demetriou <cgd@broadcom.com>
589 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
591 2002-07-30 Chris Demetriou <cgd@broadcom.com>
593 * mips.igen (do_load_double, do_store_double): New functions.
594 (LDC1, SDC1): Rename to...
595 (LDC1b, SDC1b): respectively.
596 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
598 2002-07-29 Michael Snyder <msnyder@redhat.com>
600 * cp1.c (fp_recip2): Modify initialization expression so that
601 GCC will recognize it as constant.
603 2002-06-18 Chris Demetriou <cgd@broadcom.com>
605 * mdmx.c (SD_): Delete.
606 (Unpredictable): Re-define, for now, to directly invoke
607 unpredictable_action().
608 (mdmx_acc_op): Fix error in .ob immediate handling.
610 2002-06-18 Andrew Cagney <cagney@redhat.com>
612 * interp.c (sim_firmware_command): Initialize `address'.
614 2002-06-16 Andrew Cagney <ac131313@redhat.com>
616 * configure: Regenerated to track ../common/aclocal.m4 changes.
618 2002-06-14 Chris Demetriou <cgd@broadcom.com>
619 Ed Satterthwaite <ehs@broadcom.com>
621 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
622 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
623 * mips.igen: Include mips3d.igen.
624 (mips3d): New model name for MIPS-3D ASE instructions.
625 (CVT.W.fmt): Don't use this instruction for word (source) format
627 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
628 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
629 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
630 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
631 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
632 (RSquareRoot1, RSquareRoot2): New macros.
633 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
634 (fp_rsqrt2): New functions.
635 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
636 * configure: Regenerate.
638 2002-06-13 Chris Demetriou <cgd@broadcom.com>
639 Ed Satterthwaite <ehs@broadcom.com>
641 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
642 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
643 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
644 (convert): Note that this function is not used for paired-single
646 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
647 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
648 (check_fmt_p): Enable paired-single support.
649 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
650 (PUU.PS): New instructions.
651 (CVT.S.fmt): Don't use this instruction for paired-single format
653 * sim-main.h (FP_formats): New value 'fmt_ps.'
654 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
655 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
657 2002-06-12 Chris Demetriou <cgd@broadcom.com>
659 * mips.igen: Fix formatting of function calls in
662 2002-06-12 Chris Demetriou <cgd@broadcom.com>
664 * mips.igen (MOVN, MOVZ): Trace result.
665 (TNEI): Print "tnei" as the opcode name in traces.
666 (CEIL.W): Add disassembly string for traces.
667 (RSQRT.fmt): Make location of disassembly string consistent
668 with other instructions.
670 2002-06-12 Chris Demetriou <cgd@broadcom.com>
672 * mips.igen (X): Delete unused function.
674 2002-06-08 Andrew Cagney <cagney@redhat.com>
676 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
678 2002-06-07 Chris Demetriou <cgd@broadcom.com>
679 Ed Satterthwaite <ehs@broadcom.com>
681 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
682 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
683 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
684 (fp_nmsub): New prototypes.
685 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
686 (NegMultiplySub): New defines.
687 * mips.igen (RSQRT.fmt): Use RSquareRoot().
688 (MADD.D, MADD.S): Replace with...
689 (MADD.fmt): New instruction.
690 (MSUB.D, MSUB.S): Replace with...
691 (MSUB.fmt): New instruction.
692 (NMADD.D, NMADD.S): Replace with...
693 (NMADD.fmt): New instruction.
694 (NMSUB.D, MSUB.S): Replace with...
695 (NMSUB.fmt): New instruction.
697 2002-06-07 Chris Demetriou <cgd@broadcom.com>
698 Ed Satterthwaite <ehs@broadcom.com>
700 * cp1.c: Fix more comment spelling and formatting.
701 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
702 (denorm_mode): New function.
703 (fpu_unary, fpu_binary): Round results after operation, collect
704 status from rounding operations, and update the FCSR.
705 (convert): Collect status from integer conversions and rounding
706 operations, and update the FCSR. Adjust NaN values that result
707 from conversions. Convert to use sim_io_eprintf rather than
708 fprintf, and remove some debugging code.
709 * cp1.h (fenr_FS): New define.
711 2002-06-07 Chris Demetriou <cgd@broadcom.com>
713 * cp1.c (convert): Remove unusable debugging code, and move MIPS
714 rounding mode to sim FP rounding mode flag conversion code into...
715 (rounding_mode): New function.
717 2002-06-07 Chris Demetriou <cgd@broadcom.com>
719 * cp1.c: Clean up formatting of a few comments.
720 (value_fpr): Reformat switch statement.
722 2002-06-06 Chris Demetriou <cgd@broadcom.com>
723 Ed Satterthwaite <ehs@broadcom.com>
726 * sim-main.h: Include cp1.h.
727 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
728 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
729 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
730 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
731 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
732 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
733 * cp1.c: Don't include sim-fpu.h; already included by
734 sim-main.h. Clean up formatting of some comments.
735 (NaN, Equal, Less): Remove.
736 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
737 (fp_cmp): New functions.
738 * mips.igen (do_c_cond_fmt): Remove.
739 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
740 Compare. Add result tracing.
741 (CxC1): Remove, replace with...
742 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
743 (DMxC1): Remove, replace with...
744 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
745 (MxC1): Remove, replace with...
746 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
748 2002-06-04 Chris Demetriou <cgd@broadcom.com>
750 * sim-main.h (FGRIDX): Remove, replace all uses with...
751 (FGR_BASE): New macro.
752 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
753 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
754 (NR_FGR, FGR): Likewise.
755 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
756 * mips.igen: Likewise.
758 2002-06-04 Chris Demetriou <cgd@broadcom.com>
760 * cp1.c: Add an FSF Copyright notice to this file.
762 2002-06-04 Chris Demetriou <cgd@broadcom.com>
763 Ed Satterthwaite <ehs@broadcom.com>
765 * cp1.c (Infinity): Remove.
766 * sim-main.h (Infinity): Likewise.
768 * cp1.c (fp_unary, fp_binary): New functions.
769 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
770 (fp_sqrt): New functions, implemented in terms of the above.
771 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
772 (Recip, SquareRoot): Remove (replaced by functions above).
773 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
774 (fp_recip, fp_sqrt): New prototypes.
775 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
776 (Recip, SquareRoot): Replace prototypes with #defines which
777 invoke the functions above.
779 2002-06-03 Chris Demetriou <cgd@broadcom.com>
781 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
782 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
783 file, remove PARAMS from prototypes.
784 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
785 simulator state arguments.
786 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
787 pass simulator state arguments.
788 * cp1.c (SD): Redefine as CPU_STATE(cpu).
789 (store_fpr, convert): Remove 'sd' argument.
790 (value_fpr): Likewise. Convert to use 'SD' instead.
792 2002-06-03 Chris Demetriou <cgd@broadcom.com>
794 * cp1.c (Min, Max): Remove #if 0'd functions.
795 * sim-main.h (Min, Max): Remove.
797 2002-06-03 Chris Demetriou <cgd@broadcom.com>
799 * cp1.c: fix formatting of switch case and default labels.
800 * interp.c: Likewise.
801 * sim-main.c: Likewise.
803 2002-06-03 Chris Demetriou <cgd@broadcom.com>
805 * cp1.c: Clean up comments which describe FP formats.
806 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
808 2002-06-03 Chris Demetriou <cgd@broadcom.com>
809 Ed Satterthwaite <ehs@broadcom.com>
811 * configure.in (mipsisa64sb1*-*-*): New target for supporting
812 Broadcom SiByte SB-1 processor configurations.
813 * configure: Regenerate.
814 * sb1.igen: New file.
815 * mips.igen: Include sb1.igen.
817 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
818 * mdmx.igen: Add "sb1" model to all appropriate functions and
820 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
821 (ob_func, ob_acc): Reference the above.
822 (qh_acc): Adjust to keep the same size as ob_acc.
823 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
824 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
826 2002-06-03 Chris Demetriou <cgd@broadcom.com>
828 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
830 2002-06-02 Chris Demetriou <cgd@broadcom.com>
831 Ed Satterthwaite <ehs@broadcom.com>
833 * mips.igen (mdmx): New (pseudo-)model.
834 * mdmx.c, mdmx.igen: New files.
835 * Makefile.in (SIM_OBJS): Add mdmx.o.
836 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
838 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
839 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
840 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
841 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
842 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
843 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
844 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
845 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
846 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
847 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
848 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
849 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
850 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
851 (qh_fmtsel): New macros.
852 (_sim_cpu): New member "acc".
853 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
854 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
856 2002-05-01 Chris Demetriou <cgd@broadcom.com>
858 * interp.c: Use 'deprecated' rather than 'depreciated.'
859 * sim-main.h: Likewise.
861 2002-05-01 Chris Demetriou <cgd@broadcom.com>
863 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
864 which wouldn't compile anyway.
865 * sim-main.h (unpredictable_action): New function prototype.
866 (Unpredictable): Define to call igen function unpredictable().
867 (NotWordValue): New macro to call igen function not_word_value().
868 (UndefinedResult): Remove.
869 * interp.c (undefined_result): Remove.
870 (unpredictable_action): New function.
871 * mips.igen (not_word_value, unpredictable): New functions.
872 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
873 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
874 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
875 NotWordValue() to check for unpredictable inputs, then
876 Unpredictable() to handle them.
878 2002-02-24 Chris Demetriou <cgd@broadcom.com>
880 * mips.igen: Fix formatting of calls to Unpredictable().
882 2002-04-20 Andrew Cagney <ac131313@redhat.com>
884 * interp.c (sim_open): Revert previous change.
886 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
888 * interp.c (sim_open): Disable chunk of code that wrote code in
889 vector table entries.
891 2002-03-19 Chris Demetriou <cgd@broadcom.com>
893 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
894 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
897 2002-03-19 Chris Demetriou <cgd@broadcom.com>
899 * cp1.c: Fix many formatting issues.
901 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
903 * cp1.c (fpu_format_name): New function to replace...
904 (DOFMT): This. Delete, and update all callers.
905 (fpu_rounding_mode_name): New function to replace...
906 (RMMODE): This. Delete, and update all callers.
908 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
910 * interp.c: Move FPU support routines from here to...
911 * cp1.c: Here. New file.
912 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
915 2002-03-12 Chris Demetriou <cgd@broadcom.com>
917 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
918 * mips.igen (mips32, mips64): New models, add to all instructions
919 and functions as appropriate.
920 (loadstore_ea, check_u64): New variant for model mips64.
921 (check_fmt_p): New variant for models mipsV and mips64, remove
922 mipsV model marking fro other variant.
925 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
926 for mips32 and mips64.
927 (DCLO, DCLZ): New instructions for mips64.
929 2002-03-07 Chris Demetriou <cgd@broadcom.com>
931 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
932 immediate or code as a hex value with the "%#lx" format.
933 (ANDI): Likewise, and fix printed instruction name.
935 2002-03-05 Chris Demetriou <cgd@broadcom.com>
937 * sim-main.h (UndefinedResult, Unpredictable): New macros
938 which currently do nothing.
940 2002-03-05 Chris Demetriou <cgd@broadcom.com>
942 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
943 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
944 (status_CU3): New definitions.
946 * sim-main.h (ExceptionCause): Add new values for MIPS32
947 and MIPS64: MDMX, MCheck, CacheErr. Update comments
948 for DebugBreakPoint and NMIReset to note their status in
950 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
951 (SignalExceptionCacheErr): New exception macros.
953 2002-03-05 Chris Demetriou <cgd@broadcom.com>
955 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
956 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
958 (SignalExceptionCoProcessorUnusable): Take as argument the
959 unusable coprocessor number.
961 2002-03-05 Chris Demetriou <cgd@broadcom.com>
963 * mips.igen: Fix formatting of all SignalException calls.
965 2002-03-05 Chris Demetriou <cgd@broadcom.com>
967 * sim-main.h (SIGNEXTEND): Remove.
969 2002-03-04 Chris Demetriou <cgd@broadcom.com>
971 * mips.igen: Remove gencode comment from top of file, fix
972 spelling in another comment.
974 2002-03-04 Chris Demetriou <cgd@broadcom.com>
976 * mips.igen (check_fmt, check_fmt_p): New functions to check
977 whether specific floating point formats are usable.
978 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
979 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
980 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
981 Use the new functions.
982 (do_c_cond_fmt): Remove format checks...
983 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
985 2002-03-03 Chris Demetriou <cgd@broadcom.com>
987 * mips.igen: Fix formatting of check_fpu calls.
989 2002-03-03 Chris Demetriou <cgd@broadcom.com>
991 * mips.igen (FLOOR.L.fmt): Store correct destination register.
993 2002-03-03 Chris Demetriou <cgd@broadcom.com>
995 * mips.igen: Remove whitespace at end of lines.
997 2002-03-02 Chris Demetriou <cgd@broadcom.com>
999 * mips.igen (loadstore_ea): New function to do effective
1000 address calculations.
1001 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1002 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1003 CACHE): Use loadstore_ea to do effective address computations.
1005 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1007 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1008 * mips.igen (LL, CxC1, MxC1): Likewise.
1010 2002-03-02 Chris Demetriou <cgd@broadcom.com>
1012 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1013 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1014 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1015 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1016 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1017 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1018 Don't split opcode fields by hand, use the opcode field values
1021 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1023 * mips.igen (do_divu): Fix spacing.
1025 * mips.igen (do_dsllv): Move to be right before DSLLV,
1026 to match the rest of the do_<shift> functions.
1028 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1030 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1031 DSRL32, do_dsrlv): Trace inputs and results.
1033 2002-03-01 Chris Demetriou <cgd@broadcom.com>
1035 * mips.igen (CACHE): Provide instruction-printing string.
1037 * interp.c (signal_exception): Comment tokens after #endif.
1039 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1041 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1042 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1043 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1044 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1045 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1046 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1047 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1048 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1050 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1052 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1053 instruction-printing string.
1054 (LWU): Use '64' as the filter flag.
1056 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1058 * mips.igen (SDXC1): Fix instruction-printing string.
1060 2002-02-28 Chris Demetriou <cgd@broadcom.com>
1062 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1063 filter flags "32,f".
1065 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1067 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1070 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1072 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1073 add a comma) so that it more closely match the MIPS ISA
1074 documentation opcode partitioning.
1075 (PREF): Put useful names on opcode fields, and include
1076 instruction-printing string.
1078 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1080 * mips.igen (check_u64): New function which in the future will
1081 check whether 64-bit instructions are usable and signal an
1082 exception if not. Currently a no-op.
1083 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1084 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1085 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1086 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1088 * mips.igen (check_fpu): New function which in the future will
1089 check whether FPU instructions are usable and signal an exception
1090 if not. Currently a no-op.
1091 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1092 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1093 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1094 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1095 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1096 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1097 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1098 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1100 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1102 * mips.igen (do_load_left, do_load_right): Move to be immediately
1104 (do_store_left, do_store_right): Move to be immediately following
1107 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1109 * mips.igen (mipsV): New model name. Also, add it to
1110 all instructions and functions where it is appropriate.
1112 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1114 * mips.igen: For all functions and instructions, list model
1115 names that support that instruction one per line.
1117 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1119 * mips.igen: Add some additional comments about supported
1120 models, and about which instructions go where.
1121 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1122 order as is used in the rest of the file.
1124 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1126 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1127 indicating that ALU32_END or ALU64_END are there to check
1129 (DADD): Likewise, but also remove previous comment about
1132 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1134 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1135 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1136 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1137 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1138 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1139 fields (i.e., add and move commas) so that they more closely
1140 match the MIPS ISA documentation opcode partitioning.
1142 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1144 * mips.igen (ADDI): Print immediate value.
1145 (BREAK): Print code.
1146 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1147 (SLL): Print "nop" specially, and don't run the code
1148 that does the shift for the "nop" case.
1150 2001-11-17 Fred Fish <fnf@redhat.com>
1152 * sim-main.h (float_operation): Move enum declaration outside
1153 of _sim_cpu struct declaration.
1155 2001-04-12 Jim Blandy <jimb@redhat.com>
1157 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1158 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1160 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1161 PENDING_FILL, and you can get the intended effect gracefully by
1162 calling PENDING_SCHED directly.
1164 2001-02-23 Ben Elliston <bje@redhat.com>
1166 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1167 already defined elsewhere.
1169 2001-02-19 Ben Elliston <bje@redhat.com>
1171 * sim-main.h (sim_monitor): Return an int.
1172 * interp.c (sim_monitor): Add return values.
1173 (signal_exception): Handle error conditions from sim_monitor.
1175 2001-02-08 Ben Elliston <bje@redhat.com>
1177 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1178 (store_memory): Likewise, pass cia to sim_core_write*.
1180 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1182 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1183 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1185 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1187 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1188 * Makefile.in: Don't delete *.igen when cleaning directory.
1190 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1192 * m16.igen (break): Call SignalException not sim_engine_halt.
1194 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1196 From Jason Eckhardt:
1197 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1199 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1201 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1203 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1205 * mips.igen (do_dmultx): Fix typo.
1207 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1209 * configure: Regenerated to track ../common/aclocal.m4 changes.
1211 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1213 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1215 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1217 * sim-main.h (GPR_CLEAR): Define macro.
1219 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1221 * interp.c (decode_coproc): Output long using %lx and not %s.
1223 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1225 * interp.c (sim_open): Sort & extend dummy memory regions for
1226 --board=jmr3904 for eCos.
1228 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1230 * configure: Regenerated.
1232 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1234 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1235 calls, conditional on the simulator being in verbose mode.
1237 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1239 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1240 cache don't get ReservedInstruction traps.
1242 1999-11-29 Mark Salter <msalter@cygnus.com>
1244 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1245 to clear status bits in sdisr register. This is how the hardware works.
1247 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1248 being used by cygmon.
1250 1999-11-11 Andrew Haley <aph@cygnus.com>
1252 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1255 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1257 * mips.igen (MULT): Correct previous mis-applied patch.
1259 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1261 * mips.igen (delayslot32): Handle sequence like
1262 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1263 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1264 (MULT): Actually pass the third register...
1266 1999-09-03 Mark Salter <msalter@cygnus.com>
1268 * interp.c (sim_open): Added more memory aliases for additional
1269 hardware being touched by cygmon on jmr3904 board.
1271 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1273 * configure: Regenerated to track ../common/aclocal.m4 changes.
1275 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1277 * interp.c (sim_store_register): Handle case where client - GDB -
1278 specifies that a 4 byte register is 8 bytes in size.
1279 (sim_fetch_register): Ditto.
1281 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1283 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1284 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1285 (idt_monitor_base): Base address for IDT monitor traps.
1286 (pmon_monitor_base): Ditto for PMON.
1287 (lsipmon_monitor_base): Ditto for LSI PMON.
1288 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1289 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1290 (sim_firmware_command): New function.
1291 (mips_option_handler): Call it for OPTION_FIRMWARE.
1292 (sim_open): Allocate memory for idt_monitor region. If "--board"
1293 option was given, add no monitor by default. Add BREAK hooks only if
1294 monitors are also there.
1296 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1298 * interp.c (sim_monitor): Flush output before reading input.
1300 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1302 * tconfig.in (SIM_HANDLES_LMA): Always define.
1304 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1306 From Mark Salter <msalter@cygnus.com>:
1307 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1308 (sim_open): Add setup for BSP board.
1310 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1312 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1313 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1314 them as unimplemented.
1316 1999-05-08 Felix Lee <flee@cygnus.com>
1318 * configure: Regenerated to track ../common/aclocal.m4 changes.
1320 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1322 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1324 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1326 * configure.in: Any mips64vr5*-*-* target should have
1327 -DTARGET_ENABLE_FR=1.
1328 (default_endian): Any mips64vr*el-*-* target should default to
1330 * configure: Re-generate.
1332 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1334 * mips.igen (ldl): Extend from _16_, not 32.
1336 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1338 * interp.c (sim_store_register): Force registers written to by GDB
1339 into an un-interpreted state.
1341 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1343 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1344 CPU, start periodic background I/O polls.
1345 (tx3904sio_poll): New function: periodic I/O poller.
1347 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1349 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1351 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1353 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1356 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1358 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1359 (load_word): Call SIM_CORE_SIGNAL hook on error.
1360 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1361 starting. For exception dispatching, pass PC instead of NULL_CIA.
1362 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1363 * sim-main.h (COP0_BADVADDR): Define.
1364 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1365 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1366 (_sim_cpu): Add exc_* fields to store register value snapshots.
1367 * mips.igen (*): Replace memory-related SignalException* calls
1368 with references to SIM_CORE_SIGNAL hook.
1370 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1372 * sim-main.c (*): Minor warning cleanups.
1374 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1376 * m16.igen (DADDIU5): Correct type-o.
1378 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1380 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1383 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1385 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1387 (interp.o): Add dependency on itable.h
1388 (oengine.c, gencode): Delete remaining references.
1389 (BUILT_SRC_FROM_GEN): Clean up.
1391 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1394 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1395 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1396 tmp-run-hack) : New.
1397 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1398 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1399 Drop the "64" qualifier to get the HACK generator working.
1400 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1401 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1402 qualifier to get the hack generator working.
1403 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1404 (DSLL): Use do_dsll.
1405 (DSLLV): Use do_dsllv.
1406 (DSRA): Use do_dsra.
1407 (DSRL): Use do_dsrl.
1408 (DSRLV): Use do_dsrlv.
1409 (BC1): Move *vr4100 to get the HACK generator working.
1410 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1411 get the HACK generator working.
1412 (MACC) Rename to get the HACK generator working.
1413 (DMACC,MACCS,DMACCS): Add the 64.
1415 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1417 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1418 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1420 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1422 * mips/interp.c (DEBUG): Cleanups.
1424 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1426 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1427 (tx3904sio_tickle): fflush after a stdout character output.
1429 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1431 * interp.c (sim_close): Uninstall modules.
1433 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1435 * sim-main.h, interp.c (sim_monitor): Change to global
1438 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440 * configure.in (vr4100): Only include vr4100 instructions in
1442 * configure: Re-generate.
1443 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1445 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1448 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1451 * configure.in (sim_default_gen, sim_use_gen): Replace with
1453 (--enable-sim-igen): Delete config option. Always using IGEN.
1454 * configure: Re-generate.
1456 * Makefile.in (gencode): Kill, kill, kill.
1459 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1462 bit mips16 igen simulator.
1463 * configure: Re-generate.
1465 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1466 as part of vr4100 ISA.
1467 * vr.igen: Mark all instructions as 64 bit only.
1469 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1474 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1476 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1477 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1478 * configure: Re-generate.
1480 * m16.igen (BREAK): Define breakpoint instruction.
1481 (JALX32): Mark instruction as mips16 and not r3900.
1482 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1484 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1486 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1489 insn as a debug breakpoint.
1491 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1493 (PENDING_SCHED): Clean up trace statement.
1494 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1495 (PENDING_FILL): Delay write by only one cycle.
1496 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1498 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1500 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1502 (pending_tick): Move incrementing of index to FOR statement.
1503 (pending_tick): Only update PENDING_OUT after a write has occured.
1505 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1507 * configure: Re-generate.
1509 * interp.c (sim_engine_run OLD): Delete explicit call to
1510 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1512 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1514 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1515 interrupt level number to match changed SignalExceptionInterrupt
1518 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1520 * interp.c: #include "itable.h" if WITH_IGEN.
1521 (get_insn_name): New function.
1522 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1523 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1525 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1527 * configure: Rebuilt to inhale new common/aclocal.m4.
1529 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1531 * dv-tx3904sio.c: Include sim-assert.h.
1533 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1535 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1536 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1537 Reorganize target-specific sim-hardware checks.
1538 * configure: rebuilt.
1539 * interp.c (sim_open): For tx39 target boards, set
1540 OPERATING_ENVIRONMENT, add tx3904sio devices.
1541 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1542 ROM executables. Install dv-sockser into sim-modules list.
1544 * dv-tx3904irc.c: Compiler warning clean-up.
1545 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1546 frequent hw-trace messages.
1548 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1550 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1552 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1554 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1556 * vr.igen: New file.
1557 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1558 * mips.igen: Define vr4100 model. Include vr.igen.
1559 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1561 * mips.igen (check_mf_hilo): Correct check.
1563 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565 * sim-main.h (interrupt_event): Add prototype.
1567 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1568 register_ptr, register_value.
1569 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1571 * sim-main.h (tracefh): Make extern.
1573 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1575 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1576 Reduce unnecessarily high timer event frequency.
1577 * dv-tx3904cpu.c: Ditto for interrupt event.
1579 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1581 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1583 (interrupt_event): Made non-static.
1585 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1586 interchange of configuration values for external vs. internal
1589 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1591 * mips.igen (BREAK): Moved code to here for
1592 simulator-reserved break instructions.
1593 * gencode.c (build_instruction): Ditto.
1594 * interp.c (signal_exception): Code moved from here. Non-
1595 reserved instructions now use exception vector, rather
1597 * sim-main.h: Moved magic constants to here.
1599 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1601 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1602 register upon non-zero interrupt event level, clear upon zero
1604 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1605 by passing zero event value.
1606 (*_io_{read,write}_buffer): Endianness fixes.
1607 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1608 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1610 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1611 serial I/O and timer module at base address 0xFFFF0000.
1613 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1615 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1618 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1620 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1622 * configure: Update.
1624 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1626 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1627 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1628 * configure.in: Include tx3904tmr in hw_device list.
1629 * configure: Rebuilt.
1630 * interp.c (sim_open): Instantiate three timer instances.
1631 Fix address typo of tx3904irc instance.
1633 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1635 * interp.c (signal_exception): SystemCall exception now uses
1636 the exception vector.
1638 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1640 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1643 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1645 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1647 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1649 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1651 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1652 sim-main.h. Declare a struct hw_descriptor instead of struct
1653 hw_device_descriptor.
1655 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1657 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1658 right bits and then re-align left hand bytes to correct byte
1659 lanes. Fix incorrect computation in do_store_left when loading
1660 bytes from second word.
1662 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1664 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1665 * interp.c (sim_open): Only create a device tree when HW is
1668 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1669 * interp.c (signal_exception): Ditto.
1671 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1673 * gencode.c: Mark BEGEZALL as LIKELY.
1675 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1677 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1678 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1680 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1682 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1683 modules. Recognize TX39 target with "mips*tx39" pattern.
1684 * configure: Rebuilt.
1685 * sim-main.h (*): Added many macros defining bits in
1686 TX39 control registers.
1687 (SignalInterrupt): Send actual PC instead of NULL.
1688 (SignalNMIReset): New exception type.
1689 * interp.c (board): New variable for future use to identify
1690 a particular board being simulated.
1691 (mips_option_handler,mips_options): Added "--board" option.
1692 (interrupt_event): Send actual PC.
1693 (sim_open): Make memory layout conditional on board setting.
1694 (signal_exception): Initial implementation of hardware interrupt
1695 handling. Accept another break instruction variant for simulator
1697 (decode_coproc): Implement RFE instruction for TX39.
1698 (mips.igen): Decode RFE instruction as such.
1699 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1700 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1701 bbegin to implement memory map.
1702 * dv-tx3904cpu.c: New file.
1703 * dv-tx3904irc.c: New file.
1705 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1707 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1709 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1711 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1712 with calls to check_div_hilo.
1714 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1716 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1717 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1718 Add special r3900 version of do_mult_hilo.
1719 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1720 with calls to check_mult_hilo.
1721 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1722 with calls to check_div_hilo.
1724 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1726 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1727 Document a replacement.
1729 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1731 * interp.c (sim_monitor): Make mon_printf work.
1733 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1735 * sim-main.h (INSN_NAME): New arg `cpu'.
1737 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1739 * configure: Regenerated to track ../common/aclocal.m4 changes.
1741 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1743 * configure: Regenerated to track ../common/aclocal.m4 changes.
1746 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1748 * acconfig.h: New file.
1749 * configure.in: Reverted change of Apr 24; use sinclude again.
1751 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1756 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1758 * configure.in: Don't call sinclude.
1760 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1762 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1764 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1766 * mips.igen (ERET): Implement.
1768 * interp.c (decode_coproc): Return sign-extended EPC.
1770 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1772 * interp.c (signal_exception): Do not ignore Trap.
1773 (signal_exception): On TRAP, restart at exception address.
1774 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1775 (signal_exception): Update.
1776 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1777 so that TRAP instructions are caught.
1779 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1781 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1782 contains HI/LO access history.
1783 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1784 (HIACCESS, LOACCESS): Delete, replace with
1785 (HIHISTORY, LOHISTORY): New macros.
1786 (CHECKHILO): Delete all, moved to mips.igen
1788 * gencode.c (build_instruction): Do not generate checks for
1789 correct HI/LO register usage.
1791 * interp.c (old_engine_run): Delete checks for correct HI/LO
1794 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1795 check_mf_cycles): New functions.
1796 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1797 do_divu, domultx, do_mult, do_multu): Use.
1799 * tx.igen ("madd", "maddu"): Use.
1801 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1803 * mips.igen (DSRAV): Use function do_dsrav.
1804 (SRAV): Use new function do_srav.
1806 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1807 (B): Sign extend 11 bit immediate.
1808 (EXT-B*): Shift 16 bit immediate left by 1.
1809 (ADDIU*): Don't sign extend immediate value.
1811 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1813 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1815 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1818 * mips.igen (delayslot32, nullify_next_insn): New functions.
1819 (m16.igen): Always include.
1820 (do_*): Add more tracing.
1822 * m16.igen (delayslot16): Add NIA argument, could be called by a
1823 32 bit MIPS16 instruction.
1825 * interp.c (ifetch16): Move function from here.
1826 * sim-main.c (ifetch16): To here.
1828 * sim-main.c (ifetch16, ifetch32): Update to match current
1829 implementations of LH, LW.
1830 (signal_exception): Don't print out incorrect hex value of illegal
1833 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1835 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1838 * m16.igen: Implement MIPS16 instructions.
1840 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1841 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1842 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1843 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1844 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1845 bodies of corresponding code from 32 bit insn to these. Also used
1846 by MIPS16 versions of functions.
1848 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1849 (IMEM16): Drop NR argument from macro.
1851 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1853 * Makefile.in (SIM_OBJS): Add sim-main.o.
1855 * sim-main.h (address_translation, load_memory, store_memory,
1856 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1858 (pr_addr, pr_uword64): Declare.
1859 (sim-main.c): Include when H_REVEALS_MODULE_P.
1861 * interp.c (address_translation, load_memory, store_memory,
1862 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1864 * sim-main.c: To here. Fix compilation problems.
1866 * configure.in: Enable inlining.
1867 * configure: Re-config.
1869 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
1873 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1875 * mips.igen: Include tx.igen.
1876 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1877 * tx.igen: New file, contains MADD and MADDU.
1879 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1880 the hardwired constant `7'.
1881 (store_memory): Ditto.
1882 (LOADDRMASK): Move definition to sim-main.h.
1884 mips.igen (MTC0): Enable for r3900.
1887 mips.igen (do_load_byte): Delete.
1888 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1889 do_store_right): New functions.
1890 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1892 configure.in: Let the tx39 use igen again.
1895 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1897 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1898 not an address sized quantity. Return zero for cache sizes.
1900 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902 * mips.igen (r3900): r3900 does not support 64 bit integer
1905 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1907 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1909 * configure : Rebuild.
1911 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1913 * configure: Regenerated to track ../common/aclocal.m4 changes.
1915 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1917 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1919 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1924 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1926 * configure: Regenerated to track ../common/aclocal.m4 changes.
1928 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1930 * interp.c (Max, Min): Comment out functions. Not yet used.
1932 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934 * configure: Regenerated to track ../common/aclocal.m4 changes.
1936 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1938 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1939 configurable settings for stand-alone simulator.
1941 * configure.in: Added X11 search, just in case.
1943 * configure: Regenerated.
1945 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1947 * interp.c (sim_write, sim_read, load_memory, store_memory):
1948 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1950 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1952 * sim-main.h (GETFCC): Return an unsigned value.
1954 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1956 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1957 (DADD): Result destination is RD not RT.
1959 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1961 * sim-main.h (HIACCESS, LOACCESS): Always define.
1963 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1965 * interp.c (sim_info): Delete.
1967 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1969 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1970 (mips_option_handler): New argument `cpu'.
1971 (sim_open): Update call to sim_add_option_table.
1973 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1975 * mips.igen (CxC1): Add tracing.
1977 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1979 * sim-main.h (Max, Min): Declare.
1981 * interp.c (Max, Min): New functions.
1983 * mips.igen (BC1): Add tracing.
1985 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1987 * interp.c Added memory map for stack in vr4100
1989 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1991 * interp.c (load_memory): Add missing "break"'s.
1993 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995 * interp.c (sim_store_register, sim_fetch_register): Pass in
1996 length parameter. Return -1.
1998 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2000 * interp.c: Added hardware init hook, fixed warnings.
2002 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2004 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2006 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2008 * interp.c (ifetch16): New function.
2010 * sim-main.h (IMEM32): Rename IMEM.
2011 (IMEM16_IMMED): Define.
2013 (DELAY_SLOT): Update.
2015 * m16run.c (sim_engine_run): New file.
2017 * m16.igen: All instructions except LB.
2018 (LB): Call do_load_byte.
2019 * mips.igen (do_load_byte): New function.
2020 (LB): Call do_load_byte.
2022 * mips.igen: Move spec for insn bit size and high bit from here.
2023 * Makefile.in (tmp-igen, tmp-m16): To here.
2025 * m16.dc: New file, decode mips16 instructions.
2027 * Makefile.in (SIM_NO_ALL): Define.
2028 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2030 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2032 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2033 point unit to 32 bit registers.
2034 * configure: Re-generate.
2036 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2038 * configure.in (sim_use_gen): Make IGEN the default simulator
2039 generator for generic 32 and 64 bit mips targets.
2040 * configure: Re-generate.
2042 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2044 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2047 * interp.c (sim_fetch_register, sim_store_register): Read/write
2048 FGR from correct location.
2049 (sim_open): Set size of FGR's according to
2050 WITH_TARGET_FLOATING_POINT_BITSIZE.
2052 * sim-main.h (FGR): Store floating point registers in a separate
2055 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2059 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2061 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2063 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2065 * interp.c (pending_tick): New function. Deliver pending writes.
2067 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2068 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2069 it can handle mixed sized quantites and single bits.
2071 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2073 * interp.c (oengine.h): Do not include when building with IGEN.
2074 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2075 (sim_info): Ditto for PROCESSOR_64BIT.
2076 (sim_monitor): Replace ut_reg with unsigned_word.
2077 (*): Ditto for t_reg.
2078 (LOADDRMASK): Define.
2079 (sim_open): Remove defunct check that host FP is IEEE compliant,
2080 using software to emulate floating point.
2081 (value_fpr, ...): Always compile, was conditional on HASFPU.
2083 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2085 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2088 * interp.c (SD, CPU): Define.
2089 (mips_option_handler): Set flags in each CPU.
2090 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2091 (sim_close): Do not clear STATE, deleted anyway.
2092 (sim_write, sim_read): Assume CPU zero's vm should be used for
2094 (sim_create_inferior): Set the PC for all processors.
2095 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2097 (mips16_entry): Pass correct nr of args to store_word, load_word.
2098 (ColdReset): Cold reset all cpu's.
2099 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2100 (sim_monitor, load_memory, store_memory, signal_exception): Use
2101 `CPU' instead of STATE_CPU.
2104 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2107 * sim-main.h (signal_exception): Add sim_cpu arg.
2108 (SignalException*): Pass both SD and CPU to signal_exception.
2109 * interp.c (signal_exception): Update.
2111 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2113 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2114 address_translation): Ditto
2115 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2117 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2119 * configure: Regenerated to track ../common/aclocal.m4 changes.
2121 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2123 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2125 * mips.igen (model): Map processor names onto BFD name.
2127 * sim-main.h (CPU_CIA): Delete.
2128 (SET_CIA, GET_CIA): Define
2130 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2135 * configure.in (default_endian): Configure a big-endian simulator
2137 * configure: Re-generate.
2139 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2143 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2145 * interp.c (sim_monitor): Handle Densan monitor outbyte
2146 and inbyte functions.
2148 1997-12-29 Felix Lee <flee@cygnus.com>
2150 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2152 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2154 * Makefile.in (tmp-igen): Arrange for $zero to always be
2155 reset to zero after every instruction.
2157 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2159 * configure: Regenerated to track ../common/aclocal.m4 changes.
2162 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2164 * mips.igen (MSUB): Fix to work like MADD.
2165 * gencode.c (MSUB): Similarly.
2167 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2169 * configure: Regenerated to track ../common/aclocal.m4 changes.
2171 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2175 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2177 * sim-main.h (sim-fpu.h): Include.
2179 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2180 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2181 using host independant sim_fpu module.
2183 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * interp.c (signal_exception): Report internal errors with SIGABRT
2188 * sim-main.h (C0_CONFIG): New register.
2189 (signal.h): No longer include.
2191 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2193 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2195 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2197 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199 * mips.igen: Tag vr5000 instructions.
2200 (ANDI): Was missing mipsIV model, fix assembler syntax.
2201 (do_c_cond_fmt): New function.
2202 (C.cond.fmt): Handle mips I-III which do not support CC field
2204 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2205 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2207 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2208 vr5000 which saves LO in a GPR separatly.
2210 * configure.in (enable-sim-igen): For vr5000, select vr5000
2211 specific instructions.
2212 * configure: Re-generate.
2214 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2216 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2218 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2219 fmt_uninterpreted_64 bit cases to switch. Convert to
2222 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2224 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2225 as specified in IV3.2 spec.
2226 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2228 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2230 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2231 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2232 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2233 PENDING_FILL versions of instructions. Simplify.
2235 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2237 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2239 (MTHI, MFHI): Disable code checking HI-LO.
2241 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2243 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2245 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2247 * gencode.c (build_mips16_operands): Replace IPC with cia.
2249 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2250 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2252 (UndefinedResult): Replace function with macro/function
2254 (sim_engine_run): Don't save PC in IPC.
2256 * sim-main.h (IPC): Delete.
2259 * interp.c (signal_exception, store_word, load_word,
2260 address_translation, load_memory, store_memory, cache_op,
2261 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2262 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2263 current instruction address - cia - argument.
2264 (sim_read, sim_write): Call address_translation directly.
2265 (sim_engine_run): Rename variable vaddr to cia.
2266 (signal_exception): Pass cia to sim_monitor
2268 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2269 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2270 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2272 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2273 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2276 * interp.c (signal_exception): Pass restart address to
2279 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2280 idecode.o): Add dependency.
2282 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2284 (DELAY_SLOT): Update NIA not PC with branch address.
2285 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2287 * mips.igen: Use CIA not PC in branch calculations.
2288 (illegal): Call SignalException.
2289 (BEQ, ADDIU): Fix assembler.
2291 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2293 * m16.igen (JALX): Was missing.
2295 * configure.in (enable-sim-igen): New configuration option.
2296 * configure: Re-generate.
2298 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2300 * interp.c (load_memory, store_memory): Delete parameter RAW.
2301 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2302 bypassing {load,store}_memory.
2304 * sim-main.h (ByteSwapMem): Delete definition.
2306 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2308 * interp.c (sim_do_command, sim_commands): Delete mips specific
2309 commands. Handled by module sim-options.
2311 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2312 (WITH_MODULO_MEMORY): Define.
2314 * interp.c (sim_info): Delete code printing memory size.
2316 * interp.c (mips_size): Nee sim_size, delete function.
2318 (monitor, monitor_base, monitor_size): Delete global variables.
2319 (sim_open, sim_close): Delete code creating monitor and other
2320 memory regions. Use sim-memopts module, via sim_do_commandf, to
2321 manage memory regions.
2322 (load_memory, store_memory): Use sim-core for memory model.
2324 * interp.c (address_translation): Delete all memory map code
2325 except line forcing 32 bit addresses.
2327 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2332 * interp.c (logfh, logfile): Delete globals.
2333 (sim_open, sim_close): Delete code opening & closing log file.
2334 (mips_option_handler): Delete -l and -n options.
2335 (OPTION mips_options): Ditto.
2337 * interp.c (OPTION mips_options): Rename option trace to dinero.
2338 (mips_option_handler): Update.
2340 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2342 * interp.c (fetch_str): New function.
2343 (sim_monitor): Rewrite using sim_read & sim_write.
2344 (sim_open): Check magic number.
2345 (sim_open): Write monitor vectors into memory using sim_write.
2346 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2347 (sim_read, sim_write): Simplify - transfer data one byte at a
2349 (load_memory, store_memory): Clarify meaning of parameter RAW.
2351 * sim-main.h (isHOST): Defete definition.
2352 (isTARGET): Mark as depreciated.
2353 (address_translation): Delete parameter HOST.
2355 * interp.c (address_translation): Delete parameter HOST.
2357 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2361 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2362 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2364 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2366 * mips.igen: Add model filter field to records.
2368 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2372 interp.c (sim_engine_run): Do not compile function sim_engine_run
2373 when WITH_IGEN == 1.
2375 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2376 target architecture.
2378 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2379 igen. Replace with configuration variables sim_igen_flags /
2382 * m16.igen: New file. Copy mips16 insns here.
2383 * mips.igen: From here.
2385 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2387 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2389 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2391 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2393 * gencode.c (build_instruction): Follow sim_write's lead in using
2394 BigEndianMem instead of !ByteSwapMem.
2396 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2398 * configure.in (sim_gen): Dependent on target, select type of
2399 generator. Always select old style generator.
2401 configure: Re-generate.
2403 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2405 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2406 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2407 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2408 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2409 SIM_@sim_gen@_*, set by autoconf.
2411 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2413 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2415 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2416 CURRENT_FLOATING_POINT instead.
2418 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2419 (address_translation): Raise exception InstructionFetch when
2420 translation fails and isINSTRUCTION.
2422 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2423 sim_engine_run): Change type of of vaddr and paddr to
2425 (address_translation, prefetch, load_memory, store_memory,
2426 cache_op): Change type of vAddr and pAddr to address_word.
2428 * gencode.c (build_instruction): Change type of vaddr and paddr to
2431 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2433 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2434 macro to obtain result of ALU op.
2436 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438 * interp.c (sim_info): Call profile_print.
2440 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2444 * sim-main.h (WITH_PROFILE): Do not define, defined in
2445 common/sim-config.h. Use sim-profile module.
2446 (simPROFILE): Delete defintion.
2448 * interp.c (PROFILE): Delete definition.
2449 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2450 (sim_close): Delete code writing profile histogram.
2451 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2453 (sim_engine_run): Delete code profiling the PC.
2455 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2457 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2459 * interp.c (sim_monitor): Make register pointers of type
2462 * sim-main.h: Make registers of type unsigned_word not
2465 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2467 * interp.c (sync_operation): Rename from SyncOperation, make
2468 global, add SD argument.
2469 (prefetch): Rename from Prefetch, make global, add SD argument.
2470 (decode_coproc): Make global.
2472 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2474 * gencode.c (build_instruction): Generate DecodeCoproc not
2475 decode_coproc calls.
2477 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2478 (SizeFGR): Move to sim-main.h
2479 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2480 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2481 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2483 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2484 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2485 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2486 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2487 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2488 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2490 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2492 (sim-alu.h): Include.
2493 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2494 (sim_cia): Typedef to instruction_address.
2496 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498 * Makefile.in (interp.o): Rename generated file engine.c to
2503 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2505 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2507 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2509 * gencode.c (build_instruction): For "FPSQRT", output correct
2510 number of arguments to Recip.
2512 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2514 * Makefile.in (interp.o): Depends on sim-main.h
2516 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2518 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2519 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2520 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2521 STATE, DSSTATE): Define
2522 (GPR, FGRIDX, ..): Define.
2524 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2525 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2526 (GPR, FGRIDX, ...): Delete macros.
2528 * interp.c: Update names to match defines from sim-main.h
2530 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2532 * interp.c (sim_monitor): Add SD argument.
2533 (sim_warning): Delete. Replace calls with calls to
2535 (sim_error): Delete. Replace calls with sim_io_error.
2536 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2537 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2538 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2540 (mips_size): Rename from sim_size. Add SD argument.
2542 * interp.c (simulator): Delete global variable.
2543 (callback): Delete global variable.
2544 (mips_option_handler, sim_open, sim_write, sim_read,
2545 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2546 sim_size,sim_monitor): Use sim_io_* not callback->*.
2547 (sim_open): ZALLOC simulator struct.
2548 (PROFILE): Do not define.
2550 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2552 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2553 support.h with corresponding code.
2555 * sim-main.h (word64, uword64), support.h: Move definition to
2557 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2560 * Makefile.in: Update dependencies
2561 * interp.c: Do not include.
2563 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2565 * interp.c (address_translation, load_memory, store_memory,
2566 cache_op): Rename to from AddressTranslation et.al., make global,
2569 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2572 * interp.c (SignalException): Rename to signal_exception, make
2575 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2577 * sim-main.h (SignalException, SignalExceptionInterrupt,
2578 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2579 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2580 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2583 * interp.c, support.h: Use.
2585 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2588 to value_fpr / store_fpr. Add SD argument.
2589 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2590 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2592 * sim-main.h (ValueFPR, StoreFPR): Define.
2594 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596 * interp.c (sim_engine_run): Check consistency between configure
2597 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2600 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2601 (mips_fpu): Configure WITH_FLOATING_POINT.
2602 (mips_endian): Configure WITH_TARGET_ENDIAN.
2603 * configure: Update.
2605 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607 * configure: Regenerated to track ../common/aclocal.m4 changes.
2609 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2611 * configure: Regenerated.
2613 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2615 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2617 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2619 * gencode.c (print_igen_insn_models): Assume certain architectures
2620 include all mips* instructions.
2621 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2624 * Makefile.in (tmp.igen): Add target. Generate igen input from
2627 * gencode.c (FEATURE_IGEN): Define.
2628 (main): Add --igen option. Generate output in igen format.
2629 (process_instructions): Format output according to igen option.
2630 (print_igen_insn_format): New function.
2631 (print_igen_insn_models): New function.
2632 (process_instructions): Only issue warnings and ignore
2633 instructions when no FEATURE_IGEN.
2635 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2637 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2640 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2644 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2646 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2647 SIM_RESERVED_BITS): Delete, moved to common.
2648 (SIM_EXTRA_CFLAGS): Update.
2650 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2652 * configure.in: Configure non-strict memory alignment.
2653 * configure: Regenerated to track ../common/aclocal.m4 changes.
2655 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2657 * configure: Regenerated to track ../common/aclocal.m4 changes.
2659 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2661 * gencode.c (SDBBP,DERET): Added (3900) insns.
2662 (RFE): Turn on for 3900.
2663 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2664 (dsstate): Made global.
2665 (SUBTARGET_R3900): Added.
2666 (CANCELDELAYSLOT): New.
2667 (SignalException): Ignore SystemCall rather than ignore and
2668 terminate. Add DebugBreakPoint handling.
2669 (decode_coproc): New insns RFE, DERET; and new registers Debug
2670 and DEPC protected by SUBTARGET_R3900.
2671 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2673 * Makefile.in,configure.in: Add mips subtarget option.
2674 * configure: Update.
2676 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2678 * gencode.c: Add r3900 (tx39).
2681 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2683 * gencode.c (build_instruction): Don't need to subtract 4 for
2686 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2688 * interp.c: Correct some HASFPU problems.
2690 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2692 * configure: Regenerated to track ../common/aclocal.m4 changes.
2694 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696 * interp.c (mips_options): Fix samples option short form, should
2699 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701 * interp.c (sim_info): Enable info code. Was just returning.
2703 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2705 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2708 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2712 (build_instruction): Ditto for LL.
2714 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2716 * configure: Regenerated to track ../common/aclocal.m4 changes.
2718 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2720 * configure: Regenerated to track ../common/aclocal.m4 changes.
2723 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725 * interp.c (sim_open): Add call to sim_analyze_program, update
2728 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2730 * interp.c (sim_kill): Delete.
2731 (sim_create_inferior): Add ABFD argument. Set PC from same.
2732 (sim_load): Move code initializing trap handlers from here.
2733 (sim_open): To here.
2734 (sim_load): Delete, use sim-hload.c.
2736 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2738 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2740 * configure: Regenerated to track ../common/aclocal.m4 changes.
2743 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745 * interp.c (sim_open): Add ABFD argument.
2746 (sim_load): Move call to sim_config from here.
2747 (sim_open): To here. Check return status.
2749 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2751 * gencode.c (build_instruction): Two arg MADD should
2752 not assign result to $0.
2754 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2756 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2757 * sim/mips/configure.in: Regenerate.
2759 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2761 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2762 signed8, unsigned8 et.al. types.
2764 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2765 hosts when selecting subreg.
2767 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2769 * interp.c (sim_engine_run): Reset the ZERO register to zero
2770 regardless of FEATURE_WARN_ZERO.
2771 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2773 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2776 (SignalException): For BreakPoints ignore any mode bits and just
2778 (SignalException): Always set the CAUSE register.
2780 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2783 exception has been taken.
2785 * interp.c: Implement the ERET and mt/f sr instructions.
2787 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789 * interp.c (SignalException): Don't bother restarting an
2792 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2794 * interp.c (SignalException): Really take an interrupt.
2795 (interrupt_event): Only deliver interrupts when enabled.
2797 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2799 * interp.c (sim_info): Only print info when verbose.
2800 (sim_info) Use sim_io_printf for output.
2802 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2804 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2807 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2809 * interp.c (sim_do_command): Check for common commands if a
2810 simulator specific command fails.
2812 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2814 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2815 and simBE when DEBUG is defined.
2817 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2819 * interp.c (interrupt_event): New function. Pass exception event
2820 onto exception handler.
2822 * configure.in: Check for stdlib.h.
2823 * configure: Regenerate.
2825 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2826 variable declaration.
2827 (build_instruction): Initialize memval1.
2828 (build_instruction): Add UNUSED attribute to byte, bigend,
2830 (build_operands): Ditto.
2832 * interp.c: Fix GCC warnings.
2833 (sim_get_quit_code): Delete.
2835 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2836 * Makefile.in: Ditto.
2837 * configure: Re-generate.
2839 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2841 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2843 * interp.c (mips_option_handler): New function parse argumes using
2845 (myname): Replace with STATE_MY_NAME.
2846 (sim_open): Delete check for host endianness - performed by
2848 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2849 (sim_open): Move much of the initialization from here.
2850 (sim_load): To here. After the image has been loaded and
2852 (sim_open): Move ColdReset from here.
2853 (sim_create_inferior): To here.
2854 (sim_open): Make FP check less dependant on host endianness.
2856 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2858 * interp.c (sim_set_callbacks): Delete.
2860 * interp.c (membank, membank_base, membank_size): Replace with
2861 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2862 (sim_open): Remove call to callback->init. gdb/run do this.
2866 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2868 * interp.c (big_endian_p): Delete, replaced by
2869 current_target_byte_order.
2871 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2873 * interp.c (host_read_long, host_read_word, host_swap_word,
2874 host_swap_long): Delete. Using common sim-endian.
2875 (sim_fetch_register, sim_store_register): Use H2T.
2876 (pipeline_ticks): Delete. Handled by sim-events.
2878 (sim_engine_run): Update.
2880 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2882 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2884 (SignalException): To here. Signal using sim_engine_halt.
2885 (sim_stop_reason): Delete, moved to common.
2887 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2889 * interp.c (sim_open): Add callback argument.
2890 (sim_set_callbacks): Delete SIM_DESC argument.
2893 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2895 * Makefile.in (SIM_OBJS): Add common modules.
2897 * interp.c (sim_set_callbacks): Also set SD callback.
2898 (set_endianness, xfer_*, swap_*): Delete.
2899 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2900 Change to functions using sim-endian macros.
2901 (control_c, sim_stop): Delete, use common version.
2902 (simulate): Convert into.
2903 (sim_engine_run): This function.
2904 (sim_resume): Delete.
2906 * interp.c (simulation): New variable - the simulator object.
2907 (sim_kind): Delete global - merged into simulation.
2908 (sim_load): Cleanup. Move PC assignment from here.
2909 (sim_create_inferior): To here.
2911 * sim-main.h: New file.
2912 * interp.c (sim-main.h): Include.
2914 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2916 * configure: Regenerated to track ../common/aclocal.m4 changes.
2918 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2920 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2922 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2924 * gencode.c (build_instruction): DIV instructions: check
2925 for division by zero and integer overflow before using
2926 host's division operation.
2928 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2930 * Makefile.in (SIM_OBJS): Add sim-load.o.
2931 * interp.c: #include bfd.h.
2932 (target_byte_order): Delete.
2933 (sim_kind, myname, big_endian_p): New static locals.
2934 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2935 after argument parsing. Recognize -E arg, set endianness accordingly.
2936 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2937 load file into simulator. Set PC from bfd.
2938 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2939 (set_endianness): Use big_endian_p instead of target_byte_order.
2941 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2943 * interp.c (sim_size): Delete prototype - conflicts with
2944 definition in remote-sim.h. Correct definition.
2946 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2948 * configure: Regenerated to track ../common/aclocal.m4 changes.
2951 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2953 * interp.c (sim_open): New arg `kind'.
2955 * configure: Regenerated to track ../common/aclocal.m4 changes.
2957 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2959 * configure: Regenerated to track ../common/aclocal.m4 changes.
2961 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2963 * interp.c (sim_open): Set optind to 0 before calling getopt.
2965 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2967 * configure: Regenerated to track ../common/aclocal.m4 changes.
2969 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2971 * interp.c : Replace uses of pr_addr with pr_uword64
2972 where the bit length is always 64 independent of SIM_ADDR.
2973 (pr_uword64) : added.
2975 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2977 * configure: Re-generate.
2979 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2981 * configure: Regenerate to track ../common/aclocal.m4 changes.
2983 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2985 * interp.c (sim_open): New SIM_DESC result. Argument is now
2987 (other sim_*): New SIM_DESC argument.
2989 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2991 * interp.c: Fix printing of addresses for non-64-bit targets.
2992 (pr_addr): Add function to print address based on size.
2994 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2996 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2998 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3000 * gencode.c (build_mips16_operands): Correct computation of base
3001 address for extended PC relative instruction.
3003 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3005 * interp.c (mips16_entry): Add support for floating point cases.
3006 (SignalException): Pass floating point cases to mips16_entry.
3007 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3009 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3011 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3012 and then set the state to fmt_uninterpreted.
3013 (COP_SW): Temporarily set the state to fmt_word while calling
3016 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3018 * gencode.c (build_instruction): The high order may be set in the
3019 comparison flags at any ISA level, not just ISA 4.
3021 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3023 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3024 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3025 * configure.in: sinclude ../common/aclocal.m4.
3026 * configure: Regenerated.
3028 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3030 * configure: Rebuild after change to aclocal.m4.
3032 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3034 * configure configure.in Makefile.in: Update to new configure
3035 scheme which is more compatible with WinGDB builds.
3036 * configure.in: Improve comment on how to run autoconf.
3037 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3038 * Makefile.in: Use autoconf substitution to install common
3041 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3043 * gencode.c (build_instruction): Use BigEndianCPU instead of
3046 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3048 * interp.c (sim_monitor): Make output to stdout visible in
3049 wingdb's I/O log window.
3051 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3053 * support.h: Undo previous change to SIGTRAP
3056 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3058 * interp.c (store_word, load_word): New static functions.
3059 (mips16_entry): New static function.
3060 (SignalException): Look for mips16 entry and exit instructions.
3061 (simulate): Use the correct index when setting fpr_state after
3062 doing a pending move.
3064 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3066 * interp.c: Fix byte-swapping code throughout to work on
3067 both little- and big-endian hosts.
3069 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3071 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3072 with gdb/config/i386/xm-windows.h.
3074 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3076 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3077 that messes up arithmetic shifts.
3079 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3081 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3082 SIGTRAP and SIGQUIT for _WIN32.
3084 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3086 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3087 force a 64 bit multiplication.
3088 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3089 destination register is 0, since that is the default mips16 nop
3092 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3094 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3095 (build_endian_shift): Don't check proc64.
3096 (build_instruction): Always set memval to uword64. Cast op2 to
3097 uword64 when shifting it left in memory instructions. Always use
3098 the same code for stores--don't special case proc64.
3100 * gencode.c (build_mips16_operands): Fix base PC value for PC
3102 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3104 * interp.c (simJALDELAYSLOT): Define.
3105 (JALDELAYSLOT): Define.
3106 (INDELAYSLOT, INJALDELAYSLOT): Define.
3107 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3109 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3111 * interp.c (sim_open): add flush_cache as a PMON routine
3112 (sim_monitor): handle flush_cache by ignoring it
3114 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3116 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3118 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3119 (BigEndianMem): Rename to ByteSwapMem and change sense.
3120 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3121 BigEndianMem references to !ByteSwapMem.
3122 (set_endianness): New function, with prototype.
3123 (sim_open): Call set_endianness.
3124 (sim_info): Use simBE instead of BigEndianMem.
3125 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3126 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3127 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3128 ifdefs, keeping the prototype declaration.
3129 (swap_word): Rewrite correctly.
3130 (ColdReset): Delete references to CONFIG. Delete endianness related
3131 code; moved to set_endianness.
3133 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3135 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3136 * interp.c (CHECKHILO): Define away.
3137 (simSIGINT): New macro.
3138 (membank_size): Increase from 1MB to 2MB.
3139 (control_c): New function.
3140 (sim_resume): Rename parameter signal to signal_number. Add local
3141 variable prev. Call signal before and after simulate.
3142 (sim_stop_reason): Add simSIGINT support.
3143 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3145 (sim_warning): Delete call to SignalException. Do call printf_filtered
3147 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3148 a call to sim_warning.
3150 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3152 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3153 16 bit instructions.
3155 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3157 Add support for mips16 (16 bit MIPS implementation):
3158 * gencode.c (inst_type): Add mips16 instruction encoding types.
3159 (GETDATASIZEINSN): Define.
3160 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3161 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3163 (MIPS16_DECODE): New table, for mips16 instructions.
3164 (bitmap_val): New static function.
3165 (struct mips16_op): Define.
3166 (mips16_op_table): New table, for mips16 operands.
3167 (build_mips16_operands): New static function.
3168 (process_instructions): If PC is odd, decode a mips16
3169 instruction. Break out instruction handling into new
3170 build_instruction function.
3171 (build_instruction): New static function, broken out of
3172 process_instructions. Check modifiers rather than flags for SHIFT
3173 bit count and m[ft]{hi,lo} direction.
3174 (usage): Pass program name to fprintf.
3175 (main): Remove unused variable this_option_optind. Change
3176 ``*loptarg++'' to ``loptarg++''.
3177 (my_strtoul): Parenthesize && within ||.
3178 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3179 (simulate): If PC is odd, fetch a 16 bit instruction, and
3180 increment PC by 2 rather than 4.
3181 * configure.in: Add case for mips16*-*-*.
3182 * configure: Rebuild.
3184 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3186 * interp.c: Allow -t to enable tracing in standalone simulator.
3187 Fix garbage output in trace file and error messages.
3189 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3191 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3192 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3193 * configure.in: Simplify using macros in ../common/aclocal.m4.
3194 * configure: Regenerated.
3195 * tconfig.in: New file.
3197 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3199 * interp.c: Fix bugs in 64-bit port.
3200 Use ansi function declarations for msvc compiler.
3201 Initialize and test file pointer in trace code.
3202 Prevent duplicate definition of LAST_EMED_REGNUM.
3204 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3206 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3208 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3210 * interp.c (SignalException): Check for explicit terminating
3212 * gencode.c: Pass instruction value through SignalException()
3213 calls for Trap, Breakpoint and Syscall.
3215 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3217 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3218 only used on those hosts that provide it.
3219 * configure.in: Add sqrt() to list of functions to be checked for.
3220 * config.in: Re-generated.
3221 * configure: Re-generated.
3223 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3225 * gencode.c (process_instructions): Call build_endian_shift when
3226 expanding STORE RIGHT, to fix swr.
3227 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3228 clear the high bits.
3229 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3230 Fix float to int conversions to produce signed values.
3232 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3234 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3235 (process_instructions): Correct handling of nor instruction.
3236 Correct shift count for 32 bit shift instructions. Correct sign
3237 extension for arithmetic shifts to not shift the number of bits in
3238 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3239 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3241 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3242 It's OK to have a mult follow a mult. What's not OK is to have a
3243 mult follow an mfhi.
3244 (Convert): Comment out incorrect rounding code.
3246 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3248 * interp.c (sim_monitor): Improved monitor printf
3249 simulation. Tidied up simulator warnings, and added "--log" option
3250 for directing warning message output.
3251 * gencode.c: Use sim_warning() rather than WARNING macro.
3253 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3255 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3256 getopt1.o, rather than on gencode.c. Link objects together.
3257 Don't link against -liberty.
3258 (gencode.o, getopt.o, getopt1.o): New targets.
3259 * gencode.c: Include <ctype.h> and "ansidecl.h".
3260 (AND): Undefine after including "ansidecl.h".
3261 (ULONG_MAX): Define if not defined.
3262 (OP_*): Don't define macros; now defined in opcode/mips.h.
3263 (main): Call my_strtoul rather than strtoul.
3264 (my_strtoul): New static function.
3266 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3268 * gencode.c (process_instructions): Generate word64 and uword64
3269 instead of `long long' and `unsigned long long' data types.
3270 * interp.c: #include sysdep.h to get signals, and define default
3272 * (Convert): Work around for Visual-C++ compiler bug with type
3274 * support.h: Make things compile under Visual-C++ by using
3275 __int64 instead of `long long'. Change many refs to long long
3276 into word64/uword64 typedefs.
3278 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3280 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3281 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3283 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3284 (AC_PROG_INSTALL): Added.
3285 (AC_PROG_CC): Moved to before configure.host call.
3286 * configure: Rebuilt.
3288 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3290 * configure.in: Define @SIMCONF@ depending on mips target.
3291 * configure: Rebuild.
3292 * Makefile.in (run): Add @SIMCONF@ to control simulator
3294 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3295 * interp.c: Remove some debugging, provide more detailed error
3296 messages, update memory accesses to use LOADDRMASK.
3298 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3300 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3301 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3303 * configure: Rebuild.
3304 * config.in: New file, generated by autoheader.
3305 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3306 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3307 HAVE_ANINT and HAVE_AINT, as appropriate.
3308 * Makefile.in (run): Use @LIBS@ rather than -lm.
3309 (interp.o): Depend upon config.h.
3310 (Makefile): Just rebuild Makefile.
3311 (clean): Remove stamp-h.
3312 (mostlyclean): Make the same as clean, not as distclean.
3313 (config.h, stamp-h): New targets.
3315 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3317 * interp.c (ColdReset): Fix boolean test. Make all simulator
3320 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3322 * interp.c (xfer_direct_word, xfer_direct_long,
3323 swap_direct_word, swap_direct_long, xfer_big_word,
3324 xfer_big_long, xfer_little_word, xfer_little_long,
3325 swap_word,swap_long): Added.
3326 * interp.c (ColdReset): Provide function indirection to
3327 host<->simulated_target transfer routines.
3328 * interp.c (sim_store_register, sim_fetch_register): Updated to
3329 make use of indirected transfer routines.
3331 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3333 * gencode.c (process_instructions): Ensure FP ABS instruction
3335 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3336 system call support.
3338 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3340 * interp.c (sim_do_command): Complain if callback structure not
3343 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3345 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3346 support for Sun hosts.
3347 * Makefile.in (gencode): Ensure the host compiler and libraries
3348 used for cross-hosted build.
3350 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3352 * interp.c, gencode.c: Some more (TODO) tidying.
3354 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3356 * gencode.c, interp.c: Replaced explicit long long references with
3357 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3358 * support.h (SET64LO, SET64HI): Macros added.
3360 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3362 * configure: Regenerate with autoconf 2.7.
3364 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3366 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3367 * support.h: Remove superfluous "1" from #if.
3368 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3370 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3372 * interp.c (StoreFPR): Control UndefinedResult() call on
3373 WARN_RESULT manifest.
3375 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3377 * gencode.c: Tidied instruction decoding, and added FP instruction
3380 * interp.c: Added dineroIII, and BSD profiling support. Also
3381 run-time FP handling.
3383 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3385 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3386 gencode.c, interp.c, support.h: created.