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[thirdparty/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 NOTEs:
17
18 The IDT monitor (found on the VR4300 board), seems to lie about
19 register contents. It seems to treat the registers as sign-extended
20 32-bit values. This cause *REAL* problems when single-stepping 64-bit
21 code on the hardware.
22
23 */
24
25 #include "config.h"
26 #include "bfd.h"
27 #include "sim-main.h"
28 #include "sim-utils.h"
29 #include "sim-options.h"
30 #include "sim-assert.h"
31 #include "sim-hw.h"
32
33 #include "itable.h"
34
35
36 #include "config.h"
37
38 #include <stdio.h>
39 #include <stdarg.h>
40 #include <ansidecl.h>
41 #include <ctype.h>
42 #include <limits.h>
43 #include <math.h>
44 #include <stdlib.h>
45 #include <string.h>
46
47 #include "getopt.h"
48 #include "libiberty.h"
49 #include "bfd.h"
50 #include "elf-bfd.h"
51 #include "sim/callback.h" /* GDB simulator callback interface */
52 #include "sim/sim.h" /* GDB simulator interface */
53 #include "sim-syscall.h" /* Simulator system call support */
54
55 char* pr_addr (SIM_ADDR addr);
56 char* pr_uword64 (uword64 addr);
57
58
59 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
60 #define CPU cpu
61 #define SD sd
62
63
64 /* The following reserved instruction value is used when a simulator
65 trap is required. NOTE: Care must be taken, since this value may be
66 used in later revisions of the MIPS ISA. */
67
68 #define RSVD_INSTRUCTION (0x00000039)
69 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
70
71 #define RSVD_INSTRUCTION_ARG_SHIFT 6
72 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
73
74
75 /* Bits in the Debug register */
76 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
77 #define Debug_DM 0x40000000 /* Debug Mode */
78 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
79
80 /*---------------------------------------------------------------------------*/
81 /*-- GDB simulator interface ------------------------------------------------*/
82 /*---------------------------------------------------------------------------*/
83
84 static void ColdReset (SIM_DESC sd);
85
86 /*---------------------------------------------------------------------------*/
87
88
89
90 #define DELAYSLOT() {\
91 if (STATE & simDELAYSLOT)\
92 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
93 STATE |= simDELAYSLOT;\
94 }
95
96 #define JALDELAYSLOT() {\
97 DELAYSLOT ();\
98 STATE |= simJALDELAYSLOT;\
99 }
100
101 #define NULLIFY() {\
102 STATE &= ~simDELAYSLOT;\
103 STATE |= simSKIPNEXT;\
104 }
105
106 #define CANCELDELAYSLOT() {\
107 DSSTATE = 0;\
108 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
109 }
110
111 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
112 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
113
114 /* Note that the monitor code essentially assumes this layout of memory.
115 If you change these, change the monitor code, too. */
116 /* FIXME Currently addresses are truncated to 32-bits, see
117 mips/sim-main.c:address_translation(). If that changes, then these
118 values will need to be extended, and tested for more carefully. */
119 #define K0BASE (0x80000000)
120 #define K0SIZE (0x20000000)
121 #define K1BASE (0xA0000000)
122 #define K1SIZE (0x20000000)
123
124 /* Simple run-time monitor support.
125
126 We emulate the monitor by placing magic reserved instructions at
127 the monitor's entry points; when we hit these instructions, instead
128 of raising an exception (as we would normally), we look at the
129 instruction and perform the appropriate monitory operation.
130
131 `*_monitor_base' are the physical addresses at which the corresponding
132 monitor vectors are located. `0' means none. By default,
133 install all three.
134 The RSVD_INSTRUCTION... macros specify the magic instructions we
135 use at the monitor entry points. */
136 static int firmware_option_p = 0;
137 static SIM_ADDR idt_monitor_base = 0xBFC00000;
138 static SIM_ADDR pmon_monitor_base = 0xBFC00500;
139 static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
140
141 static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
142
143 #define MEM_SIZE (8 << 20) /* 8 MBytes */
144
145
146 #if WITH_TRACE_ANY_P
147 static char *tracefile = "trace.din"; /* default filename for trace log */
148 FILE *tracefh = NULL;
149 static void open_trace (SIM_DESC sd);
150 #else
151 #define open_trace(sd)
152 #endif
153
154 static const char * get_insn_name (sim_cpu *, int);
155
156 /* simulation target board. NULL=canonical */
157 static char* board = NULL;
158
159
160 static DECLARE_OPTION_HANDLER (mips_option_handler);
161
162 enum {
163 OPTION_DINERO_TRACE = OPTION_START,
164 OPTION_DINERO_FILE,
165 OPTION_FIRMWARE,
166 OPTION_INFO_MEMORY,
167 OPTION_BOARD
168 };
169
170 static int display_mem_info = 0;
171
172 static SIM_RC
173 mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
174 int is_command)
175 {
176 int cpu_nr;
177 switch (opt)
178 {
179 case OPTION_DINERO_TRACE: /* ??? */
180 #if WITH_TRACE_ANY_P
181 /* Eventually the simTRACE flag could be treated as a toggle, to
182 allow external control of the program points being traced
183 (i.e. only from main onwards, excluding the run-time setup,
184 etc.). */
185 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
186 {
187 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
188 if (arg == NULL)
189 STATE |= simTRACE;
190 else if (strcmp (arg, "yes") == 0)
191 STATE |= simTRACE;
192 else if (strcmp (arg, "no") == 0)
193 STATE &= ~simTRACE;
194 else if (strcmp (arg, "on") == 0)
195 STATE |= simTRACE;
196 else if (strcmp (arg, "off") == 0)
197 STATE &= ~simTRACE;
198 else
199 {
200 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
201 return SIM_RC_FAIL;
202 }
203 }
204 return SIM_RC_OK;
205 #else /* !WITH_TRACE_ANY_P */
206 fprintf(stderr,"\
207 Simulator constructed without dinero tracing support (for performance).\n\
208 Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
209 return SIM_RC_FAIL;
210 #endif /* !WITH_TRACE_ANY_P */
211
212 case OPTION_DINERO_FILE:
213 #if WITH_TRACE_ANY_P
214 if (optarg != NULL) {
215 char *tmp;
216 tmp = (char *)malloc(strlen(optarg) + 1);
217 if (tmp == NULL)
218 {
219 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
220 return SIM_RC_FAIL;
221 }
222 else {
223 strcpy(tmp,optarg);
224 tracefile = tmp;
225 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
226 }
227 }
228 #endif /* WITH_TRACE_ANY_P */
229 return SIM_RC_OK;
230
231 case OPTION_FIRMWARE:
232 return sim_firmware_command (sd, arg);
233
234 case OPTION_BOARD:
235 {
236 if (arg)
237 {
238 board = zalloc(strlen(arg) + 1);
239 strcpy(board, arg);
240 }
241 return SIM_RC_OK;
242 }
243
244 case OPTION_INFO_MEMORY:
245 display_mem_info = 1;
246 break;
247 }
248
249 return SIM_RC_OK;
250 }
251
252
253 static const OPTION mips_options[] =
254 {
255 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
256 '\0', "on|off", "Enable dinero tracing",
257 mips_option_handler },
258 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
259 '\0', "FILE", "Write dinero trace to FILE",
260 mips_option_handler },
261 { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
262 '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
263 mips_option_handler },
264 { {"board", required_argument, NULL, OPTION_BOARD},
265 '\0', "none" /* rely on compile-time string concatenation for other options */
266
267 #define BOARD_JMR3904 "jmr3904"
268 "|" BOARD_JMR3904
269 #define BOARD_JMR3904_PAL "jmr3904pal"
270 "|" BOARD_JMR3904_PAL
271 #define BOARD_JMR3904_DEBUG "jmr3904debug"
272 "|" BOARD_JMR3904_DEBUG
273 #define BOARD_BSP "bsp"
274 "|" BOARD_BSP
275
276 , "Customize simulation for a particular board.", mips_option_handler },
277
278 /* These next two options have the same names as ones found in the
279 memory_options[] array in common/sim-memopt.c. This is because
280 the intention is to provide an alternative handler for those two
281 options. We need an alternative handler because the memory
282 regions are not set up until after the command line arguments
283 have been parsed, and so we cannot display the memory info whilst
284 processing the command line. There is a hack in sim_open to
285 remove these handlers when we want the real --memory-info option
286 to work. */
287 { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
288 '\0', NULL, "List configured memory regions", mips_option_handler },
289 { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
290 '\0', NULL, NULL, mips_option_handler },
291
292 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
293 };
294
295
296 int interrupt_pending;
297
298 void
299 interrupt_event (SIM_DESC sd, void *data)
300 {
301 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
302 address_word cia = CPU_PC_GET (cpu);
303 if (SR & status_IE)
304 {
305 interrupt_pending = 0;
306 SignalExceptionInterrupt (1); /* interrupt "1" */
307 }
308 else if (!interrupt_pending)
309 sim_events_schedule (sd, 1, interrupt_event, data);
310 }
311
312
313 /*---------------------------------------------------------------------------*/
314 /*-- Device registration hook -----------------------------------------------*/
315 /*---------------------------------------------------------------------------*/
316 static void device_init(SIM_DESC sd) {
317 #ifdef DEVICE_INIT
318 extern void register_devices(SIM_DESC);
319 register_devices(sd);
320 #endif
321 }
322
323 /*---------------------------------------------------------------------------*/
324 /*-- GDB simulator interface ------------------------------------------------*/
325 /*---------------------------------------------------------------------------*/
326
327 static sim_cia
328 mips_pc_get (sim_cpu *cpu)
329 {
330 return PC;
331 }
332
333 static void
334 mips_pc_set (sim_cpu *cpu, sim_cia pc)
335 {
336 PC = pc;
337 }
338
339 static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
340 static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
341
342 SIM_DESC
343 sim_open (SIM_OPEN_KIND kind, host_callback *cb,
344 struct bfd *abfd, char * const *argv)
345 {
346 int i;
347 SIM_DESC sd = sim_state_alloc (kind, cb);
348 sim_cpu *cpu;
349
350 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
351
352 /* The cpu data is kept in a separately allocated chunk of memory. */
353 if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK)
354 return 0;
355
356 cpu = STATE_CPU (sd, 0); /* FIXME */
357
358 /* FIXME: watchpoints code shouldn't need this */
359 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
360
361 /* Initialize the mechanism for doing insn profiling. */
362 CPU_INSN_NAME (cpu) = get_insn_name;
363 CPU_MAX_INSNS (cpu) = nr_itable_entries;
364
365 STATE = 0;
366
367 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
368 return 0;
369 sim_add_option_table (sd, NULL, mips_options);
370
371
372 /* The parser will print an error message for us, so we silently return. */
373 if (sim_parse_args (sd, argv) != SIM_RC_OK)
374 {
375 /* Uninstall the modules to avoid memory leaks,
376 file descriptor leaks, etc. */
377 sim_module_uninstall (sd);
378 return 0;
379 }
380
381 /* handle board-specific memory maps */
382 if (board == NULL)
383 {
384 /* Allocate core managed memory */
385 sim_memopt *entry, *match = NULL;
386 address_word mem_size = 0;
387 int mapped = 0;
388
389 /* For compatibility with the old code - under this (at level one)
390 are the kernel spaces K0 & K1. Both of these map to a single
391 smaller sub region */
392 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
393
394 /* Look for largest memory region defined on command-line at
395 phys address 0. */
396 for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
397 {
398 /* If we find an entry at address 0, then we will end up
399 allocating a new buffer in the "memory alias" command
400 below. The region at address 0 will be deleted. */
401 address_word size = (entry->modulo != 0
402 ? entry->modulo : entry->nr_bytes);
403 if (entry->addr == 0
404 && (!match || entry->level < match->level))
405 match = entry;
406 else if (entry->addr == K0BASE || entry->addr == K1BASE)
407 mapped = 1;
408 else
409 {
410 sim_memopt *alias;
411 for (alias = entry->alias; alias != NULL; alias = alias->next)
412 {
413 if (alias->addr == 0
414 && (!match || entry->level < match->level))
415 match = entry;
416 else if (alias->addr == K0BASE || alias->addr == K1BASE)
417 mapped = 1;
418 }
419 }
420 }
421
422 if (!mapped)
423 {
424 if (match)
425 {
426 /* Get existing memory region size. */
427 mem_size = (match->modulo != 0
428 ? match->modulo : match->nr_bytes);
429 /* Delete old region. */
430 sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
431 match->space, match->addr, match->level);
432 }
433 else if (mem_size == 0)
434 mem_size = MEM_SIZE;
435 /* Limit to KSEG1 size (512MB) */
436 if (mem_size > K1SIZE)
437 mem_size = K1SIZE;
438 /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
439 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
440 K1BASE, K1SIZE, (long)mem_size, K0BASE);
441 }
442
443 device_init(sd);
444 }
445 else if (board != NULL
446 && (strcmp(board, BOARD_BSP) == 0))
447 {
448 int i;
449
450 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
451
452 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
453 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
454 0x9FC00000,
455 4 * 1024 * 1024, /* 4 MB */
456 0xBFC00000);
457
458 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
459 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
460 0x80000000,
461 4 * 1024 * 1024, /* 4 MB */
462 0xA0000000);
463
464 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
465 for (i=0; i<8; i++) /* 32 MB total */
466 {
467 unsigned size = 4 * 1024 * 1024; /* 4 MB */
468 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
469 0x88000000 + (i * size),
470 size,
471 0xA8000000 + (i * size));
472 }
473 }
474 #if (WITH_HW)
475 else if (board != NULL
476 && (strcmp(board, BOARD_JMR3904) == 0 ||
477 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
478 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
479 {
480 /* match VIRTUAL memory layout of JMR-TX3904 board */
481 int i;
482
483 /* --- disable monitor unless forced on by user --- */
484
485 if (! firmware_option_p)
486 {
487 idt_monitor_base = 0;
488 pmon_monitor_base = 0;
489 lsipmon_monitor_base = 0;
490 }
491
492 /* --- environment --- */
493
494 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
495
496 /* --- memory --- */
497
498 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
499 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
500 0x9FC00000,
501 4 * 1024 * 1024, /* 4 MB */
502 0xBFC00000);
503
504 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
505 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
506 0x80000000,
507 4 * 1024 * 1024, /* 4 MB */
508 0xA0000000);
509
510 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
511 for (i=0; i<8; i++) /* 32 MB total */
512 {
513 unsigned size = 4 * 1024 * 1024; /* 4 MB */
514 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
515 0x88000000 + (i * size),
516 size,
517 0xA8000000 + (i * size));
518 }
519
520 /* Dummy memory regions for unsimulated devices - sorted by address */
521
522 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
523 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
524 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
525 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
526 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
527 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
528 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
529 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
530 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
531
532
533 /* --- simulated devices --- */
534 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
535 sim_hw_parse (sd, "/tx3904cpu");
536 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
537 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
538 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
539 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
540 {
541 /* FIXME: poking at dv-sockser internals, use tcp backend if
542 --sockser_addr option was given.*/
543 extern char* sockser_addr;
544 if(sockser_addr == NULL)
545 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
546 else
547 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
548 }
549 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
550 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
551
552 /* -- device connections --- */
553 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
554 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
555 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
556 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
557 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
558 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
559
560 /* add PAL timer & I/O module */
561 if(! strcmp(board, BOARD_JMR3904_PAL))
562 {
563 /* the device */
564 sim_hw_parse (sd, "/pal@0xffff0000");
565 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
566
567 /* wire up interrupt ports to irc */
568 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
569 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
570 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
571 }
572
573 if(! strcmp(board, BOARD_JMR3904_DEBUG))
574 {
575 /* -- DEBUG: glue interrupt generators --- */
576 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
577 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
578 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
579 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
580 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
581 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
582 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
583 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
584 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
585 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
586 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
587 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
588 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
589 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
590 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
591 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
592 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
593 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
594 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
595 }
596
597 device_init(sd);
598 }
599 #endif
600
601 if (display_mem_info)
602 {
603 struct option_list * ol;
604 struct option_list * prev;
605
606 /* This is a hack. We want to execute the real --memory-info command
607 line switch which is handled in common/sim-memopts.c, not the
608 override we have defined in this file. So we remove the
609 mips_options array from the state options list. This is safe
610 because we have now processed all of the command line. */
611 for (ol = STATE_OPTIONS (sd), prev = NULL;
612 ol != NULL;
613 prev = ol, ol = ol->next)
614 if (ol->options == mips_options)
615 break;
616
617 SIM_ASSERT (ol != NULL);
618
619 if (prev == NULL)
620 STATE_OPTIONS (sd) = ol->next;
621 else
622 prev->next = ol->next;
623
624 sim_do_commandf (sd, "memory-info");
625 }
626
627 /* check for/establish the a reference program image */
628 if (sim_analyze_program (sd,
629 (STATE_PROG_ARGV (sd) != NULL
630 ? *STATE_PROG_ARGV (sd)
631 : NULL),
632 abfd) != SIM_RC_OK)
633 {
634 sim_module_uninstall (sd);
635 return 0;
636 }
637
638 /* Configure/verify the target byte order and other runtime
639 configuration options */
640 if (sim_config (sd) != SIM_RC_OK)
641 {
642 sim_module_uninstall (sd);
643 return 0;
644 }
645
646 if (sim_post_argv_init (sd) != SIM_RC_OK)
647 {
648 /* Uninstall the modules to avoid memory leaks,
649 file descriptor leaks, etc. */
650 sim_module_uninstall (sd);
651 return 0;
652 }
653
654 /* verify assumptions the simulator made about the host type system.
655 This macro does not return if there is a problem */
656 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
657 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
658
659 /* This is NASTY, in that we are assuming the size of specific
660 registers: */
661 {
662 int rn;
663 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
664 {
665 if (rn < 32)
666 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
667 else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
668 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
669 else if ((rn >= 33) && (rn <= 37))
670 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
671 else if ((rn == SRIDX)
672 || (rn == FCR0IDX)
673 || (rn == FCR31IDX)
674 || ((rn >= 72) && (rn <= 89)))
675 cpu->register_widths[rn] = 32;
676 else
677 cpu->register_widths[rn] = 0;
678 }
679
680
681 }
682
683 if (STATE & simTRACE)
684 open_trace(sd);
685
686 /*
687 sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
688 idt_monitor_base,
689 pmon_monitor_base,
690 lsipmon_monitor_base);
691 */
692
693 /* Write the monitor trap address handlers into the monitor (eeprom)
694 address space. This can only be done once the target endianness
695 has been determined. */
696 if (idt_monitor_base != 0)
697 {
698 unsigned loop;
699 unsigned idt_monitor_size = 1 << 11;
700
701 /* the default monitor region */
702 sim_do_commandf (sd, "memory region 0x%x,0x%x",
703 idt_monitor_base, idt_monitor_size);
704
705 /* Entry into the IDT monitor is via fixed address vectors, and
706 not using machine instructions. To avoid clashing with use of
707 the MIPS TRAP system, we place our own (simulator specific)
708 "undefined" instructions into the relevant vector slots. */
709 for (loop = 0; (loop < idt_monitor_size); loop += 4)
710 {
711 address_word vaddr = (idt_monitor_base + loop);
712 unsigned32 insn = (RSVD_INSTRUCTION |
713 (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
714 << RSVD_INSTRUCTION_ARG_SHIFT));
715 H2T (insn);
716 sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
717 }
718 }
719
720 if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
721 {
722 /* The PMON monitor uses the same address space, but rather than
723 branching into it the address of a routine is loaded. We can
724 cheat for the moment, and direct the PMON routine to IDT style
725 instructions within the monitor space. This relies on the IDT
726 monitor not using the locations from 0xBFC00500 onwards as its
727 entry points.*/
728 unsigned loop;
729 for (loop = 0; (loop < 24); loop++)
730 {
731 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
732 switch (loop)
733 {
734 case 0: /* read */
735 value = 7;
736 break;
737 case 1: /* write */
738 value = 8;
739 break;
740 case 2: /* open */
741 value = 6;
742 break;
743 case 3: /* close */
744 value = 10;
745 break;
746 case 5: /* printf */
747 value = ((0x500 - 16) / 8); /* not an IDT reason code */
748 break;
749 case 8: /* cliexit */
750 value = 17;
751 break;
752 case 11: /* flush_cache */
753 value = 28;
754 break;
755 }
756
757 SIM_ASSERT (idt_monitor_base != 0);
758 value = ((unsigned int) idt_monitor_base + (value * 8));
759 H2T (value);
760
761 if (pmon_monitor_base != 0)
762 {
763 address_word vaddr = (pmon_monitor_base + (loop * 4));
764 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
765 }
766
767 if (lsipmon_monitor_base != 0)
768 {
769 address_word vaddr = (lsipmon_monitor_base + (loop * 4));
770 sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
771 }
772 }
773
774 /* Write an abort sequence into the TRAP (common) exception vector
775 addresses. This is to catch code executing a TRAP (et.al.)
776 instruction without installing a trap handler. */
777 if ((idt_monitor_base != 0) ||
778 (pmon_monitor_base != 0) ||
779 (lsipmon_monitor_base != 0))
780 {
781 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
782 HALT_INSTRUCTION /* BREAK */ };
783 H2T (halt[0]);
784 H2T (halt[1]);
785 sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
786 sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
787 sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
788 /* XXX: Write here unconditionally? */
789 sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
790 sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
791 sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
792 }
793 }
794
795 /* CPU specific initialization. */
796 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
797 {
798 SIM_CPU *cpu = STATE_CPU (sd, i);
799
800 CPU_REG_FETCH (cpu) = mips_reg_fetch;
801 CPU_REG_STORE (cpu) = mips_reg_store;
802 CPU_PC_FETCH (cpu) = mips_pc_get;
803 CPU_PC_STORE (cpu) = mips_pc_set;
804 }
805
806 return sd;
807 }
808
809 #if WITH_TRACE_ANY_P
810 static void
811 open_trace (SIM_DESC sd)
812 {
813 tracefh = fopen(tracefile,"wb+");
814 if (tracefh == NULL)
815 {
816 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
817 tracefh = stderr;
818 }
819 }
820 #endif
821
822 /* Return name of an insn, used by insn profiling. */
823 static const char *
824 get_insn_name (sim_cpu *cpu, int i)
825 {
826 return itable[i].name;
827 }
828
829 void
830 mips_sim_close (SIM_DESC sd, int quitting)
831 {
832 #if WITH_TRACE_ANY_P
833 if (tracefh != NULL && tracefh != stderr)
834 fclose(tracefh);
835 tracefh = NULL;
836 #endif
837 }
838
839 static int
840 mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
841 {
842 /* NOTE: gdb (the client) stores registers in target byte order
843 while the simulator uses host byte order */
844
845 /* Unfortunately this suffers from the same problem as the register
846 numbering one. We need to know what the width of each logical
847 register number is for the architecture being simulated. */
848
849 if (cpu->register_widths[rn] == 0)
850 {
851 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
852 return 0;
853 }
854
855 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
856 {
857 cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
858 if (cpu->register_widths[rn] == 32)
859 {
860 if (length == 8)
861 {
862 cpu->fgr[rn - FGR_BASE] =
863 (unsigned32) T2H_8 (*(unsigned64*)memory);
864 return 8;
865 }
866 else
867 {
868 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
869 return 4;
870 }
871 }
872 else
873 {
874 if (length == 8)
875 {
876 cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
877 return 8;
878 }
879 else
880 {
881 cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
882 return 4;
883 }
884 }
885 }
886
887 if (cpu->register_widths[rn] == 32)
888 {
889 if (length == 8)
890 {
891 cpu->registers[rn] =
892 (unsigned32) T2H_8 (*(unsigned64*)memory);
893 return 8;
894 }
895 else
896 {
897 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
898 return 4;
899 }
900 }
901 else
902 {
903 if (length == 8)
904 {
905 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
906 return 8;
907 }
908 else
909 {
910 cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
911 return 4;
912 }
913 }
914
915 return 0;
916 }
917
918 static int
919 mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
920 {
921 /* NOTE: gdb (the client) stores registers in target byte order
922 while the simulator uses host byte order */
923
924 if (cpu->register_widths[rn] == 0)
925 {
926 sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
927 return 0;
928 }
929
930 /* Any floating point register */
931 if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
932 {
933 if (cpu->register_widths[rn] == 32)
934 {
935 if (length == 8)
936 {
937 *(unsigned64*)memory =
938 H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
939 return 8;
940 }
941 else
942 {
943 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
944 return 4;
945 }
946 }
947 else
948 {
949 if (length == 8)
950 {
951 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
952 return 8;
953 }
954 else
955 {
956 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
957 return 4;
958 }
959 }
960 }
961
962 if (cpu->register_widths[rn] == 32)
963 {
964 if (length == 8)
965 {
966 *(unsigned64*)memory =
967 H2T_8 ((unsigned32) (cpu->registers[rn]));
968 return 8;
969 }
970 else
971 {
972 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
973 return 4;
974 }
975 }
976 else
977 {
978 if (length == 8)
979 {
980 *(unsigned64*)memory =
981 H2T_8 ((unsigned64) (cpu->registers[rn]));
982 return 8;
983 }
984 else
985 {
986 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
987 return 4;
988 }
989 }
990
991 return 0;
992 }
993
994 SIM_RC
995 sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
996 char * const *argv, char * const *env)
997 {
998
999 #ifdef DEBUG
1000 #if 0 /* FIXME: doesn't compile */
1001 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1002 pr_addr(PC));
1003 #endif
1004 #endif /* DEBUG */
1005
1006 ColdReset(sd);
1007
1008 if (abfd != NULL)
1009 {
1010 /* override PC value set by ColdReset () */
1011 int cpu_nr;
1012 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1013 {
1014 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1015 sim_cia pc = bfd_get_start_address (abfd);
1016
1017 /* We need to undo brain-dead bfd behavior where it sign-extends
1018 addresses that are supposed to be unsigned. See the mips bfd
1019 sign_extend_vma setting. We have to check the ELF data itself
1020 in order to handle o32 & n32 ABIs. */
1021 if (abfd->tdata.elf_obj_data->elf_header->e_ident[EI_CLASS] ==
1022 ELFCLASS32)
1023 pc = (unsigned32) pc;
1024
1025 CPU_PC_SET (cpu, pc);
1026 }
1027 }
1028
1029 #if 0 /* def DEBUG */
1030 if (argv || env)
1031 {
1032 /* We should really place the argv slot values into the argument
1033 registers, and onto the stack as required. However, this
1034 assumes that we have a stack defined, which is not
1035 necessarily true at the moment. */
1036 char **cptr;
1037 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1038 for (cptr = argv; (cptr && *cptr); cptr++)
1039 printf("DBG: arg \"%s\"\n",*cptr);
1040 }
1041 #endif /* DEBUG */
1042
1043 return SIM_RC_OK;
1044 }
1045
1046 /*---------------------------------------------------------------------------*/
1047 /*-- Private simulator support interface ------------------------------------*/
1048 /*---------------------------------------------------------------------------*/
1049
1050 /* Read a null terminated string from memory, return in a buffer */
1051 static char *
1052 fetch_str (SIM_DESC sd,
1053 address_word addr)
1054 {
1055 char *buf;
1056 int nr = 0;
1057 unsigned char null;
1058 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1059 nr++;
1060 buf = NZALLOC (char, nr + 1);
1061 sim_read (sd, addr, (unsigned char *)buf, nr);
1062 return buf;
1063 }
1064
1065
1066 /* Implements the "sim firmware" command:
1067 sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
1068 NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
1069 defaults to the normal address for that monitor.
1070 sim firmware none --- don't emulate any ROM monitor. Useful
1071 if you need a clean address space. */
1072 static SIM_RC
1073 sim_firmware_command (SIM_DESC sd, char *arg)
1074 {
1075 int address_present = 0;
1076 SIM_ADDR address;
1077
1078 /* Signal occurrence of this option. */
1079 firmware_option_p = 1;
1080
1081 /* Parse out the address, if present. */
1082 {
1083 char *p = strchr (arg, '@');
1084 if (p)
1085 {
1086 char *q;
1087 address_present = 1;
1088 p ++; /* skip over @ */
1089
1090 address = strtoul (p, &q, 0);
1091 if (*q != '\0')
1092 {
1093 sim_io_printf (sd, "Invalid address given to the"
1094 "`sim firmware NAME@ADDRESS' command: %s\n",
1095 p);
1096 return SIM_RC_FAIL;
1097 }
1098 }
1099 else
1100 {
1101 address_present = 0;
1102 address = -1; /* Dummy value. */
1103 }
1104 }
1105
1106 if (! strncmp (arg, "idt", 3))
1107 {
1108 idt_monitor_base = address_present ? address : 0xBFC00000;
1109 pmon_monitor_base = 0;
1110 lsipmon_monitor_base = 0;
1111 }
1112 else if (! strncmp (arg, "pmon", 4))
1113 {
1114 /* pmon uses indirect calls. Hook into implied idt. */
1115 pmon_monitor_base = address_present ? address : 0xBFC00500;
1116 idt_monitor_base = pmon_monitor_base - 0x500;
1117 lsipmon_monitor_base = 0;
1118 }
1119 else if (! strncmp (arg, "lsipmon", 7))
1120 {
1121 /* lsipmon uses indirect calls. Hook into implied idt. */
1122 pmon_monitor_base = 0;
1123 lsipmon_monitor_base = address_present ? address : 0xBFC00200;
1124 idt_monitor_base = lsipmon_monitor_base - 0x200;
1125 }
1126 else if (! strncmp (arg, "none", 4))
1127 {
1128 if (address_present)
1129 {
1130 sim_io_printf (sd,
1131 "The `sim firmware none' command does "
1132 "not take an `ADDRESS' argument.\n");
1133 return SIM_RC_FAIL;
1134 }
1135 idt_monitor_base = 0;
1136 pmon_monitor_base = 0;
1137 lsipmon_monitor_base = 0;
1138 }
1139 else
1140 {
1141 sim_io_printf (sd, "\
1142 Unrecognized name given to the `sim firmware NAME' command: %s\n\
1143 Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
1144 arg);
1145 return SIM_RC_FAIL;
1146 }
1147
1148 return SIM_RC_OK;
1149 }
1150
1151 /* stat structures from MIPS32/64. */
1152 static const char stat32_map[] =
1153 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1154 ":st_rdev,2:st_size,4:st_atime,4:st_spare1,4:st_mtime,4:st_spare2,4"
1155 ":st_ctime,4:st_spare3,4:st_blksize,4:st_blocks,4:st_spare4,8";
1156
1157 static const char stat64_map[] =
1158 "st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
1159 ":st_rdev,2:st_size,8:st_atime,8:st_spare1,8:st_mtime,8:st_spare2,8"
1160 ":st_ctime,8:st_spare3,8:st_blksize,8:st_blocks,8:st_spare4,16";
1161
1162 /* Map for calls using the host struct stat. */
1163 static const CB_TARGET_DEFS_MAP CB_stat_map[] =
1164 {
1165 { "stat", CB_SYS_stat, 15 },
1166 { 0, -1, -1 }
1167 };
1168
1169
1170 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1171 int
1172 sim_monitor (SIM_DESC sd,
1173 sim_cpu *cpu,
1174 address_word cia,
1175 unsigned int reason)
1176 {
1177 #ifdef DEBUG
1178 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1179 #endif /* DEBUG */
1180
1181 /* The IDT monitor actually allows two instructions per vector
1182 slot. However, the simulator currently causes a trap on each
1183 individual instruction. We cheat, and lose the bottom bit. */
1184 reason >>= 1;
1185
1186 /* The following callback functions are available, however the
1187 monitor we are simulating does not make use of them: get_errno,
1188 isatty, rename, system and time. */
1189 switch (reason)
1190 {
1191
1192 case 6: /* int open(char *path,int flags) */
1193 {
1194 char *path = fetch_str (sd, A0);
1195 V0 = sim_io_open (sd, path, (int)A1);
1196 free (path);
1197 break;
1198 }
1199
1200 case 7: /* int read(int file,char *ptr,int len) */
1201 {
1202 int fd = A0;
1203 int nr = A2;
1204 char *buf = zalloc (nr);
1205 V0 = sim_io_read (sd, fd, buf, nr);
1206 sim_write (sd, A1, (unsigned char *)buf, nr);
1207 free (buf);
1208 }
1209 break;
1210
1211 case 8: /* int write(int file,char *ptr,int len) */
1212 {
1213 int fd = A0;
1214 int nr = A2;
1215 char *buf = zalloc (nr);
1216 sim_read (sd, A1, (unsigned char *)buf, nr);
1217 V0 = sim_io_write (sd, fd, buf, nr);
1218 if (fd == 1)
1219 sim_io_flush_stdout (sd);
1220 else if (fd == 2)
1221 sim_io_flush_stderr (sd);
1222 free (buf);
1223 break;
1224 }
1225
1226 case 10: /* int close(int file) */
1227 {
1228 V0 = sim_io_close (sd, (int)A0);
1229 break;
1230 }
1231
1232 case 2: /* Densan monitor: char inbyte(int waitflag) */
1233 {
1234 if (A0 == 0) /* waitflag == NOWAIT */
1235 V0 = (unsigned_word)-1;
1236 }
1237 /* Drop through to case 11 */
1238
1239 case 11: /* char inbyte(void) */
1240 {
1241 char tmp;
1242 /* ensure that all output has gone... */
1243 sim_io_flush_stdout (sd);
1244 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1245 {
1246 sim_io_error(sd,"Invalid return from character read");
1247 V0 = (unsigned_word)-1;
1248 }
1249 else
1250 V0 = (unsigned_word)tmp;
1251 break;
1252 }
1253
1254 case 3: /* Densan monitor: void co(char chr) */
1255 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1256 {
1257 char tmp = (char)(A0 & 0xFF);
1258 sim_io_write_stdout (sd, &tmp, sizeof(char));
1259 break;
1260 }
1261
1262 case 13: /* int unlink(const char *path) */
1263 {
1264 char *path = fetch_str (sd, A0);
1265 V0 = sim_io_unlink (sd, path);
1266 free (path);
1267 break;
1268 }
1269
1270 case 14: /* int lseek(int fd, int offset, int whence) */
1271 {
1272 V0 = sim_io_lseek (sd, A0, A1, A2);
1273 break;
1274 }
1275
1276 case 15: /* int stat(const char *path, struct stat *buf); */
1277 {
1278 /* As long as the infrastructure doesn't cache anything
1279 related to the stat mapping, this trick gets us a dual
1280 "struct stat"-type mapping in the least error-prone way. */
1281 host_callback *cb = STATE_CALLBACK (sd);
1282 const char *saved_map = cb->stat_map;
1283 CB_TARGET_DEFS_MAP *saved_syscall_map = cb->syscall_map;
1284 bfd *prog_bfd = STATE_PROG_BFD (sd);
1285 int is_elf32bit = (elf_elfheader(prog_bfd)->e_ident[EI_CLASS] ==
1286 ELFCLASS32);
1287 static CB_SYSCALL s;
1288 CB_SYSCALL_INIT (&s);
1289 s.func = 15;
1290 /* Mask out the sign extension part for 64-bit targets because the
1291 MIPS simulator's memory model is still 32-bit. */
1292 s.arg1 = A0 & 0xFFFFFFFF;
1293 s.arg2 = A1 & 0xFFFFFFFF;
1294 s.p1 = (PTR) sd;
1295 s.p2 = (PTR) cpu;
1296 s.read_mem = sim_syscall_read_mem;
1297 s.write_mem = sim_syscall_write_mem;
1298
1299 cb->syscall_map = (CB_TARGET_DEFS_MAP *) CB_stat_map;
1300 cb->stat_map = is_elf32bit ? stat32_map : stat64_map;
1301
1302 if (cb_syscall (cb, &s) != CB_RC_OK)
1303 sim_engine_halt (sd, cpu, NULL, mips_pc_get (cpu),
1304 sim_stopped, SIM_SIGILL);
1305
1306 V0 = s.result;
1307 cb->stat_map = saved_map;
1308 cb->syscall_map = saved_syscall_map;
1309 break;
1310 }
1311
1312 case 17: /* void _exit() */
1313 {
1314 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1315 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1316 (unsigned int)(A0 & 0xFFFFFFFF));
1317 break;
1318 }
1319
1320 case 28: /* PMON flush_cache */
1321 break;
1322
1323 case 55: /* void get_mem_info(unsigned int *ptr) */
1324 /* in: A0 = pointer to three word memory location */
1325 /* out: [A0 + 0] = size */
1326 /* [A0 + 4] = instruction cache size */
1327 /* [A0 + 8] = data cache size */
1328 {
1329 unsigned_4 value;
1330 unsigned_4 zero = 0;
1331 address_word mem_size;
1332 sim_memopt *entry, *match = NULL;
1333
1334 /* Search for memory region mapped to KSEG0 or KSEG1. */
1335 for (entry = STATE_MEMOPT (sd);
1336 entry != NULL;
1337 entry = entry->next)
1338 {
1339 if ((entry->addr == K0BASE || entry->addr == K1BASE)
1340 && (!match || entry->level < match->level))
1341 match = entry;
1342 else
1343 {
1344 sim_memopt *alias;
1345 for (alias = entry->alias;
1346 alias != NULL;
1347 alias = alias->next)
1348 if ((alias->addr == K0BASE || alias->addr == K1BASE)
1349 && (!match || entry->level < match->level))
1350 match = entry;
1351 }
1352 }
1353
1354 /* Get region size, limit to KSEG1 size (512MB). */
1355 SIM_ASSERT (match != NULL);
1356 mem_size = (match->modulo != 0
1357 ? match->modulo : match->nr_bytes);
1358 if (mem_size > K1SIZE)
1359 mem_size = K1SIZE;
1360
1361 value = mem_size;
1362 H2T (value);
1363 sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
1364 sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
1365 sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
1366 /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
1367 break;
1368 }
1369
1370 case 158: /* PMON printf */
1371 /* in: A0 = pointer to format string */
1372 /* A1 = optional argument 1 */
1373 /* A2 = optional argument 2 */
1374 /* A3 = optional argument 3 */
1375 /* out: void */
1376 /* The following is based on the PMON printf source */
1377 {
1378 address_word s = A0;
1379 unsigned char c;
1380 signed_word *ap = &A1; /* 1st argument */
1381 /* This isn't the quickest way, since we call the host print
1382 routine for every character almost. But it does avoid
1383 having to allocate and manage a temporary string buffer. */
1384 /* TODO: Include check that we only use three arguments (A1,
1385 A2 and A3) */
1386 while (sim_read (sd, s++, &c, 1) && c != '\0')
1387 {
1388 if (c == '%')
1389 {
1390 char tmp[40];
1391 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1392 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1393 while (sim_read (sd, s++, &c, 1) && c != '\0')
1394 {
1395 if (strchr ("dobxXulscefg%", c))
1396 break;
1397 else if (c == '-')
1398 fmt = FMT_LJUST;
1399 else if (c == '0')
1400 fmt = FMT_RJUST0;
1401 else if (c == '~')
1402 fmt = FMT_CENTER;
1403 else if (c == '*')
1404 {
1405 if (haddot)
1406 trunc = (int)*ap++;
1407 else
1408 width = (int)*ap++;
1409 }
1410 else if (c >= '1' && c <= '9')
1411 {
1412 address_word t = s;
1413 unsigned int n;
1414 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1415 tmp[s - t] = c;
1416 tmp[s - t] = '\0';
1417 n = (unsigned int)strtol(tmp,NULL,10);
1418 if (haddot)
1419 trunc = n;
1420 else
1421 width = n;
1422 s--;
1423 }
1424 else if (c == '.')
1425 haddot = 1;
1426 }
1427 switch (c)
1428 {
1429 case '%':
1430 sim_io_printf (sd, "%%");
1431 break;
1432 case 's':
1433 if ((int)*ap != 0)
1434 {
1435 address_word p = *ap++;
1436 unsigned char ch;
1437 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1438 sim_io_printf(sd, "%c", ch);
1439 }
1440 else
1441 sim_io_printf(sd,"(null)");
1442 break;
1443 case 'c':
1444 sim_io_printf (sd, "%c", (int)*ap++);
1445 break;
1446 default:
1447 if (c == 'l')
1448 {
1449 sim_read (sd, s++, &c, 1);
1450 if (c == 'l')
1451 {
1452 longlong = 1;
1453 sim_read (sd, s++, &c, 1);
1454 }
1455 }
1456 if (strchr ("dobxXu", c))
1457 {
1458 word64 lv = (word64) *ap++;
1459 if (c == 'b')
1460 sim_io_printf(sd,"<binary not supported>");
1461 else
1462 {
1463 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1464 if (longlong)
1465 sim_io_printf(sd, tmp, lv);
1466 else
1467 sim_io_printf(sd, tmp, (int)lv);
1468 }
1469 }
1470 else if (strchr ("eEfgG", c))
1471 {
1472 double dbl = *(double*)(ap++);
1473 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1474 sim_io_printf (sd, tmp, dbl);
1475 trunc = 0;
1476 }
1477 }
1478 }
1479 else
1480 sim_io_printf(sd, "%c", c);
1481 }
1482 break;
1483 }
1484
1485 default:
1486 /* Unknown reason. */
1487 return 0;
1488 }
1489 return 1;
1490 }
1491
1492 /* Store a word into memory. */
1493
1494 static void
1495 store_word (SIM_DESC sd,
1496 sim_cpu *cpu,
1497 address_word cia,
1498 uword64 vaddr,
1499 signed_word val)
1500 {
1501 address_word paddr = vaddr;
1502
1503 if ((vaddr & 3) != 0)
1504 SignalExceptionAddressStore ();
1505 else
1506 {
1507 const uword64 mask = 7;
1508 uword64 memval;
1509 unsigned int byte;
1510
1511 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1512 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1513 memval = ((uword64) val) << (8 * byte);
1514 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
1515 isREAL);
1516 }
1517 }
1518
1519 /* Load a word from memory. */
1520
1521 static signed_word
1522 load_word (SIM_DESC sd,
1523 sim_cpu *cpu,
1524 address_word cia,
1525 uword64 vaddr)
1526 {
1527 if ((vaddr & 3) != 0)
1528 {
1529 SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
1530 }
1531 else
1532 {
1533 address_word paddr = vaddr;
1534 const uword64 mask = 0x7;
1535 const unsigned int reverse = ReverseEndian ? 1 : 0;
1536 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1537 uword64 memval;
1538 unsigned int byte;
1539
1540 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1541 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
1542 isREAL);
1543 byte = (vaddr & mask) ^ (bigend << 2);
1544 return EXTEND32 (memval >> (8 * byte));
1545 }
1546
1547 return 0;
1548 }
1549
1550 /* Simulate the mips16 entry and exit pseudo-instructions. These
1551 would normally be handled by the reserved instruction exception
1552 code, but for ease of simulation we just handle them directly. */
1553
1554 static void
1555 mips16_entry (SIM_DESC sd,
1556 sim_cpu *cpu,
1557 address_word cia,
1558 unsigned int insn)
1559 {
1560 int aregs, sregs, rreg;
1561
1562 #ifdef DEBUG
1563 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1564 #endif /* DEBUG */
1565
1566 aregs = (insn & 0x700) >> 8;
1567 sregs = (insn & 0x0c0) >> 6;
1568 rreg = (insn & 0x020) >> 5;
1569
1570 /* This should be checked by the caller. */
1571 if (sregs == 3)
1572 abort ();
1573
1574 if (aregs < 5)
1575 {
1576 int i;
1577 signed_word tsp;
1578
1579 /* This is the entry pseudo-instruction. */
1580
1581 for (i = 0; i < aregs; i++)
1582 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1583
1584 tsp = SP;
1585 SP -= 32;
1586
1587 if (rreg)
1588 {
1589 tsp -= 4;
1590 store_word (SD, CPU, cia, (uword64) tsp, RA);
1591 }
1592
1593 for (i = 0; i < sregs; i++)
1594 {
1595 tsp -= 4;
1596 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1597 }
1598 }
1599 else
1600 {
1601 int i;
1602 signed_word tsp;
1603
1604 /* This is the exit pseudo-instruction. */
1605
1606 tsp = SP + 32;
1607
1608 if (rreg)
1609 {
1610 tsp -= 4;
1611 RA = load_word (SD, CPU, cia, (uword64) tsp);
1612 }
1613
1614 for (i = 0; i < sregs; i++)
1615 {
1616 tsp -= 4;
1617 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1618 }
1619
1620 SP += 32;
1621
1622 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1623 {
1624 if (aregs == 5)
1625 {
1626 FGR[0] = WORD64LO (GPR[4]);
1627 FPR_STATE[0] = fmt_uninterpreted;
1628 }
1629 else if (aregs == 6)
1630 {
1631 FGR[0] = WORD64LO (GPR[5]);
1632 FGR[1] = WORD64LO (GPR[4]);
1633 FPR_STATE[0] = fmt_uninterpreted;
1634 FPR_STATE[1] = fmt_uninterpreted;
1635 }
1636 }
1637
1638 PC = RA;
1639 }
1640
1641 }
1642
1643 /*-- trace support ----------------------------------------------------------*/
1644
1645 /* The trace support is provided (if required) in the memory accessing
1646 routines. Since we are also providing the architecture specific
1647 features, the architecture simulation code can also deal with
1648 notifying the trace world of cache flushes, etc. Similarly we do
1649 not need to provide profiling support in the simulator engine,
1650 since we can sample in the instruction fetch control loop. By
1651 defining the trace manifest, we add tracing as a run-time
1652 option. */
1653
1654 #if WITH_TRACE_ANY_P
1655 /* Tracing by default produces "din" format (as required by
1656 dineroIII). Each line of such a trace file *MUST* have a din label
1657 and address field. The rest of the line is ignored, so comments can
1658 be included if desired. The first field is the label which must be
1659 one of the following values:
1660
1661 0 read data
1662 1 write data
1663 2 instruction fetch
1664 3 escape record (treated as unknown access type)
1665 4 escape record (causes cache flush)
1666
1667 The address field is a 32bit (lower-case) hexadecimal address
1668 value. The address should *NOT* be preceded by "0x".
1669
1670 The size of the memory transfer is not important when dealing with
1671 cache lines (as long as no more than a cache line can be
1672 transferred in a single operation :-), however more information
1673 could be given following the dineroIII requirement to allow more
1674 complete memory and cache simulators to provide better
1675 results. i.e. the University of Pisa has a cache simulator that can
1676 also take bus size and speed as (variable) inputs to calculate
1677 complete system performance (a much more useful ability when trying
1678 to construct an end product, rather than a processor). They
1679 currently have an ARM version of their tool called ChARM. */
1680
1681
1682 void
1683 dotrace (SIM_DESC sd,
1684 sim_cpu *cpu,
1685 FILE *tracefh,
1686 int type,
1687 SIM_ADDR address,
1688 int width,
1689 char *comment,...)
1690 {
1691 if (STATE & simTRACE) {
1692 va_list ap;
1693 fprintf(tracefh,"%d %s ; width %d ; ",
1694 type,
1695 pr_addr(address),
1696 width);
1697 va_start(ap,comment);
1698 vfprintf(tracefh,comment,ap);
1699 va_end(ap);
1700 fprintf(tracefh,"\n");
1701 }
1702 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1703 we may be generating 64bit ones, we should put the hi-32bits of the
1704 address into the comment field. */
1705
1706 /* TODO: Provide a buffer for the trace lines. We can then avoid
1707 performing writes until the buffer is filled, or the file is
1708 being closed. */
1709
1710 /* NOTE: We could consider adding a comment field to the "din" file
1711 produced using type 3 markers (unknown access). This would then
1712 allow information about the program that the "din" is for, and
1713 the MIPs world that was being simulated, to be placed into the
1714 trace file. */
1715
1716 return;
1717 }
1718 #endif /* WITH_TRACE_ANY_P */
1719
1720 /*---------------------------------------------------------------------------*/
1721 /*-- simulator engine -------------------------------------------------------*/
1722 /*---------------------------------------------------------------------------*/
1723
1724 static void
1725 ColdReset (SIM_DESC sd)
1726 {
1727 int cpu_nr;
1728 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1729 {
1730 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1731 /* RESET: Fixed PC address: */
1732 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1733 /* The reset vector address is in the unmapped, uncached memory space. */
1734
1735 SR &= ~(status_SR | status_TS | status_RP);
1736 SR |= (status_ERL | status_BEV);
1737
1738 /* Cheat and allow access to the complete register set immediately */
1739 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1740 && WITH_TARGET_WORD_BITSIZE == 64)
1741 SR |= status_FR; /* 64bit registers */
1742
1743 /* Ensure that any instructions with pending register updates are
1744 cleared: */
1745 PENDING_INVALIDATE();
1746
1747 /* Initialise the FPU registers to the unknown state */
1748 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1749 {
1750 int rn;
1751 for (rn = 0; (rn < 32); rn++)
1752 FPR_STATE[rn] = fmt_uninterpreted;
1753 }
1754
1755 /* Initialise the Config0 register. */
1756 C0_CONFIG = 0x80000000 /* Config1 present */
1757 | 2; /* KSEG0 uncached */
1758 if (WITH_TARGET_WORD_BITSIZE == 64)
1759 {
1760 /* FIXME Currently mips/sim-main.c:address_translation()
1761 truncates all addresses to 32-bits. */
1762 if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
1763 C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
1764 else
1765 C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
1766 }
1767 if (BigEndianMem)
1768 C0_CONFIG |= 0x00008000; /* Big Endian */
1769 }
1770 }
1771
1772
1773
1774
1775 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1776 /* Signal an exception condition. This will result in an exception
1777 that aborts the instruction. The instruction operation pseudocode
1778 will never see a return from this function call. */
1779
1780 void
1781 signal_exception (SIM_DESC sd,
1782 sim_cpu *cpu,
1783 address_word cia,
1784 int exception,...)
1785 {
1786 /* int vector; */
1787
1788 #ifdef DEBUG
1789 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1790 #endif /* DEBUG */
1791
1792 /* Ensure that any active atomic read/modify/write operation will fail: */
1793 LLBIT = 0;
1794
1795 /* Save registers before interrupt dispatching */
1796 #ifdef SIM_CPU_EXCEPTION_TRIGGER
1797 SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
1798 #endif
1799
1800 switch (exception) {
1801
1802 case DebugBreakPoint:
1803 if (! (Debug & Debug_DM))
1804 {
1805 if (INDELAYSLOT())
1806 {
1807 CANCELDELAYSLOT();
1808
1809 Debug |= Debug_DBD; /* signaled from within in delay slot */
1810 DEPC = cia - 4; /* reference the branch instruction */
1811 }
1812 else
1813 {
1814 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1815 DEPC = cia;
1816 }
1817
1818 Debug |= Debug_DM; /* in debugging mode */
1819 Debug |= Debug_DBp; /* raising a DBp exception */
1820 PC = 0xBFC00200;
1821 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1822 }
1823 break;
1824
1825 case ReservedInstruction:
1826 {
1827 va_list ap;
1828 unsigned int instruction;
1829 va_start(ap,exception);
1830 instruction = va_arg(ap,unsigned int);
1831 va_end(ap);
1832 /* Provide simple monitor support using ReservedInstruction
1833 exceptions. The following code simulates the fixed vector
1834 entry points into the IDT monitor by causing a simulator
1835 trap, performing the monitor operation, and returning to
1836 the address held in the $ra register (standard PCS return
1837 address). This means we only need to pre-load the vector
1838 space with suitable instruction values. For systems were
1839 actual trap instructions are used, we would not need to
1840 perform this magic. */
1841 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1842 {
1843 int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
1844 if (!sim_monitor (SD, CPU, cia, reason))
1845 sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
1846
1847 /* NOTE: This assumes that a branch-and-link style
1848 instruction was used to enter the vector (which is the
1849 case with the current IDT monitor). */
1850 sim_engine_restart (SD, CPU, NULL, RA);
1851 }
1852 /* Look for the mips16 entry and exit instructions, and
1853 simulate a handler for them. */
1854 else if ((cia & 1) != 0
1855 && (instruction & 0xf81f) == 0xe809
1856 && (instruction & 0x0c0) != 0x0c0)
1857 {
1858 mips16_entry (SD, CPU, cia, instruction);
1859 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1860 }
1861 /* else fall through to normal exception processing */
1862 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1863 }
1864
1865 default:
1866 /* Store exception code into current exception id variable (used
1867 by exit code): */
1868
1869 /* TODO: If not simulating exceptions then stop the simulator
1870 execution. At the moment we always stop the simulation. */
1871
1872 #ifdef SUBTARGET_R3900
1873 /* update interrupt-related registers */
1874
1875 /* insert exception code in bits 6:2 */
1876 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1877 /* shift IE/KU history bits left */
1878 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1879
1880 if (STATE & simDELAYSLOT)
1881 {
1882 STATE &= ~simDELAYSLOT;
1883 CAUSE |= cause_BD;
1884 EPC = (cia - 4); /* reference the branch instruction */
1885 }
1886 else
1887 EPC = cia;
1888
1889 if (SR & status_BEV)
1890 PC = (signed)0xBFC00000 + 0x180;
1891 else
1892 PC = (signed)0x80000000 + 0x080;
1893 #else
1894 /* See figure 5-17 for an outline of the code below */
1895 if (! (SR & status_EXL))
1896 {
1897 CAUSE = (exception << 2);
1898 if (STATE & simDELAYSLOT)
1899 {
1900 STATE &= ~simDELAYSLOT;
1901 CAUSE |= cause_BD;
1902 EPC = (cia - 4); /* reference the branch instruction */
1903 }
1904 else
1905 EPC = cia;
1906 /* FIXME: TLB et.al. */
1907 /* vector = 0x180; */
1908 }
1909 else
1910 {
1911 CAUSE = (exception << 2);
1912 /* vector = 0x180; */
1913 }
1914 SR |= status_EXL;
1915 /* Store exception code into current exception id variable (used
1916 by exit code): */
1917
1918 if (SR & status_BEV)
1919 PC = (signed)0xBFC00200 + 0x180;
1920 else
1921 PC = (signed)0x80000000 + 0x180;
1922 #endif
1923
1924 switch ((CAUSE >> 2) & 0x1F)
1925 {
1926 case Interrupt:
1927 /* Interrupts arrive during event processing, no need to
1928 restart */
1929 return;
1930
1931 case NMIReset:
1932 /* Ditto */
1933 #ifdef SUBTARGET_3900
1934 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1935 PC = (signed)0xBFC00000;
1936 #endif /* SUBTARGET_3900 */
1937 return;
1938
1939 case TLBModification:
1940 case TLBLoad:
1941 case TLBStore:
1942 case AddressLoad:
1943 case AddressStore:
1944 case InstructionFetch:
1945 case DataReference:
1946 /* The following is so that the simulator will continue from the
1947 exception handler address. */
1948 sim_engine_halt (SD, CPU, NULL, PC,
1949 sim_stopped, SIM_SIGBUS);
1950
1951 case ReservedInstruction:
1952 case CoProcessorUnusable:
1953 PC = EPC;
1954 sim_engine_halt (SD, CPU, NULL, PC,
1955 sim_stopped, SIM_SIGILL);
1956
1957 case IntegerOverflow:
1958 case FPE:
1959 sim_engine_halt (SD, CPU, NULL, PC,
1960 sim_stopped, SIM_SIGFPE);
1961
1962 case BreakPoint:
1963 sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
1964 break;
1965
1966 case SystemCall:
1967 case Trap:
1968 sim_engine_restart (SD, CPU, NULL, PC);
1969 break;
1970
1971 case Watch:
1972 PC = EPC;
1973 sim_engine_halt (SD, CPU, NULL, PC,
1974 sim_stopped, SIM_SIGTRAP);
1975
1976 default: /* Unknown internal exception */
1977 PC = EPC;
1978 sim_engine_halt (SD, CPU, NULL, PC,
1979 sim_stopped, SIM_SIGABRT);
1980
1981 }
1982
1983 case SimulatorFault:
1984 {
1985 va_list ap;
1986 char *msg;
1987 va_start(ap,exception);
1988 msg = va_arg(ap,char *);
1989 va_end(ap);
1990 sim_engine_abort (SD, CPU, NULL_CIA,
1991 "FATAL: Simulator error \"%s\"\n",msg);
1992 }
1993 }
1994
1995 return;
1996 }
1997
1998
1999
2000 /* This function implements what the MIPS32 and MIPS64 ISAs define as
2001 "UNPREDICTABLE" behaviour.
2002
2003 About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
2004 may vary from processor implementation to processor implementation,
2005 instruction to instruction, or as a function of time on the same
2006 implementation or instruction. Software can never depend on results
2007 that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
2008 Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
2009 0.95, page 2.)
2010
2011 For UNPREDICTABLE behaviour, we print a message, if possible print
2012 the offending instructions mips.igen instruction name (provided by
2013 the caller), and stop the simulator.
2014
2015 XXX FIXME: eventually, stopping the simulator should be made conditional
2016 on a command-line option. */
2017 void
2018 unpredictable_action(sim_cpu *cpu, address_word cia)
2019 {
2020 SIM_DESC sd = CPU_STATE(cpu);
2021
2022 sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
2023 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
2024 }
2025
2026
2027 /*-- co-processor support routines ------------------------------------------*/
2028
2029 static int UNUSED
2030 CoProcPresent(unsigned int coproc_number)
2031 {
2032 /* Return TRUE if simulator provides a model for the given co-processor number */
2033 return(0);
2034 }
2035
2036 void
2037 cop_lw (SIM_DESC sd,
2038 sim_cpu *cpu,
2039 address_word cia,
2040 int coproc_num,
2041 int coproc_reg,
2042 unsigned int memword)
2043 {
2044 switch (coproc_num)
2045 {
2046 case 1:
2047 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2048 {
2049 #ifdef DEBUG
2050 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
2051 #endif
2052 StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
2053 break;
2054 }
2055
2056 default:
2057 #if 0 /* this should be controlled by a configuration option */
2058 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
2059 #endif
2060 break;
2061 }
2062
2063 return;
2064 }
2065
2066 void
2067 cop_ld (SIM_DESC sd,
2068 sim_cpu *cpu,
2069 address_word cia,
2070 int coproc_num,
2071 int coproc_reg,
2072 uword64 memword)
2073 {
2074
2075 #ifdef DEBUG
2076 printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
2077 #endif
2078
2079 switch (coproc_num) {
2080 case 1:
2081 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2082 {
2083 StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
2084 break;
2085 }
2086
2087 default:
2088 #if 0 /* this message should be controlled by a configuration option */
2089 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
2090 #endif
2091 break;
2092 }
2093
2094 return;
2095 }
2096
2097
2098
2099
2100 unsigned int
2101 cop_sw (SIM_DESC sd,
2102 sim_cpu *cpu,
2103 address_word cia,
2104 int coproc_num,
2105 int coproc_reg)
2106 {
2107 unsigned int value = 0;
2108
2109 switch (coproc_num)
2110 {
2111 case 1:
2112 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2113 {
2114 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
2115 break;
2116 }
2117
2118 default:
2119 #if 0 /* should be controlled by configuration option */
2120 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2121 #endif
2122 break;
2123 }
2124
2125 return(value);
2126 }
2127
2128 uword64
2129 cop_sd (SIM_DESC sd,
2130 sim_cpu *cpu,
2131 address_word cia,
2132 int coproc_num,
2133 int coproc_reg)
2134 {
2135 uword64 value = 0;
2136 switch (coproc_num)
2137 {
2138 case 1:
2139 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2140 {
2141 value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
2142 break;
2143 }
2144
2145 default:
2146 #if 0 /* should be controlled by configuration option */
2147 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
2148 #endif
2149 break;
2150 }
2151
2152 return(value);
2153 }
2154
2155
2156
2157
2158 void
2159 decode_coproc (SIM_DESC sd,
2160 sim_cpu *cpu,
2161 address_word cia,
2162 unsigned int instruction,
2163 int coprocnum,
2164 CP0_operation op,
2165 int rt,
2166 int rd,
2167 int sel)
2168 {
2169 switch (coprocnum)
2170 {
2171 case 0: /* standard CPU control and cache registers */
2172 {
2173 /* R4000 Users Manual (second edition) lists the following CP0
2174 instructions:
2175 CODE><-RT><RD-><--TAIL--->
2176 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2177 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2178 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2179 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2180 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2181 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2182 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2183 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2184 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2185 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2186 */
2187 if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
2188 || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
2189 && sel == 0)
2190 {
2191 switch (rd) /* NOTEs: Standard CP0 registers */
2192 {
2193 /* 0 = Index R4000 VR4100 VR4300 */
2194 /* 1 = Random R4000 VR4100 VR4300 */
2195 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2196 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2197 /* 4 = Context R4000 VR4100 VR4300 */
2198 /* 5 = PageMask R4000 VR4100 VR4300 */
2199 /* 6 = Wired R4000 VR4100 VR4300 */
2200 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2201 /* 9 = Count R4000 VR4100 VR4300 */
2202 /* 10 = EntryHi R4000 VR4100 VR4300 */
2203 /* 11 = Compare R4000 VR4100 VR4300 */
2204 /* 12 = SR R4000 VR4100 VR4300 */
2205 #ifdef SUBTARGET_R3900
2206 case 3:
2207 /* 3 = Config R3900 */
2208 case 7:
2209 /* 7 = Cache R3900 */
2210 case 15:
2211 /* 15 = PRID R3900 */
2212
2213 /* ignore */
2214 break;
2215
2216 case 8:
2217 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2218 if (op == cp0_mfc0 || op == cp0_dmfc0)
2219 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
2220 else
2221 COP0_BADVADDR = GPR[rt];
2222 break;
2223
2224 #endif /* SUBTARGET_R3900 */
2225 case 12:
2226 if (op == cp0_mfc0 || op == cp0_dmfc0)
2227 GPR[rt] = SR;
2228 else
2229 SR = GPR[rt];
2230 break;
2231 /* 13 = Cause R4000 VR4100 VR4300 */
2232 case 13:
2233 if (op == cp0_mfc0 || op == cp0_dmfc0)
2234 GPR[rt] = CAUSE;
2235 else
2236 CAUSE = GPR[rt];
2237 break;
2238 /* 14 = EPC R4000 VR4100 VR4300 */
2239 case 14:
2240 if (op == cp0_mfc0 || op == cp0_dmfc0)
2241 GPR[rt] = (signed_word) (signed_address) EPC;
2242 else
2243 EPC = GPR[rt];
2244 break;
2245 /* 15 = PRId R4000 VR4100 VR4300 */
2246 #ifdef SUBTARGET_R3900
2247 /* 16 = Debug */
2248 case 16:
2249 if (op == cp0_mfc0 || op == cp0_dmfc0)
2250 GPR[rt] = Debug;
2251 else
2252 Debug = GPR[rt];
2253 break;
2254 #else
2255 /* 16 = Config R4000 VR4100 VR4300 */
2256 case 16:
2257 if (op == cp0_mfc0 || op == cp0_dmfc0)
2258 GPR[rt] = C0_CONFIG;
2259 else
2260 /* only bottom three bits are writable */
2261 C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
2262 break;
2263 #endif
2264 #ifdef SUBTARGET_R3900
2265 /* 17 = Debug */
2266 case 17:
2267 if (op == cp0_mfc0 || op == cp0_dmfc0)
2268 GPR[rt] = DEPC;
2269 else
2270 DEPC = GPR[rt];
2271 break;
2272 #else
2273 /* 17 = LLAddr R4000 VR4100 VR4300 */
2274 #endif
2275 /* 18 = WatchLo R4000 VR4100 VR4300 */
2276 /* 19 = WatchHi R4000 VR4100 VR4300 */
2277 /* 20 = XContext R4000 VR4100 VR4300 */
2278 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
2279 /* 27 = CacheErr R4000 VR4100 */
2280 /* 28 = TagLo R4000 VR4100 VR4300 */
2281 /* 29 = TagHi R4000 VR4100 VR4300 */
2282 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
2283 if (STATE_VERBOSE_P(SD))
2284 sim_io_eprintf (SD,
2285 "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
2286 (unsigned long)cia);
2287 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
2288 /* CPR[0,rd] = GPR[rt]; */
2289 default:
2290 if (op == cp0_mfc0 || op == cp0_dmfc0)
2291 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
2292 else
2293 COP0_GPR[rd] = GPR[rt];
2294 #if 0
2295 if (code == 0x00)
2296 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2297 else
2298 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
2299 #endif
2300 }
2301 }
2302 else if ((op == cp0_mfc0 || op == cp0_dmfc0)
2303 && rd == 16)
2304 {
2305 /* [D]MFC0 RT,C0_CONFIG,SEL */
2306 signed32 cfg = 0;
2307 switch (sel)
2308 {
2309 case 0:
2310 cfg = C0_CONFIG;
2311 break;
2312 case 1:
2313 /* MIPS32 r/o Config1:
2314 Config2 present */
2315 cfg = 0x80000000;
2316 /* MIPS16 implemented.
2317 XXX How to check configuration? */
2318 cfg |= 0x0000004;
2319 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
2320 /* MDMX & FPU implemented */
2321 cfg |= 0x00000021;
2322 break;
2323 case 2:
2324 /* MIPS32 r/o Config2:
2325 Config3 present. */
2326 cfg = 0x80000000;
2327 break;
2328 case 3:
2329 /* MIPS32 r/o Config3:
2330 SmartMIPS implemented. */
2331 cfg = 0x00000002;
2332 break;
2333 }
2334 GPR[rt] = cfg;
2335 }
2336 else if (op == cp0_eret && sel == 0x18)
2337 {
2338 /* ERET */
2339 if (SR & status_ERL)
2340 {
2341 /* Oops, not yet available */
2342 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
2343 PC = EPC;
2344 SR &= ~status_ERL;
2345 }
2346 else
2347 {
2348 PC = EPC;
2349 SR &= ~status_EXL;
2350 }
2351 }
2352 else if (op == cp0_rfe && sel == 0x10)
2353 {
2354 /* RFE */
2355 #ifdef SUBTARGET_R3900
2356 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
2357
2358 /* shift IE/KU history bits right */
2359 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
2360
2361 /* TODO: CACHE register */
2362 #endif /* SUBTARGET_R3900 */
2363 }
2364 else if (op == cp0_deret && sel == 0x1F)
2365 {
2366 /* DERET */
2367 Debug &= ~Debug_DM;
2368 DELAYSLOT();
2369 DSPC = DEPC;
2370 }
2371 else
2372 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
2373 /* TODO: When executing an ERET or RFE instruction we should
2374 clear LLBIT, to ensure that any out-standing atomic
2375 read/modify/write sequence fails. */
2376 }
2377 break;
2378
2379 case 2: /* co-processor 2 */
2380 {
2381 int handle = 0;
2382
2383
2384 if(! handle)
2385 {
2386 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
2387 instruction,pr_addr(cia));
2388 }
2389 }
2390 break;
2391
2392 case 1: /* should not occur (FPU co-processor) */
2393 case 3: /* should not occur (FPU co-processor) */
2394 SignalException(ReservedInstruction,instruction);
2395 break;
2396 }
2397
2398 return;
2399 }
2400
2401
2402 /* This code copied from gdb's utils.c. Would like to share this code,
2403 but don't know of a common place where both could get to it. */
2404
2405 /* Temporary storage using circular buffer */
2406 #define NUMCELLS 16
2407 #define CELLSIZE 32
2408 static char*
2409 get_cell (void)
2410 {
2411 static char buf[NUMCELLS][CELLSIZE];
2412 static int cell=0;
2413 if (++cell>=NUMCELLS) cell=0;
2414 return buf[cell];
2415 }
2416
2417 /* Print routines to handle variable size regs, etc */
2418
2419 /* Eliminate warning from compiler on 32-bit systems */
2420 static int thirty_two = 32;
2421
2422 char*
2423 pr_addr (SIM_ADDR addr)
2424 {
2425 char *paddr_str=get_cell();
2426 switch (sizeof(addr))
2427 {
2428 case 8:
2429 sprintf(paddr_str,"%08lx%08lx",
2430 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2431 break;
2432 case 4:
2433 sprintf(paddr_str,"%08lx",(unsigned long)addr);
2434 break;
2435 case 2:
2436 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
2437 break;
2438 default:
2439 sprintf(paddr_str,"%x",addr);
2440 }
2441 return paddr_str;
2442 }
2443
2444 char*
2445 pr_uword64 (uword64 addr)
2446 {
2447 char *paddr_str=get_cell();
2448 sprintf(paddr_str,"%08lx%08lx",
2449 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
2450 return paddr_str;
2451 }
2452
2453
2454 void
2455 mips_core_signal (SIM_DESC sd,
2456 sim_cpu *cpu,
2457 sim_cia cia,
2458 unsigned map,
2459 int nr_bytes,
2460 address_word addr,
2461 transfer_type transfer,
2462 sim_core_signals sig)
2463 {
2464 const char *copy = (transfer == read_transfer ? "read" : "write");
2465 address_word ip = CIA_ADDR (cia);
2466
2467 switch (sig)
2468 {
2469 case sim_core_unmapped_signal:
2470 sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
2471 nr_bytes, copy,
2472 (unsigned long) addr, (unsigned long) ip);
2473 COP0_BADVADDR = addr;
2474 SignalExceptionDataReference();
2475 break;
2476
2477 case sim_core_unaligned_signal:
2478 sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
2479 nr_bytes, copy,
2480 (unsigned long) addr, (unsigned long) ip);
2481 COP0_BADVADDR = addr;
2482 if(transfer == read_transfer)
2483 SignalExceptionAddressLoad();
2484 else
2485 SignalExceptionAddressStore();
2486 break;
2487
2488 default:
2489 sim_engine_abort (sd, cpu, cia,
2490 "mips_core_signal - internal error - bad switch");
2491 }
2492 }
2493
2494
2495 void
2496 mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
2497 {
2498 ASSERT(cpu != NULL);
2499
2500 if(cpu->exc_suspended > 0)
2501 sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
2502
2503 PC = cia;
2504 memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
2505 cpu->exc_suspended = 0;
2506 }
2507
2508 void
2509 mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
2510 {
2511 ASSERT(cpu != NULL);
2512
2513 if(cpu->exc_suspended > 0)
2514 sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
2515 cpu->exc_suspended, exception);
2516
2517 memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
2518 memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
2519 cpu->exc_suspended = exception;
2520 }
2521
2522 void
2523 mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
2524 {
2525 ASSERT(cpu != NULL);
2526
2527 if(exception == 0 && cpu->exc_suspended > 0)
2528 {
2529 /* warn not for breakpoints */
2530 if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
2531 sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
2532 cpu->exc_suspended);
2533 }
2534 else if(exception != 0 && cpu->exc_suspended > 0)
2535 {
2536 if(exception != cpu->exc_suspended)
2537 sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
2538 cpu->exc_suspended, exception);
2539
2540 memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
2541 }
2542 else if(exception != 0 && cpu->exc_suspended == 0)
2543 {
2544 sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
2545 }
2546 cpu->exc_suspended = 0;
2547 }
2548
2549
2550 /*---------------------------------------------------------------------------*/
2551 /*> EOF interp.c <*/
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