4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
57 // Pseudo instructions known by IGEN
60 SignalException (ReservedInstruction, 0);
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
69 SignalException (ReservedInstruction, instruction_0);
76 // Simulate a 32 bit delayslot instruction
79 :function:::address_word:delayslot32:address_word target
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
92 :function:::address_word:nullify_next_insn32:
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
103 // Check that an access to a HI/LO register meets timing requirements
105 // The following requirements exist:
107 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
108 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
109 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
110 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
115 if (history->mf.timestamp + 3 > time)
117 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
118 itable[MY_INDEX].name,
120 (long) history->mf.cia);
126 :function:::int:check_mt_hilo:hilo_history *history
127 *mipsI,mipsII,mipsIII,mipsIV:
129 // start-sanitize-vr4320
131 // end-sanitize-vr4320
132 // start-sanitize-vr5400
134 // end-sanitize-vr5400
135 // start-sanitize-r5900
137 // end-sanitize-r5900
139 signed64 time = sim_events_time (SD);
140 int ok = check_mf_cycles (SD_, history, time, "MT");
141 history->mt.timestamp = time;
142 history->mt.cia = CIA;
146 :function:::int:check_mt_hilo:hilo_history *history
148 // start-sanitize-tx19
152 signed64 time = sim_events_time (SD);
153 history->mt.timestamp = time;
154 history->mt.cia = CIA;
158 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
160 signed64 time = sim_events_time (SD);
163 && peer->mt.timestamp > history->op.timestamp
164 && history->mf.timestamp < history->op.timestamp)
166 /* The peer has been written to since the last OP yet we have
168 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
169 itable[MY_INDEX].name,
171 (long) history->op.cia,
172 (long) peer->mt.cia);
175 history->mf.timestamp = time;
176 history->mf.cia = CIA;
180 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
181 *mipsI,mipsII,mipsIII,mipsIV:
183 // start-sanitize-vr4320
185 // end-sanitize-vr4320
186 // start-sanitize-vr5400
188 // end-sanitize-vr5400
189 // start-sanitize-r5900
191 // end-sanitize-r5900
193 signed64 time = sim_events_time (SD);
194 int ok = (check_mf_cycles (SD_, hi, time, "OP")
195 && check_mf_cycles (SD_, lo, time, "OP"));
196 hi->op.timestamp = time;
197 lo->op.timestamp = time;
204 // The r3900 mult and multu insns _can_ be exectuted immediatly after
206 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
208 // start-sanitize-tx19
212 signed64 time = sim_events_time (SD);
213 hi->op.timestamp = time;
214 lo->op.timestamp = time;
220 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
221 *mipsI,mipsII,mipsIII,mipsIV:
223 // start-sanitize-vr4320
225 // end-sanitize-vr4320
226 // start-sanitize-vr5400
228 // end-sanitize-vr5400
230 // start-sanitize-tx19
233 // start-sanitize-r5900
235 // end-sanitize-r5900
237 signed64 time = sim_events_time (SD);
238 int ok = (check_mf_cycles (SD_, hi, time, "OP")
239 && check_mf_cycles (SD_, lo, time, "OP"));
240 hi->op.timestamp = time;
241 lo->op.timestamp = time;
250 // Mips Architecture:
252 // CPU Instruction Set (mipsI - mipsIV)
257 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
258 "add r<RD>, r<RS>, r<RT>"
259 *mipsI,mipsII,mipsIII,mipsIV:
261 // start-sanitize-vr4320
263 // end-sanitize-vr4320
264 // start-sanitize-vr5400
266 // end-sanitize-vr5400
267 // start-sanitize-r5900
269 // end-sanitize-r5900
271 // start-sanitize-tx19
275 ALU32_BEGIN (GPR[RS]);
282 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
283 "addi r<RT>, r<RS>, IMMEDIATE"
284 *mipsI,mipsII,mipsIII,mipsIV:
286 // start-sanitize-vr4320
288 // end-sanitize-vr4320
289 // start-sanitize-vr5400
291 // end-sanitize-vr5400
292 // start-sanitize-r5900
294 // end-sanitize-r5900
296 // start-sanitize-tx19
300 ALU32_BEGIN (GPR[RS]);
301 ALU32_ADD (EXTEND16 (IMMEDIATE));
307 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
309 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
310 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
311 TRACE_ALU_RESULT (GPR[rt]);
314 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
315 "addiu r<RT>, r<RS>, <IMMEDIATE>"
316 *mipsI,mipsII,mipsIII,mipsIV:
318 // start-sanitize-vr4320
320 // end-sanitize-vr4320
321 // start-sanitize-vr5400
323 // end-sanitize-vr5400
324 // start-sanitize-r5900
326 // end-sanitize-r5900
328 // start-sanitize-tx19
332 do_addiu (SD_, RS, RT, IMMEDIATE);
337 :function:::void:do_addu:int rs, int rt, int rd
339 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
340 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
341 TRACE_ALU_RESULT (GPR[rd]);
344 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
345 "addu r<RD>, r<RS>, r<RT>"
346 *mipsI,mipsII,mipsIII,mipsIV:
348 // start-sanitize-vr4320
350 // end-sanitize-vr4320
351 // start-sanitize-vr5400
353 // end-sanitize-vr5400
354 // start-sanitize-r5900
356 // end-sanitize-r5900
358 // start-sanitize-tx19
362 do_addu (SD_, RS, RT, RD);
367 :function:::void:do_and:int rs, int rt, int rd
369 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
370 GPR[rd] = GPR[rs] & GPR[rt];
371 TRACE_ALU_RESULT (GPR[rd]);
374 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
375 "and r<RD>, r<RS>, r<RT>"
376 *mipsI,mipsII,mipsIII,mipsIV:
378 // start-sanitize-vr4320
380 // end-sanitize-vr4320
381 // start-sanitize-vr5400
383 // end-sanitize-vr5400
384 // start-sanitize-r5900
386 // end-sanitize-r5900
388 // start-sanitize-tx19
392 do_and (SD_, RS, RT, RD);
397 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
398 "and r<RT>, r<RS>, <IMMEDIATE>"
399 *mipsI,mipsII,mipsIII,mipsIV:
401 // start-sanitize-vr4320
403 // end-sanitize-vr4320
404 // start-sanitize-vr5400
406 // end-sanitize-vr5400
407 // start-sanitize-r5900
409 // end-sanitize-r5900
411 // start-sanitize-tx19
415 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
416 GPR[RT] = GPR[RS] & IMMEDIATE;
417 TRACE_ALU_RESULT (GPR[RT]);
422 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
423 "beq r<RS>, r<RT>, <OFFSET>"
424 *mipsI,mipsII,mipsIII,mipsIV:
426 // start-sanitize-vr4320
428 // end-sanitize-vr4320
429 // start-sanitize-vr5400
431 // end-sanitize-vr5400
432 // start-sanitize-r5900
434 // end-sanitize-r5900
436 // start-sanitize-tx19
440 address_word offset = EXTEND16 (OFFSET) << 2;
441 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
442 DELAY_SLOT (NIA + offset);
447 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
448 "beql r<RS>, r<RT>, <OFFSET>"
453 // start-sanitize-vr4320
455 // end-sanitize-vr4320
456 // start-sanitize-vr5400
458 // end-sanitize-vr5400
459 // start-sanitize-r5900
461 // end-sanitize-r5900
463 // start-sanitize-tx19
467 address_word offset = EXTEND16 (OFFSET) << 2;
468 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
469 DELAY_SLOT (NIA + offset);
471 NULLIFY_NEXT_INSTRUCTION ();
476 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
477 "bgez r<RS>, <OFFSET>"
478 *mipsI,mipsII,mipsIII,mipsIV:
480 // start-sanitize-vr4320
482 // end-sanitize-vr4320
483 // start-sanitize-vr5400
485 // end-sanitize-vr5400
486 // start-sanitize-r5900
488 // end-sanitize-r5900
490 // start-sanitize-tx19
494 address_word offset = EXTEND16 (OFFSET) << 2;
495 if ((signed_word) GPR[RS] >= 0)
496 DELAY_SLOT (NIA + offset);
501 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
502 "bgezal r<RS>, <OFFSET>"
503 *mipsI,mipsII,mipsIII,mipsIV:
505 // start-sanitize-vr4320
507 // end-sanitize-vr4320
508 // start-sanitize-vr5400
510 // end-sanitize-vr5400
511 // start-sanitize-r5900
513 // end-sanitize-r5900
515 // start-sanitize-tx19
519 address_word offset = EXTEND16 (OFFSET) << 2;
521 if ((signed_word) GPR[RS] >= 0)
522 DELAY_SLOT (NIA + offset);
527 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
528 "bgezall r<RS>, <OFFSET>"
533 // start-sanitize-vr4320
535 // end-sanitize-vr4320
536 // start-sanitize-vr5400
538 // end-sanitize-vr5400
539 // start-sanitize-r5900
541 // end-sanitize-r5900
543 // start-sanitize-tx19
547 address_word offset = EXTEND16 (OFFSET) << 2;
549 /* NOTE: The branch occurs AFTER the next instruction has been
551 if ((signed_word) GPR[RS] >= 0)
552 DELAY_SLOT (NIA + offset);
554 NULLIFY_NEXT_INSTRUCTION ();
559 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
560 "bgezl r<RS>, <OFFSET>"
565 // start-sanitize-vr4320
567 // end-sanitize-vr4320
568 // start-sanitize-vr5400
570 // end-sanitize-vr5400
571 // start-sanitize-r5900
573 // end-sanitize-r5900
575 // start-sanitize-tx19
579 address_word offset = EXTEND16 (OFFSET) << 2;
580 if ((signed_word) GPR[RS] >= 0)
581 DELAY_SLOT (NIA + offset);
583 NULLIFY_NEXT_INSTRUCTION ();
588 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
589 "bgtz r<RS>, <OFFSET>"
590 *mipsI,mipsII,mipsIII,mipsIV:
592 // start-sanitize-vr4320
594 // end-sanitize-vr4320
595 // start-sanitize-vr5400
597 // end-sanitize-vr5400
598 // start-sanitize-r5900
600 // end-sanitize-r5900
602 // start-sanitize-tx19
606 address_word offset = EXTEND16 (OFFSET) << 2;
607 if ((signed_word) GPR[RS] > 0)
608 DELAY_SLOT (NIA + offset);
613 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
614 "bgtzl r<RS>, <OFFSET>"
619 // start-sanitize-vr4320
621 // end-sanitize-vr4320
622 // start-sanitize-vr5400
624 // end-sanitize-vr5400
625 // start-sanitize-r5900
627 // end-sanitize-r5900
629 // start-sanitize-tx19
633 address_word offset = EXTEND16 (OFFSET) << 2;
634 /* NOTE: The branch occurs AFTER the next instruction has been
636 if ((signed_word) GPR[RS] > 0)
637 DELAY_SLOT (NIA + offset);
639 NULLIFY_NEXT_INSTRUCTION ();
644 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
645 "blez r<RS>, <OFFSET>"
646 *mipsI,mipsII,mipsIII,mipsIV:
648 // start-sanitize-vr4320
650 // end-sanitize-vr4320
651 // start-sanitize-vr5400
653 // end-sanitize-vr5400
654 // start-sanitize-r5900
656 // end-sanitize-r5900
658 // start-sanitize-tx19
662 address_word offset = EXTEND16 (OFFSET) << 2;
663 /* NOTE: The branch occurs AFTER the next instruction has been
665 if ((signed_word) GPR[RS] <= 0)
666 DELAY_SLOT (NIA + offset);
671 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
672 "bgezl r<RS>, <OFFSET>"
677 // start-sanitize-vr4320
679 // end-sanitize-vr4320
680 // start-sanitize-vr5400
682 // end-sanitize-vr5400
683 // start-sanitize-r5900
685 // end-sanitize-r5900
687 // start-sanitize-tx19
691 address_word offset = EXTEND16 (OFFSET) << 2;
692 if ((signed_word) GPR[RS] <= 0)
693 DELAY_SLOT (NIA + offset);
695 NULLIFY_NEXT_INSTRUCTION ();
700 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
701 "bltz r<RS>, <OFFSET>"
702 *mipsI,mipsII,mipsIII,mipsIV:
704 // start-sanitize-vr4320
706 // end-sanitize-vr4320
707 // start-sanitize-vr5400
709 // end-sanitize-vr5400
710 // start-sanitize-r5900
712 // end-sanitize-r5900
714 // start-sanitize-tx19
718 address_word offset = EXTEND16 (OFFSET) << 2;
719 if ((signed_word) GPR[RS] < 0)
720 DELAY_SLOT (NIA + offset);
725 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
726 "bltzal r<RS>, <OFFSET>"
727 *mipsI,mipsII,mipsIII,mipsIV:
729 // start-sanitize-vr4320
731 // end-sanitize-vr4320
732 // start-sanitize-vr5400
734 // end-sanitize-vr5400
735 // start-sanitize-r5900
737 // end-sanitize-r5900
739 // start-sanitize-tx19
743 address_word offset = EXTEND16 (OFFSET) << 2;
745 /* NOTE: The branch occurs AFTER the next instruction has been
747 if ((signed_word) GPR[RS] < 0)
748 DELAY_SLOT (NIA + offset);
753 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
754 "bltzall r<RS>, <OFFSET>"
759 // start-sanitize-vr4320
761 // end-sanitize-vr4320
762 // start-sanitize-vr5400
764 // end-sanitize-vr5400
765 // start-sanitize-r5900
767 // end-sanitize-r5900
769 // start-sanitize-tx19
773 address_word offset = EXTEND16 (OFFSET) << 2;
775 if ((signed_word) GPR[RS] < 0)
776 DELAY_SLOT (NIA + offset);
778 NULLIFY_NEXT_INSTRUCTION ();
783 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
784 "bltzl r<RS>, <OFFSET>"
789 // start-sanitize-vr4320
791 // end-sanitize-vr4320
792 // start-sanitize-vr5400
794 // end-sanitize-vr5400
795 // start-sanitize-r5900
797 // end-sanitize-r5900
799 // start-sanitize-tx19
803 address_word offset = EXTEND16 (OFFSET) << 2;
804 /* NOTE: The branch occurs AFTER the next instruction has been
806 if ((signed_word) GPR[RS] < 0)
807 DELAY_SLOT (NIA + offset);
809 NULLIFY_NEXT_INSTRUCTION ();
814 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
815 "bne r<RS>, r<RT>, <OFFSET>"
816 *mipsI,mipsII,mipsIII,mipsIV:
818 // start-sanitize-vr4320
820 // end-sanitize-vr4320
821 // start-sanitize-vr5400
823 // end-sanitize-vr5400
824 // start-sanitize-r5900
826 // end-sanitize-r5900
828 // start-sanitize-tx19
832 address_word offset = EXTEND16 (OFFSET) << 2;
833 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
834 DELAY_SLOT (NIA + offset);
839 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
840 "bnel r<RS>, r<RT>, <OFFSET>"
845 // start-sanitize-vr4320
847 // end-sanitize-vr4320
848 // start-sanitize-vr5400
850 // end-sanitize-vr5400
851 // start-sanitize-r5900
853 // end-sanitize-r5900
855 // start-sanitize-tx19
859 address_word offset = EXTEND16 (OFFSET) << 2;
860 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
861 DELAY_SLOT (NIA + offset);
863 NULLIFY_NEXT_INSTRUCTION ();
868 000000,20.CODE,001101:SPECIAL:32::BREAK
870 *mipsI,mipsII,mipsIII,mipsIV:
872 // start-sanitize-vr4320
874 // end-sanitize-vr4320
875 // start-sanitize-vr5400
877 // end-sanitize-vr5400
878 // start-sanitize-r5900
880 // end-sanitize-r5900
882 // start-sanitize-tx19
886 SignalException(BreakPoint, instruction_0);
891 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
893 *mipsI,mipsII,mipsIII,mipsIV:
894 // start-sanitize-r5900
896 // end-sanitize-r5900
898 // start-sanitize-tx19
902 DecodeCoproc (instruction_0);
907 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
908 "dadd r<RD>, r<RS>, r<RT>"
912 // start-sanitize-vr4320
914 // end-sanitize-vr4320
915 // start-sanitize-vr5400
917 // end-sanitize-vr5400
918 // start-sanitize-r5900
920 // end-sanitize-r5900
921 // start-sanitize-tx19
925 /* this check's for overflow */
926 ALU64_BEGIN (GPR[RS]);
933 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
934 "daddi r<RT>, r<RS>, <IMMEDIATE>"
938 // start-sanitize-vr4320
940 // end-sanitize-vr4320
941 // start-sanitize-vr5400
943 // end-sanitize-vr5400
944 // start-sanitize-r5900
946 // end-sanitize-r5900
947 // start-sanitize-tx19
951 ALU64_BEGIN (GPR[RS]);
952 ALU64_ADD (EXTEND16 (IMMEDIATE));
958 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
960 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
961 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
962 TRACE_ALU_RESULT (GPR[rt]);
965 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
966 "daddu r<RT>, r<RS>, <IMMEDIATE>"
970 // start-sanitize-vr4320
972 // end-sanitize-vr4320
973 // start-sanitize-vr5400
975 // end-sanitize-vr5400
976 // start-sanitize-r5900
978 // end-sanitize-r5900
979 // start-sanitize-tx19
983 do_daddiu (SD_, RS, RT, IMMEDIATE);
988 :function:::void:do_daddu:int rs, int rt, int rd
990 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
991 GPR[rd] = GPR[rs] + GPR[rt];
992 TRACE_ALU_RESULT (GPR[rd]);
995 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
996 "daddu r<RD>, r<RS>, r<RT>"
1000 // start-sanitize-vr4320
1002 // end-sanitize-vr4320
1003 // start-sanitize-vr5400
1005 // end-sanitize-vr5400
1006 // start-sanitize-r5900
1008 // end-sanitize-r5900
1009 // start-sanitize-tx19
1011 // end-sanitize-tx19
1013 do_daddu (SD_, RS, RT, RD);
1018 :function:64::void:do_ddiv:int rs, int rt
1020 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1021 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1023 signed64 n = GPR[rs];
1024 signed64 d = GPR[rt];
1027 LO = SIGNED64 (0x8000000000000000);
1030 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1032 LO = SIGNED64 (0x8000000000000000);
1041 TRACE_ALU_RESULT2 (HI, LO);
1044 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1049 // start-sanitize-vr4320
1051 // end-sanitize-vr4320
1052 // start-sanitize-vr5400
1054 // end-sanitize-vr5400
1055 // start-sanitize-r5900
1057 // end-sanitize-r5900
1058 // start-sanitize-tx19
1060 // end-sanitize-tx19
1062 do_ddiv (SD_, RS, RT);
1067 :function:64::void:do_ddivu:int rs, int rt
1069 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1070 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1072 unsigned64 n = GPR[rs];
1073 unsigned64 d = GPR[rt];
1076 LO = SIGNED64 (0x8000000000000000);
1085 TRACE_ALU_RESULT2 (HI, LO);
1088 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1089 "ddivu r<RS>, r<RT>"
1093 // start-sanitize-vr4320
1095 // end-sanitize-vr4320
1096 // start-sanitize-vr5400
1098 // end-sanitize-vr5400
1099 // start-sanitize-tx19
1101 // end-sanitize-tx19
1103 do_ddivu (SD_, RS, RT);
1108 :function:::void:do_div:int rs, int rt
1110 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1111 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1113 signed32 n = GPR[rs];
1114 signed32 d = GPR[rt];
1117 LO = EXTEND32 (0x80000000);
1120 else if (n == SIGNED32 (0x80000000) && d == -1)
1122 LO = EXTEND32 (0x80000000);
1127 LO = EXTEND32 (n / d);
1128 HI = EXTEND32 (n % d);
1131 TRACE_ALU_RESULT2 (HI, LO);
1134 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1136 *mipsI,mipsII,mipsIII,mipsIV:
1138 // start-sanitize-vr4320
1140 // end-sanitize-vr4320
1141 // start-sanitize-vr5400
1143 // end-sanitize-vr5400
1144 // start-sanitize-r5900
1146 // end-sanitize-r5900
1148 // start-sanitize-tx19
1150 // end-sanitize-tx19
1152 do_div (SD_, RS, RT);
1157 :function:::void:do_divu:int rs, int rt
1159 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1160 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1162 unsigned32 n = GPR[rs];
1163 unsigned32 d = GPR[rt];
1166 LO = EXTEND32 (0x80000000);
1171 LO = EXTEND32 (n / d);
1172 HI = EXTEND32 (n % d);
1175 TRACE_ALU_RESULT2 (HI, LO);
1178 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1180 *mipsI,mipsII,mipsIII,mipsIV:
1182 // start-sanitize-vr4320
1184 // end-sanitize-vr4320
1185 // start-sanitize-vr5400
1187 // end-sanitize-vr5400
1188 // start-sanitize-r5900
1190 // end-sanitize-r5900
1192 // start-sanitize-tx19
1194 // end-sanitize-tx19
1196 do_divu (SD_, RS, RT);
1201 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1211 unsigned64 op1 = GPR[rs];
1212 unsigned64 op2 = GPR[rt];
1213 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1214 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1215 /* make signed multiply unsigned */
1230 /* multuply out the 4 sub products */
1231 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1232 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1233 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1234 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1235 /* add the products */
1236 mid = ((unsigned64) VH4_8 (m00)
1237 + (unsigned64) VL4_8 (m10)
1238 + (unsigned64) VL4_8 (m01));
1239 lo = U8_4 (mid, m00);
1241 + (unsigned64) VH4_8 (mid)
1242 + (unsigned64) VH4_8 (m01)
1243 + (unsigned64) VH4_8 (m10));
1253 /* save the result HI/LO (and a gpr) */
1258 TRACE_ALU_RESULT2 (HI, LO);
1261 :function:::void:do_dmult:int rs, int rt, int rd
1263 do_dmultx (SD_, rs, rt, rd, 1);
1266 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1267 "dmult r<RS>, r<RT>"
1269 // start-sanitize-tx19
1271 // end-sanitize-tx19
1272 // start-sanitize-vr4320
1274 // end-sanitize-vr4320
1276 do_dmult (SD_, RS, RT, 0);
1279 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1280 "dmult r<RS>, r<RT>":RD == 0
1281 "dmult r<RD>, r<RS>, r<RT>"
1283 // start-sanitize-vr5400
1285 // end-sanitize-vr5400
1287 do_dmult (SD_, RS, RT, RD);
1292 :function:::void:do_dmultu:int rs, int rt, int rd
1294 do_dmultx (SD_, rs, rt, rd, 0);
1297 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1298 "dmultu r<RS>, r<RT>"
1300 // start-sanitize-tx19
1302 // end-sanitize-tx19
1303 // start-sanitize-vr4320
1305 // end-sanitize-vr4320
1307 do_dmultu (SD_, RS, RT, 0);
1310 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1311 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1312 "dmultu r<RS>, r<RT>"
1314 // start-sanitize-vr5400
1316 // end-sanitize-vr5400
1318 do_dmultu (SD_, RS, RT, RD);
1323 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1324 "dsll r<RD>, r<RT>, <SHIFT>"
1328 // start-sanitize-vr4320
1330 // end-sanitize-vr4320
1331 // start-sanitize-vr5400
1333 // end-sanitize-vr5400
1334 // start-sanitize-r5900
1336 // end-sanitize-r5900
1337 // start-sanitize-tx19
1339 // end-sanitize-tx19
1342 GPR[RD] = GPR[RT] << s;
1346 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1347 "dsll32 r<RD>, r<RT>, <SHIFT>"
1351 // start-sanitize-vr4320
1353 // end-sanitize-vr4320
1354 // start-sanitize-vr5400
1356 // end-sanitize-vr5400
1357 // start-sanitize-r5900
1359 // end-sanitize-r5900
1360 // start-sanitize-tx19
1362 // end-sanitize-tx19
1365 GPR[RD] = GPR[RT] << s;
1370 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1371 "dsllv r<RD>, r<RT>, r<RS>"
1375 // start-sanitize-vr4320
1377 // end-sanitize-vr4320
1378 // start-sanitize-vr5400
1380 // end-sanitize-vr5400
1381 // start-sanitize-r5900
1383 // end-sanitize-r5900
1384 // start-sanitize-tx19
1386 // end-sanitize-tx19
1388 int s = MASKED64 (GPR[RS], 5, 0);
1389 GPR[RD] = GPR[RT] << s;
1394 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1395 "dsra r<RD>, r<RT>, <SHIFT>"
1399 // start-sanitize-vr4320
1401 // end-sanitize-vr4320
1402 // start-sanitize-vr5400
1404 // end-sanitize-vr5400
1405 // start-sanitize-r5900
1407 // end-sanitize-r5900
1408 // start-sanitize-tx19
1410 // end-sanitize-tx19
1413 GPR[RD] = ((signed64) GPR[RT]) >> s;
1417 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1418 "dsra32 r<RT>, r<RD>, <SHIFT>"
1422 // start-sanitize-vr4320
1424 // end-sanitize-vr4320
1425 // start-sanitize-vr5400
1427 // end-sanitize-vr5400
1428 // start-sanitize-r5900
1430 // end-sanitize-r5900
1431 // start-sanitize-tx19
1433 // end-sanitize-tx19
1436 GPR[RD] = ((signed64) GPR[RT]) >> s;
1440 :function:::void:do_dsrav:int rs, int rt, int rd
1442 int s = MASKED64 (GPR[rs], 5, 0);
1443 TRACE_ALU_INPUT2 (GPR[rt], s);
1444 GPR[rd] = ((signed64) GPR[rt]) >> s;
1445 TRACE_ALU_RESULT (GPR[rd]);
1448 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1449 "dsra32 r<RT>, r<RD>, r<RS>"
1453 // start-sanitize-vr4320
1455 // end-sanitize-vr4320
1456 // start-sanitize-vr5400
1458 // end-sanitize-vr5400
1459 // start-sanitize-r5900
1461 // end-sanitize-r5900
1462 // start-sanitize-tx19
1464 // end-sanitize-tx19
1466 do_dsrav (SD_, RS, RT, RD);
1470 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1471 "dsrl r<RD>, r<RT>, <SHIFT>"
1475 // start-sanitize-vr4320
1477 // end-sanitize-vr4320
1478 // start-sanitize-vr5400
1480 // end-sanitize-vr5400
1481 // start-sanitize-r5900
1483 // end-sanitize-r5900
1484 // start-sanitize-tx19
1486 // end-sanitize-tx19
1489 GPR[RD] = (unsigned64) GPR[RT] >> s;
1493 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1494 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1498 // start-sanitize-vr4320
1500 // end-sanitize-vr4320
1501 // start-sanitize-vr5400
1503 // end-sanitize-vr5400
1504 // start-sanitize-r5900
1506 // end-sanitize-r5900
1507 // start-sanitize-tx19
1509 // end-sanitize-tx19
1512 GPR[RD] = (unsigned64) GPR[RT] >> s;
1516 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1517 "dsrl32 r<RD>, r<RT>, r<RS>"
1521 // start-sanitize-vr4320
1523 // end-sanitize-vr4320
1524 // start-sanitize-vr5400
1526 // end-sanitize-vr5400
1527 // start-sanitize-r5900
1529 // end-sanitize-r5900
1530 // start-sanitize-tx19
1532 // end-sanitize-tx19
1534 int s = MASKED64 (GPR[RS], 5, 0);
1535 GPR[RD] = (unsigned64) GPR[RT] >> s;
1539 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1540 "dsub r<RD>, r<RS>, r<RT>"
1544 // start-sanitize-vr4320
1546 // end-sanitize-vr4320
1547 // start-sanitize-vr5400
1549 // end-sanitize-vr5400
1550 // start-sanitize-r5900
1552 // end-sanitize-r5900
1553 // start-sanitize-tx19
1555 // end-sanitize-tx19
1557 ALU64_BEGIN (GPR[RS]);
1558 ALU64_SUB (GPR[RT]);
1559 ALU64_END (GPR[RD]);
1563 :function:::void:do_dsubu:int rs, int rt, int rd
1565 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1566 GPR[rd] = GPR[rs] - GPR[rt];
1567 TRACE_ALU_RESULT (GPR[rd]);
1570 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1571 "dsubu r<RD>, r<RS>, r<RT>"
1575 // start-sanitize-vr4320
1577 // end-sanitize-vr4320
1578 // start-sanitize-vr5400
1580 // end-sanitize-vr5400
1581 // start-sanitize-r5900
1583 // end-sanitize-r5900
1584 // start-sanitize-tx19
1586 // end-sanitize-tx19
1588 do_dsubu (SD_, RS, RT, RD);
1592 000010,26.INSTR_INDEX:NORMAL:32::J
1594 *mipsI,mipsII,mipsIII,mipsIV:
1596 // start-sanitize-vr4320
1598 // end-sanitize-vr4320
1599 // start-sanitize-vr5400
1601 // end-sanitize-vr5400
1602 // start-sanitize-r5900
1604 // end-sanitize-r5900
1606 // start-sanitize-tx19
1608 // end-sanitize-tx19
1610 /* NOTE: The region used is that of the delay slot NIA and NOT the
1611 current instruction */
1612 address_word region = (NIA & MASK (63, 28));
1613 DELAY_SLOT (region | (INSTR_INDEX << 2));
1617 000011,26.INSTR_INDEX:NORMAL:32::JAL
1619 *mipsI,mipsII,mipsIII,mipsIV:
1621 // start-sanitize-vr4320
1623 // end-sanitize-vr4320
1624 // start-sanitize-vr5400
1626 // end-sanitize-vr5400
1627 // start-sanitize-r5900
1629 // end-sanitize-r5900
1631 // start-sanitize-tx19
1633 // end-sanitize-tx19
1635 /* NOTE: The region used is that of the delay slot and NOT the
1636 current instruction */
1637 address_word region = (NIA & MASK (63, 28));
1639 DELAY_SLOT (region | (INSTR_INDEX << 2));
1643 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1644 "jalr r<RS>":RD == 31
1646 *mipsI,mipsII,mipsIII,mipsIV:
1648 // start-sanitize-vr4320
1650 // end-sanitize-vr4320
1651 // start-sanitize-vr5400
1653 // end-sanitize-vr5400
1654 // start-sanitize-r5900
1656 // end-sanitize-r5900
1658 // start-sanitize-tx19
1660 // end-sanitize-tx19
1662 address_word temp = GPR[RS];
1668 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1670 *mipsI,mipsII,mipsIII,mipsIV:
1672 // start-sanitize-vr4320
1674 // end-sanitize-vr4320
1675 // start-sanitize-vr5400
1677 // end-sanitize-vr5400
1678 // start-sanitize-r5900
1680 // end-sanitize-r5900
1682 // start-sanitize-tx19
1684 // end-sanitize-tx19
1686 DELAY_SLOT (GPR[RS]);
1690 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1692 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1693 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1694 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1701 vaddr = base + offset;
1702 if ((vaddr & access) != 0)
1703 SignalExceptionAddressLoad ();
1704 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1705 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1706 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1707 byte = ((vaddr & mask) ^ bigendiancpu);
1708 return (memval >> (8 * byte));
1712 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1713 "lb r<RT>, <OFFSET>(r<BASE>)"
1714 *mipsI,mipsII,mipsIII,mipsIV:
1716 // start-sanitize-vr4320
1718 // end-sanitize-vr4320
1719 // start-sanitize-vr5400
1721 // end-sanitize-vr5400
1722 // start-sanitize-r5900
1724 // end-sanitize-r5900
1726 // start-sanitize-tx19
1728 // end-sanitize-tx19
1730 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1734 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1735 "lbu r<RT>, <OFFSET>(r<BASE>)"
1736 *mipsI,mipsII,mipsIII,mipsIV:
1738 // start-sanitize-vr4320
1740 // end-sanitize-vr4320
1741 // start-sanitize-vr5400
1743 // end-sanitize-vr5400
1744 // start-sanitize-r5900
1746 // end-sanitize-r5900
1748 // start-sanitize-tx19
1750 // end-sanitize-tx19
1752 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1756 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1757 "ld r<RT>, <OFFSET>(r<BASE>)"
1761 // start-sanitize-vr4320
1763 // end-sanitize-vr4320
1764 // start-sanitize-vr5400
1766 // end-sanitize-vr5400
1767 // start-sanitize-r5900
1769 // end-sanitize-r5900
1770 // start-sanitize-tx19
1772 // end-sanitize-tx19
1774 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1778 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1779 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1784 // start-sanitize-vr4320
1786 // end-sanitize-vr4320
1787 // start-sanitize-vr5400
1789 // end-sanitize-vr5400
1791 // start-sanitize-tx19
1793 // end-sanitize-tx19
1795 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1801 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1802 "ldl r<RT>, <OFFSET>(r<BASE>)"
1806 // start-sanitize-vr4320
1808 // end-sanitize-vr4320
1809 // start-sanitize-vr5400
1811 // end-sanitize-vr5400
1812 // start-sanitize-r5900
1814 // end-sanitize-r5900
1815 // start-sanitize-tx19
1817 // end-sanitize-tx19
1819 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1823 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1824 "ldr r<RT>, <OFFSET>(r<BASE>)"
1828 // start-sanitize-vr4320
1830 // end-sanitize-vr4320
1831 // start-sanitize-vr5400
1833 // end-sanitize-vr5400
1834 // start-sanitize-r5900
1836 // end-sanitize-r5900
1837 // start-sanitize-tx19
1839 // end-sanitize-tx19
1841 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1845 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1846 "lh r<RT>, <OFFSET>(r<BASE>)"
1847 *mipsI,mipsII,mipsIII,mipsIV:
1849 // start-sanitize-vr4320
1851 // end-sanitize-vr4320
1852 // start-sanitize-vr5400
1854 // end-sanitize-vr5400
1855 // start-sanitize-r5900
1857 // end-sanitize-r5900
1859 // start-sanitize-tx19
1861 // end-sanitize-tx19
1863 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1867 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1868 "lhu r<RT>, <OFFSET>(r<BASE>)"
1869 *mipsI,mipsII,mipsIII,mipsIV:
1871 // start-sanitize-vr4320
1873 // end-sanitize-vr4320
1874 // start-sanitize-vr5400
1876 // end-sanitize-vr5400
1877 // start-sanitize-r5900
1879 // end-sanitize-r5900
1881 // start-sanitize-tx19
1883 // end-sanitize-tx19
1885 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1889 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1890 "ll r<RT>, <OFFSET>(r<BASE>)"
1895 // start-sanitize-vr4320
1897 // end-sanitize-vr4320
1898 // start-sanitize-vr5400
1900 // end-sanitize-vr5400
1901 // start-sanitize-r5900
1903 // end-sanitize-r5900
1904 // start-sanitize-tx19
1906 // end-sanitize-tx19
1908 unsigned32 instruction = instruction_0;
1909 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1910 int destreg = ((instruction >> 16) & 0x0000001F);
1911 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1913 address_word vaddr = ((unsigned64)op1 + offset);
1916 if ((vaddr & 3) != 0)
1917 SignalExceptionAddressLoad();
1920 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1922 unsigned64 memval = 0;
1923 unsigned64 memval1 = 0;
1924 unsigned64 mask = 0x7;
1925 unsigned int shift = 2;
1926 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1927 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1929 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1930 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1931 byte = ((vaddr & mask) ^ (bigend << shift));
1932 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1940 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1941 "lld r<RT>, <OFFSET>(r<BASE>)"
1945 // start-sanitize-vr4320
1947 // end-sanitize-vr4320
1948 // start-sanitize-vr5400
1950 // end-sanitize-vr5400
1951 // start-sanitize-r5900
1953 // end-sanitize-r5900
1954 // start-sanitize-tx19
1956 // end-sanitize-tx19
1958 unsigned32 instruction = instruction_0;
1959 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1960 int destreg = ((instruction >> 16) & 0x0000001F);
1961 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1963 address_word vaddr = ((unsigned64)op1 + offset);
1966 if ((vaddr & 7) != 0)
1967 SignalExceptionAddressLoad();
1970 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1972 unsigned64 memval = 0;
1973 unsigned64 memval1 = 0;
1974 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1975 GPR[destreg] = memval;
1983 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1984 "lui r<RT>, <IMMEDIATE>"
1985 *mipsI,mipsII,mipsIII,mipsIV:
1987 // start-sanitize-vr4320
1989 // end-sanitize-vr4320
1990 // start-sanitize-vr5400
1992 // end-sanitize-vr5400
1993 // start-sanitize-r5900
1995 // end-sanitize-r5900
1997 // start-sanitize-tx19
1999 // end-sanitize-tx19
2001 TRACE_ALU_INPUT1 (IMMEDIATE);
2002 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2003 TRACE_ALU_RESULT (GPR[RT]);
2007 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2008 "lw r<RT>, <OFFSET>(r<BASE>)"
2009 *mipsI,mipsII,mipsIII,mipsIV:
2011 // start-sanitize-vr4320
2013 // end-sanitize-vr4320
2014 // start-sanitize-vr5400
2016 // end-sanitize-vr5400
2017 // start-sanitize-r5900
2019 // end-sanitize-r5900
2021 // start-sanitize-tx19
2023 // end-sanitize-tx19
2025 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2029 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2030 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2031 *mipsI,mipsII,mipsIII,mipsIV:
2033 // start-sanitize-vr4320
2035 // end-sanitize-vr4320
2036 // start-sanitize-vr5400
2038 // end-sanitize-vr5400
2039 // start-sanitize-r5900
2041 // end-sanitize-r5900
2043 // start-sanitize-tx19
2045 // end-sanitize-tx19
2047 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2051 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2053 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2054 address_word reverseendian = (ReverseEndian ? -1 : 0);
2055 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2062 vaddr = base + offset;
2063 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2064 paddr = (paddr ^ (reverseendian & mask));
2065 if (BigEndianMem == 0)
2066 paddr = paddr & ~access;
2067 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2068 LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
2069 /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
2070 (long) vaddr, byte, (long) paddr, (long) memval); */
2071 if ((byte & ~access) == 0)
2073 int bits = 8 * (access - byte);
2074 unsigned_word screen = LSMASK (bits - 1, 0);
2076 rt |= ((memval << bits) & ~screen);
2080 unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
2082 rt |= ((memval >> (8 * (mask - byte))) & ~screen);
2088 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2089 "lwl r<RT>, <OFFSET>(r<BASE>)"
2090 *mipsI,mipsII,mipsIII,mipsIV:
2092 // start-sanitize-vr4320
2094 // end-sanitize-vr4320
2095 // start-sanitize-vr5400
2097 // end-sanitize-vr5400
2098 // start-sanitize-r5900
2100 // end-sanitize-r5900
2102 // start-sanitize-tx19
2104 // end-sanitize-tx19
2106 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2110 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2112 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2113 address_word reverseendian = (ReverseEndian ? -1 : 0);
2114 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2121 vaddr = base + offset;
2122 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2123 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2124 paddr = (paddr ^ (reverseendian & mask));
2125 if (BigEndianMem != 0)
2126 paddr = paddr & ~access;
2127 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2128 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2129 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2130 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2131 (long) paddr, byte, (long) paddr, (long) memval); */
2133 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2135 rt |= (memval >> (8 * byte)) & screen;
2141 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2142 "lwr r<RT>, <OFFSET>(r<BASE>)"
2143 *mipsI,mipsII,mipsIII,mipsIV:
2145 // start-sanitize-vr4320
2147 // end-sanitize-vr4320
2148 // start-sanitize-vr5400
2150 // end-sanitize-vr5400
2151 // start-sanitize-r5900
2153 // end-sanitize-r5900
2155 // start-sanitize-tx19
2157 // end-sanitize-tx19
2159 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2163 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2164 "lwu r<RT>, <OFFSET>(r<BASE>)"
2168 // start-sanitize-vr4320
2170 // end-sanitize-vr4320
2171 // start-sanitize-vr5400
2173 // end-sanitize-vr5400
2174 // start-sanitize-r5900
2176 // end-sanitize-r5900
2177 // start-sanitize-tx19
2179 // end-sanitize-tx19
2181 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2185 :function:::void:do_mfhi:int rd
2187 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2188 TRACE_ALU_INPUT1 (HI);
2190 TRACE_ALU_RESULT (GPR[rd]);
2193 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2195 *mipsI,mipsII,mipsIII,mipsIV:
2197 // start-sanitize-vr4320
2199 // end-sanitize-vr4320
2200 // start-sanitize-vr5400
2202 // end-sanitize-vr5400
2203 // start-sanitize-r5900
2205 // end-sanitize-r5900
2207 // start-sanitize-tx19
2209 // end-sanitize-tx19
2216 :function:::void:do_mflo:int rd
2218 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2219 TRACE_ALU_INPUT1 (LO);
2221 TRACE_ALU_RESULT (GPR[rd]);
2224 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2226 *mipsI,mipsII,mipsIII,mipsIV:
2228 // start-sanitize-vr4320
2230 // end-sanitize-vr4320
2231 // start-sanitize-vr5400
2233 // end-sanitize-vr5400
2234 // start-sanitize-r5900
2236 // end-sanitize-r5900
2238 // start-sanitize-tx19
2240 // end-sanitize-tx19
2247 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2248 "movn r<RD>, r<RS>, r<RT>"
2251 // start-sanitize-vr4320
2253 // end-sanitize-vr4320
2254 // start-sanitize-vr5400
2256 // end-sanitize-vr5400
2257 // start-sanitize-r5900
2259 // end-sanitize-r5900
2267 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2268 "movz r<RD>, r<RS>, r<RT>"
2271 // start-sanitize-vr4320
2273 // end-sanitize-vr4320
2274 // start-sanitize-vr5400
2276 // end-sanitize-vr5400
2277 // start-sanitize-r5900
2279 // end-sanitize-r5900
2287 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2289 *mipsI,mipsII,mipsIII,mipsIV:
2291 // start-sanitize-vr4320
2293 // end-sanitize-vr4320
2294 // start-sanitize-vr5400
2296 // end-sanitize-vr5400
2297 // start-sanitize-r5900
2299 // end-sanitize-r5900
2301 // start-sanitize-tx19
2303 // end-sanitize-tx19
2305 check_mt_hilo (SD_, HIHISTORY);
2311 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2313 *mipsI,mipsII,mipsIII,mipsIV:
2315 // start-sanitize-vr4320
2317 // end-sanitize-vr4320
2318 // start-sanitize-vr5400
2320 // end-sanitize-vr5400
2321 // start-sanitize-r5900
2323 // end-sanitize-r5900
2325 // start-sanitize-tx19
2327 // end-sanitize-tx19
2329 check_mt_hilo (SD_, LOHISTORY);
2335 :function:::void:do_mult:int rs, int rt, int rd
2338 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2339 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2340 prod = (((signed64)(signed32) GPR[rs])
2341 * ((signed64)(signed32) GPR[rt]));
2342 LO = EXTEND32 (VL4_8 (prod));
2343 HI = EXTEND32 (VH4_8 (prod));
2346 TRACE_ALU_RESULT2 (HI, LO);
2349 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2351 *mipsI,mipsII,mipsIII,mipsIV:
2352 // start-sanitize-vr4320
2354 // end-sanitize-vr4320
2356 do_mult (SD_, RS, RT, 0);
2360 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2361 "mult r<RD>, r<RS>, r<RT>"
2363 // start-sanitize-vr5400
2365 // end-sanitize-vr5400
2366 // start-sanitize-r5900
2368 // end-sanitize-r5900
2370 // start-sanitize-tx19
2372 // end-sanitize-tx19
2374 do_mult (SD_, RS, RT, RD);
2378 :function:::void:do_multu:int rs, int rt, int rd
2381 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2382 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2383 prod = (((unsigned64)(unsigned32) GPR[rs])
2384 * ((unsigned64)(unsigned32) GPR[rt]));
2385 LO = EXTEND32 (VL4_8 (prod));
2386 HI = EXTEND32 (VH4_8 (prod));
2389 TRACE_ALU_RESULT2 (HI, LO);
2392 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2393 "multu r<RS>, r<RT>"
2394 *mipsI,mipsII,mipsIII,mipsIV:
2395 // start-sanitize-vr4320
2397 // end-sanitize-vr4320
2399 do_multu (SD_, RS, RT, 0);
2402 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2403 "multu r<RD>, r<RS>, r<RT>"
2405 // start-sanitize-vr5400
2407 // end-sanitize-vr5400
2408 // start-sanitize-r5900
2410 // end-sanitize-r5900
2412 // start-sanitize-tx19
2414 // end-sanitize-tx19
2416 do_multu (SD_, RS, RT, 0);
2420 :function:::void:do_nor:int rs, int rt, int rd
2422 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2423 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2424 TRACE_ALU_RESULT (GPR[rd]);
2427 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2428 "nor r<RD>, r<RS>, r<RT>"
2429 *mipsI,mipsII,mipsIII,mipsIV:
2431 // start-sanitize-vr4320
2433 // end-sanitize-vr4320
2434 // start-sanitize-vr5400
2436 // end-sanitize-vr5400
2437 // start-sanitize-r5900
2439 // end-sanitize-r5900
2441 // start-sanitize-tx19
2443 // end-sanitize-tx19
2445 do_nor (SD_, RS, RT, RD);
2449 :function:::void:do_or:int rs, int rt, int rd
2451 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2452 GPR[rd] = (GPR[rs] | GPR[rt]);
2453 TRACE_ALU_RESULT (GPR[rd]);
2456 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2457 "or r<RD>, r<RS>, r<RT>"
2458 *mipsI,mipsII,mipsIII,mipsIV:
2460 // start-sanitize-vr4320
2462 // end-sanitize-vr4320
2463 // start-sanitize-vr5400
2465 // end-sanitize-vr5400
2466 // start-sanitize-r5900
2468 // end-sanitize-r5900
2470 // start-sanitize-tx19
2472 // end-sanitize-tx19
2474 do_or (SD_, RS, RT, RD);
2479 :function:::void:do_ori:int rs, int rt, unsigned immediate
2481 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2482 GPR[rt] = (GPR[rs] | immediate);
2483 TRACE_ALU_RESULT (GPR[rt]);
2486 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2487 "ori r<RT>, r<RS>, <IMMEDIATE>"
2488 *mipsI,mipsII,mipsIII,mipsIV:
2490 // start-sanitize-vr4320
2492 // end-sanitize-vr4320
2493 // start-sanitize-vr5400
2495 // end-sanitize-vr5400
2496 // start-sanitize-r5900
2498 // end-sanitize-r5900
2500 // start-sanitize-tx19
2502 // end-sanitize-tx19
2504 do_ori (SD_, RS, RT, IMMEDIATE);
2508 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2511 // start-sanitize-vr4320
2513 // end-sanitize-vr4320
2514 // start-sanitize-vr5400
2516 // end-sanitize-vr5400
2517 // start-sanitize-r5900
2519 // end-sanitize-r5900
2521 unsigned32 instruction = instruction_0;
2522 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2523 int hint = ((instruction >> 16) & 0x0000001F);
2524 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2526 address_word vaddr = ((unsigned64)op1 + offset);
2530 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2531 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2536 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2538 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2539 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2540 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2547 vaddr = base + offset;
2548 if ((vaddr & access) != 0)
2549 SignalExceptionAddressStore ();
2550 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2551 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2552 byte = ((vaddr & mask) ^ bigendiancpu);
2553 memval = (word << (8 * byte));
2554 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2558 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2559 "sb r<RT>, <OFFSET>(r<BASE>)"
2560 *mipsI,mipsII,mipsIII,mipsIV:
2562 // start-sanitize-vr4320
2564 // end-sanitize-vr4320
2565 // start-sanitize-vr5400
2567 // end-sanitize-vr5400
2568 // start-sanitize-r5900
2570 // end-sanitize-r5900
2572 // start-sanitize-tx19
2574 // end-sanitize-tx19
2576 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2580 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2581 "sc r<RT>, <OFFSET>(r<BASE>)"
2586 // start-sanitize-vr4320
2588 // end-sanitize-vr4320
2589 // start-sanitize-vr5400
2591 // end-sanitize-vr5400
2592 // start-sanitize-r5900
2594 // end-sanitize-r5900
2595 // start-sanitize-tx19
2597 // end-sanitize-tx19
2599 unsigned32 instruction = instruction_0;
2600 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2601 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2602 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2604 address_word vaddr = ((unsigned64)op1 + offset);
2607 if ((vaddr & 3) != 0)
2608 SignalExceptionAddressStore();
2611 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2613 unsigned64 memval = 0;
2614 unsigned64 memval1 = 0;
2615 unsigned64 mask = 0x7;
2617 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2618 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2619 memval = ((unsigned64) op2 << (8 * byte));
2622 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2624 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2631 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2632 "scd r<RT>, <OFFSET>(r<BASE>)"
2636 // start-sanitize-vr4320
2638 // end-sanitize-vr4320
2639 // start-sanitize-vr5400
2641 // end-sanitize-vr5400
2642 // start-sanitize-r5900
2644 // end-sanitize-r5900
2645 // start-sanitize-tx19
2647 // end-sanitize-tx19
2649 unsigned32 instruction = instruction_0;
2650 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2651 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2652 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2654 address_word vaddr = ((unsigned64)op1 + offset);
2657 if ((vaddr & 7) != 0)
2658 SignalExceptionAddressStore();
2661 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2663 unsigned64 memval = 0;
2664 unsigned64 memval1 = 0;
2668 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2670 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2677 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2678 "sd r<RT>, <OFFSET>(r<BASE>)"
2682 // start-sanitize-vr4320
2684 // end-sanitize-vr4320
2685 // start-sanitize-vr5400
2687 // end-sanitize-vr5400
2688 // start-sanitize-r5900
2690 // end-sanitize-r5900
2691 // start-sanitize-tx19
2693 // end-sanitize-tx19
2695 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2699 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2700 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2705 // start-sanitize-vr4320
2707 // end-sanitize-vr4320
2708 // start-sanitize-vr5400
2710 // end-sanitize-vr5400
2711 // start-sanitize-r5900
2713 // end-sanitize-r5900
2714 // start-sanitize-tx19
2716 // end-sanitize-tx19
2718 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2722 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2723 "sdl r<RT>, <OFFSET>(r<BASE>)"
2727 // start-sanitize-vr4320
2729 // end-sanitize-vr4320
2730 // start-sanitize-vr5400
2732 // end-sanitize-vr5400
2733 // start-sanitize-r5900
2735 // end-sanitize-r5900
2736 // start-sanitize-tx19
2738 // end-sanitize-tx19
2740 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2744 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2745 "sdr r<RT>, <OFFSET>(r<BASE>)"
2749 // start-sanitize-vr4320
2751 // end-sanitize-vr4320
2752 // start-sanitize-vr5400
2754 // end-sanitize-vr5400
2755 // start-sanitize-r5900
2757 // end-sanitize-r5900
2758 // start-sanitize-tx19
2760 // end-sanitize-tx19
2762 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2766 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2767 "sh r<RT>, <OFFSET>(r<BASE>)"
2768 *mipsI,mipsII,mipsIII,mipsIV:
2770 // start-sanitize-vr4320
2772 // end-sanitize-vr4320
2773 // start-sanitize-vr5400
2775 // end-sanitize-vr5400
2776 // start-sanitize-r5900
2778 // end-sanitize-r5900
2780 // start-sanitize-tx19
2782 // end-sanitize-tx19
2784 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2788 :function:::void:do_sll:int rt, int rd, int shift
2790 unsigned32 temp = (GPR[rt] << shift);
2791 TRACE_ALU_INPUT2 (GPR[rt], shift);
2792 GPR[rd] = EXTEND32 (temp);
2793 TRACE_ALU_RESULT (GPR[rd]);
2796 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2797 "sll r<RD>, r<RT>, <SHIFT>"
2798 *mipsI,mipsII,mipsIII,mipsIV:
2800 // start-sanitize-vr4320
2802 // end-sanitize-vr4320
2803 // start-sanitize-vr5400
2805 // end-sanitize-vr5400
2806 // start-sanitize-r5900
2808 // end-sanitize-r5900
2810 // start-sanitize-tx19
2812 // end-sanitize-tx19
2814 do_sll (SD_, RT, RD, SHIFT);
2818 :function:::void:do_sllv:int rs, int rt, int rd
2820 int s = MASKED (GPR[rs], 4, 0);
2821 unsigned32 temp = (GPR[rt] << s);
2822 TRACE_ALU_INPUT2 (GPR[rt], s);
2823 GPR[rd] = EXTEND32 (temp);
2824 TRACE_ALU_RESULT (GPR[rd]);
2827 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2828 "sllv r<RD>, r<RT>, r<RS>"
2829 *mipsI,mipsII,mipsIII,mipsIV:
2831 // start-sanitize-vr4320
2833 // end-sanitize-vr4320
2834 // start-sanitize-vr5400
2836 // end-sanitize-vr5400
2837 // start-sanitize-r5900
2839 // end-sanitize-r5900
2841 // start-sanitize-tx19
2843 // end-sanitize-tx19
2845 do_sllv (SD_, RS, RT, RD);
2849 :function:::void:do_slt:int rs, int rt, int rd
2851 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2852 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2853 TRACE_ALU_RESULT (GPR[rd]);
2856 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2857 "slt r<RD>, r<RS>, r<RT>"
2858 *mipsI,mipsII,mipsIII,mipsIV:
2860 // start-sanitize-vr4320
2862 // end-sanitize-vr4320
2863 // start-sanitize-vr5400
2865 // end-sanitize-vr5400
2866 // start-sanitize-r5900
2868 // end-sanitize-r5900
2870 // start-sanitize-tx19
2872 // end-sanitize-tx19
2874 do_slt (SD_, RS, RT, RD);
2878 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2880 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2881 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2882 TRACE_ALU_RESULT (GPR[rt]);
2885 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2886 "slti r<RT>, r<RS>, <IMMEDIATE>"
2887 *mipsI,mipsII,mipsIII,mipsIV:
2889 // start-sanitize-vr4320
2891 // end-sanitize-vr4320
2892 // start-sanitize-vr5400
2894 // end-sanitize-vr5400
2895 // start-sanitize-r5900
2897 // end-sanitize-r5900
2899 // start-sanitize-tx19
2901 // end-sanitize-tx19
2903 do_slti (SD_, RS, RT, IMMEDIATE);
2907 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2909 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2910 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2911 TRACE_ALU_RESULT (GPR[rt]);
2914 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2915 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2916 *mipsI,mipsII,mipsIII,mipsIV:
2918 // start-sanitize-vr4320
2920 // end-sanitize-vr4320
2921 // start-sanitize-vr5400
2923 // end-sanitize-vr5400
2924 // start-sanitize-r5900
2926 // end-sanitize-r5900
2928 // start-sanitize-tx19
2930 // end-sanitize-tx19
2932 do_sltiu (SD_, RS, RT, IMMEDIATE);
2937 :function:::void:do_sltu:int rs, int rt, int rd
2939 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2940 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2941 TRACE_ALU_RESULT (GPR[rd]);
2944 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2945 "sltu r<RD>, r<RS>, r<RT>"
2946 *mipsI,mipsII,mipsIII,mipsIV:
2948 // start-sanitize-vr4320
2950 // end-sanitize-vr4320
2951 // start-sanitize-vr5400
2953 // end-sanitize-vr5400
2954 // start-sanitize-r5900
2956 // end-sanitize-r5900
2958 // start-sanitize-tx19
2960 // end-sanitize-tx19
2962 do_sltu (SD_, RS, RT, RD);
2966 :function:::void:do_sra:int rt, int rd, int shift
2968 signed32 temp = (signed32) GPR[rt] >> shift;
2969 TRACE_ALU_INPUT2 (GPR[rt], shift);
2970 GPR[rd] = EXTEND32 (temp);
2971 TRACE_ALU_RESULT (GPR[rd]);
2974 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2975 "sra r<RD>, r<RT>, <SHIFT>"
2976 *mipsI,mipsII,mipsIII,mipsIV:
2978 // start-sanitize-vr4320
2980 // end-sanitize-vr4320
2981 // start-sanitize-vr5400
2983 // end-sanitize-vr5400
2984 // start-sanitize-r5900
2986 // end-sanitize-r5900
2988 // start-sanitize-tx19
2990 // end-sanitize-tx19
2992 do_sra (SD_, RT, RD, SHIFT);
2997 :function:::void:do_srav:int rs, int rt, int rd
2999 int s = MASKED (GPR[rs], 4, 0);
3000 signed32 temp = (signed32) GPR[rt] >> s;
3001 TRACE_ALU_INPUT2 (GPR[rt], s);
3002 GPR[rd] = EXTEND32 (temp);
3003 TRACE_ALU_RESULT (GPR[rd]);
3006 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3007 "srav r<RD>, r<RT>, r<RS>"
3008 *mipsI,mipsII,mipsIII,mipsIV:
3010 // start-sanitize-vr4320
3012 // end-sanitize-vr4320
3013 // start-sanitize-vr5400
3015 // end-sanitize-vr5400
3016 // start-sanitize-r5900
3018 // end-sanitize-r5900
3020 // start-sanitize-tx19
3022 // end-sanitize-tx19
3024 do_srav (SD_, RS, RT, RD);
3029 :function:::void:do_srl:int rt, int rd, int shift
3031 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3032 TRACE_ALU_INPUT2 (GPR[rt], shift);
3033 GPR[rd] = EXTEND32 (temp);
3034 TRACE_ALU_RESULT (GPR[rd]);
3037 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3038 "srl r<RD>, r<RT>, <SHIFT>"
3039 *mipsI,mipsII,mipsIII,mipsIV:
3041 // start-sanitize-vr4320
3043 // end-sanitize-vr4320
3044 // start-sanitize-vr5400
3046 // end-sanitize-vr5400
3047 // start-sanitize-r5900
3049 // end-sanitize-r5900
3051 // start-sanitize-tx19
3053 // end-sanitize-tx19
3055 do_srl (SD_, RT, RD, SHIFT);
3059 :function:::void:do_srlv:int rs, int rt, int rd
3061 int s = MASKED (GPR[rs], 4, 0);
3062 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3063 TRACE_ALU_INPUT2 (GPR[rt], s);
3064 GPR[rd] = EXTEND32 (temp);
3065 TRACE_ALU_RESULT (GPR[rd]);
3068 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3069 "srlv r<RD>, r<RT>, r<RS>"
3070 *mipsI,mipsII,mipsIII,mipsIV:
3072 // start-sanitize-vr4320
3074 // end-sanitize-vr4320
3075 // start-sanitize-vr5400
3077 // end-sanitize-vr5400
3078 // start-sanitize-r5900
3080 // end-sanitize-r5900
3082 // start-sanitize-tx19
3084 // end-sanitize-tx19
3086 do_srlv (SD_, RS, RT, RD);
3090 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3091 "sub r<RD>, r<RS>, r<RT>"
3092 *mipsI,mipsII,mipsIII,mipsIV:
3094 // start-sanitize-vr4320
3096 // end-sanitize-vr4320
3097 // start-sanitize-vr5400
3099 // end-sanitize-vr5400
3100 // start-sanitize-r5900
3102 // end-sanitize-r5900
3104 // start-sanitize-tx19
3106 // end-sanitize-tx19
3108 ALU32_BEGIN (GPR[RS]);
3109 ALU32_SUB (GPR[RT]);
3110 ALU32_END (GPR[RD]);
3114 :function:::void:do_subu:int rs, int rt, int rd
3116 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3117 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3118 TRACE_ALU_RESULT (GPR[rd]);
3121 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3122 "subu r<RD>, r<RS>, r<RT>"
3123 *mipsI,mipsII,mipsIII,mipsIV:
3125 // start-sanitize-vr4320
3127 // end-sanitize-vr4320
3128 // start-sanitize-vr5400
3130 // end-sanitize-vr5400
3131 // start-sanitize-r5900
3133 // end-sanitize-r5900
3135 // start-sanitize-tx19
3137 // end-sanitize-tx19
3139 do_subu (SD_, RS, RT, RD);
3143 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3144 "sw r<RT>, <OFFSET>(r<BASE>)"
3145 *mipsI,mipsII,mipsIII,mipsIV:
3146 // start-sanitize-tx19
3148 // end-sanitize-tx19
3150 // start-sanitize-vr4320
3152 // end-sanitize-vr4320
3154 // start-sanitize-vr5400
3156 // end-sanitize-vr5400
3157 // start-sanitize-r5900
3159 // end-sanitize-r5900
3161 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3165 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3166 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3167 *mipsI,mipsII,mipsIII,mipsIV:
3169 // start-sanitize-vr4320
3171 // end-sanitize-vr4320
3172 // start-sanitize-vr5400
3174 // end-sanitize-vr5400
3176 // start-sanitize-tx19
3178 // end-sanitize-tx19
3180 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3185 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3187 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3188 address_word reverseendian = (ReverseEndian ? -1 : 0);
3189 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3196 vaddr = base + offset;
3197 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3198 paddr = (paddr ^ (reverseendian & mask));
3199 if (BigEndianMem == 0)
3200 paddr = paddr & ~access;
3201 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3202 if ((byte & ~access) == 0)
3203 memval = (rt >> (8 * (access - byte)));
3205 memval = (rt << (8 * (mask - byte)));
3206 StoreMemory (uncached, byte & access, memval, 0, paddr, vaddr, isREAL);
3210 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3211 "swl r<RT>, <OFFSET>(r<BASE>)"
3212 *mipsI,mipsII,mipsIII,mipsIV:
3214 // start-sanitize-vr4320
3216 // end-sanitize-vr4320
3217 // start-sanitize-vr5400
3219 // end-sanitize-vr5400
3220 // start-sanitize-r5900
3222 // end-sanitize-r5900
3224 // start-sanitize-tx19
3226 // end-sanitize-tx19
3228 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3232 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3234 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3235 address_word reverseendian = (ReverseEndian ? -1 : 0);
3236 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3243 vaddr = base + offset;
3244 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3245 paddr = (paddr ^ (reverseendian & mask));
3246 if (BigEndianMem != 0)
3248 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3249 memval = (rt << (byte * 8));
3250 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3253 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3254 "swr r<RT>, <OFFSET>(r<BASE>)"
3255 *mipsI,mipsII,mipsIII,mipsIV:
3257 // start-sanitize-vr4320
3259 // end-sanitize-vr4320
3260 // start-sanitize-vr5400
3262 // end-sanitize-vr5400
3263 // start-sanitize-r5900
3265 // end-sanitize-r5900
3267 // start-sanitize-tx19
3269 // end-sanitize-tx19
3271 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3275 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3282 // start-sanitize-vr4320
3284 // end-sanitize-vr4320
3285 // start-sanitize-vr5400
3287 // end-sanitize-vr5400
3288 // start-sanitize-r5900
3290 // end-sanitize-r5900
3292 // start-sanitize-tx19
3294 // end-sanitize-tx19
3296 SyncOperation (STYPE);
3300 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3302 *mipsI,mipsII,mipsIII,mipsIV:
3304 // start-sanitize-vr4320
3306 // end-sanitize-vr4320
3307 // start-sanitize-vr5400
3309 // end-sanitize-vr5400
3310 // start-sanitize-r5900
3312 // end-sanitize-r5900
3314 // start-sanitize-tx19
3316 // end-sanitize-tx19
3318 SignalException(SystemCall, instruction_0);
3322 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3328 // start-sanitize-vr4320
3330 // end-sanitize-vr4320
3331 // start-sanitize-vr5400
3333 // end-sanitize-vr5400
3334 // start-sanitize-r5900
3336 // end-sanitize-r5900
3337 // start-sanitize-tx19
3339 // end-sanitize-tx19
3341 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3342 SignalException(Trap, instruction_0);
3346 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3347 "teqi r<RS>, <IMMEDIATE>"
3352 // start-sanitize-vr4320
3354 // end-sanitize-vr4320
3355 // start-sanitize-vr5400
3357 // end-sanitize-vr5400
3358 // start-sanitize-r5900
3360 // end-sanitize-r5900
3361 // start-sanitize-tx19
3363 // end-sanitize-tx19
3365 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3366 SignalException(Trap, instruction_0);
3370 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3376 // start-sanitize-vr4320
3378 // end-sanitize-vr4320
3379 // start-sanitize-vr5400
3381 // end-sanitize-vr5400
3382 // start-sanitize-r5900
3384 // end-sanitize-r5900
3385 // start-sanitize-tx19
3387 // end-sanitize-tx19
3389 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3390 SignalException(Trap, instruction_0);
3394 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3395 "tgei r<RS>, <IMMEDIATE>"
3400 // start-sanitize-vr4320
3402 // end-sanitize-vr4320
3403 // start-sanitize-vr5400
3405 // end-sanitize-vr5400
3406 // start-sanitize-r5900
3408 // end-sanitize-r5900
3409 // start-sanitize-tx19
3411 // end-sanitize-tx19
3413 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3414 SignalException(Trap, instruction_0);
3418 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3419 "tgeiu r<RS>, <IMMEDIATE>"
3424 // start-sanitize-vr4320
3426 // end-sanitize-vr4320
3427 // start-sanitize-vr5400
3429 // end-sanitize-vr5400
3430 // start-sanitize-r5900
3432 // end-sanitize-r5900
3433 // start-sanitize-tx19
3435 // end-sanitize-tx19
3437 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3438 SignalException(Trap, instruction_0);
3442 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3448 // start-sanitize-vr4320
3450 // end-sanitize-vr4320
3451 // start-sanitize-vr5400
3453 // end-sanitize-vr5400
3454 // start-sanitize-r5900
3456 // end-sanitize-r5900
3457 // start-sanitize-tx19
3459 // end-sanitize-tx19
3461 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3462 SignalException(Trap, instruction_0);
3466 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3472 // start-sanitize-vr4320
3474 // end-sanitize-vr4320
3475 // start-sanitize-vr5400
3477 // end-sanitize-vr5400
3478 // start-sanitize-r5900
3480 // end-sanitize-r5900
3481 // start-sanitize-tx19
3483 // end-sanitize-tx19
3485 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3486 SignalException(Trap, instruction_0);
3490 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3491 "tlti r<RS>, <IMMEDIATE>"
3496 // start-sanitize-vr4320
3498 // end-sanitize-vr4320
3499 // start-sanitize-vr5400
3501 // end-sanitize-vr5400
3502 // start-sanitize-r5900
3504 // end-sanitize-r5900
3505 // start-sanitize-tx19
3507 // end-sanitize-tx19
3509 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3510 SignalException(Trap, instruction_0);
3514 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3515 "tltiu r<RS>, <IMMEDIATE>"
3520 // start-sanitize-vr4320
3522 // end-sanitize-vr4320
3523 // start-sanitize-vr5400
3525 // end-sanitize-vr5400
3526 // start-sanitize-r5900
3528 // end-sanitize-r5900
3529 // start-sanitize-tx19
3531 // end-sanitize-tx19
3533 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3534 SignalException(Trap, instruction_0);
3538 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3544 // start-sanitize-vr4320
3546 // end-sanitize-vr4320
3547 // start-sanitize-vr5400
3549 // end-sanitize-vr5400
3550 // start-sanitize-r5900
3552 // end-sanitize-r5900
3553 // start-sanitize-tx19
3555 // end-sanitize-tx19
3557 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3558 SignalException(Trap, instruction_0);
3562 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3568 // start-sanitize-vr4320
3570 // end-sanitize-vr4320
3571 // start-sanitize-vr5400
3573 // end-sanitize-vr5400
3574 // start-sanitize-r5900
3576 // end-sanitize-r5900
3577 // start-sanitize-tx19
3579 // end-sanitize-tx19
3581 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3582 SignalException(Trap, instruction_0);
3586 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3587 "tne r<RS>, <IMMEDIATE>"
3592 // start-sanitize-vr4320
3594 // end-sanitize-vr4320
3595 // start-sanitize-vr5400
3597 // end-sanitize-vr5400
3598 // start-sanitize-r5900
3600 // end-sanitize-r5900
3601 // start-sanitize-tx19
3603 // end-sanitize-tx19
3605 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3606 SignalException(Trap, instruction_0);
3610 :function:::void:do_xor:int rs, int rt, int rd
3612 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3613 GPR[rd] = GPR[rs] ^ GPR[rt];
3614 TRACE_ALU_RESULT (GPR[rd]);
3617 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3618 "xor r<RD>, r<RS>, r<RT>"
3619 *mipsI,mipsII,mipsIII,mipsIV:
3621 // start-sanitize-vr4320
3623 // end-sanitize-vr4320
3624 // start-sanitize-vr5400
3626 // end-sanitize-vr5400
3627 // start-sanitize-r5900
3629 // end-sanitize-r5900
3631 // start-sanitize-tx19
3633 // end-sanitize-tx19
3635 do_xor (SD_, RS, RT, RD);
3639 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3641 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3642 GPR[rt] = GPR[rs] ^ immediate;
3643 TRACE_ALU_RESULT (GPR[rt]);
3646 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3647 "xori r<RT>, r<RS>, <IMMEDIATE>"
3648 *mipsI,mipsII,mipsIII,mipsIV:
3650 // start-sanitize-vr4320
3652 // end-sanitize-vr4320
3653 // start-sanitize-vr5400
3655 // end-sanitize-vr5400
3656 // start-sanitize-r5900
3658 // end-sanitize-r5900
3660 // start-sanitize-tx19
3662 // end-sanitize-tx19
3664 do_xori (SD_, RS, RT, IMMEDIATE);
3669 // MIPS Architecture:
3671 // FPU Instruction Set (COP1 & COP1X)
3679 case fmt_single: return "s";
3680 case fmt_double: return "d";
3681 case fmt_word: return "w";
3682 case fmt_long: return "l";
3683 default: return "?";
3693 default: return "?";
3713 :%s::::COND:int cond
3717 case 00: return "f";
3718 case 01: return "un";
3719 case 02: return "eq";
3720 case 03: return "ueq";
3721 case 04: return "olt";
3722 case 05: return "ult";
3723 case 06: return "ole";
3724 case 07: return "ule";
3725 case 010: return "sf";
3726 case 011: return "ngle";
3727 case 012: return "seq";
3728 case 013: return "ngl";
3729 case 014: return "lt";
3730 case 015: return "nge";
3731 case 016: return "le";
3732 case 017: return "ngt";
3733 default: return "?";
3738 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3739 "abs.%s<FMT> f<FD>, f<FS>"
3740 *mipsI,mipsII,mipsIII,mipsIV:
3742 // start-sanitize-vr4320
3744 // end-sanitize-vr4320
3745 // start-sanitize-vr5400
3747 // end-sanitize-vr5400
3749 // start-sanitize-tx19
3751 // end-sanitize-tx19
3753 unsigned32 instruction = instruction_0;
3754 int destreg = ((instruction >> 6) & 0x0000001F);
3755 int fs = ((instruction >> 11) & 0x0000001F);
3756 int format = ((instruction >> 21) & 0x00000007);
3758 if ((format != fmt_single) && (format != fmt_double))
3759 SignalException(ReservedInstruction,instruction);
3761 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3767 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3768 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3769 *mipsI,mipsII,mipsIII,mipsIV:
3771 // start-sanitize-vr4320
3773 // end-sanitize-vr4320
3774 // start-sanitize-vr5400
3776 // end-sanitize-vr5400
3778 // start-sanitize-tx19
3780 // end-sanitize-tx19
3782 unsigned32 instruction = instruction_0;
3783 int destreg = ((instruction >> 6) & 0x0000001F);
3784 int fs = ((instruction >> 11) & 0x0000001F);
3785 int ft = ((instruction >> 16) & 0x0000001F);
3786 int format = ((instruction >> 21) & 0x00000007);
3788 if ((format != fmt_single) && (format != fmt_double))
3789 SignalException(ReservedInstruction, instruction);
3791 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3802 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3803 "bc1%s<TF>%s<ND> <OFFSET>"
3804 *mipsI,mipsII,mipsIII:
3805 // start-sanitize-r5900
3807 // end-sanitize-r5900
3809 TRACE_BRANCH_INPUT (PREVCOC1());
3810 if (PREVCOC1() == TF)
3812 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3813 TRACE_BRANCH_RESULT (dest);
3818 TRACE_BRANCH_RESULT (0);
3819 NULLIFY_NEXT_INSTRUCTION ();
3823 TRACE_BRANCH_RESULT (NIA);
3827 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3828 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3829 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3832 // start-sanitize-vr4320
3834 // end-sanitize-vr4320
3835 // start-sanitize-vr5400
3837 // end-sanitize-vr5400
3839 // start-sanitize-tx19
3841 // end-sanitize-tx19
3843 if (GETFCC(CC) == TF)
3845 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3849 NULLIFY_NEXT_INSTRUCTION ();
3859 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3861 if ((fmt != fmt_single) && (fmt != fmt_double))
3862 SignalException (ReservedInstruction, insn);
3869 unsigned64 ofs = ValueFPR (fs, fmt);
3870 unsigned64 oft = ValueFPR (ft, fmt);
3871 if (NaN (ofs, fmt) || NaN (oft, fmt))
3873 if (FCSR & FP_ENABLE (IO))
3875 FCSR |= FP_CAUSE (IO);
3876 SignalExceptionFPE ();
3884 less = Less (ofs, oft, fmt);
3885 equal = Equal (ofs, oft, fmt);
3888 condition = (((cond & (1 << 2)) && less)
3889 || ((cond & (1 << 1)) && equal)
3890 || ((cond & (1 << 0)) && unordered));
3891 SETFCC (cc, condition);
3895 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3896 *mipsI,mipsII,mipsIII:
3897 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3899 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3902 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3903 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3904 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3907 // start-sanitize-vr4320
3909 // end-sanitize-vr4320
3910 // start-sanitize-vr5400
3912 // end-sanitize-vr5400
3914 // start-sanitize-tx19
3916 // end-sanitize-tx19
3918 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3922 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3923 "ceil.l.%s<FMT> f<FD>, f<FS>"
3927 // start-sanitize-vr4320
3929 // end-sanitize-vr4320
3930 // start-sanitize-vr5400
3932 // end-sanitize-vr5400
3933 // start-sanitize-r5900
3935 // end-sanitize-r5900
3937 // start-sanitize-tx19
3939 // end-sanitize-tx19
3941 unsigned32 instruction = instruction_0;
3942 int destreg = ((instruction >> 6) & 0x0000001F);
3943 int fs = ((instruction >> 11) & 0x0000001F);
3944 int format = ((instruction >> 21) & 0x00000007);
3946 if ((format != fmt_single) && (format != fmt_double))
3947 SignalException(ReservedInstruction,instruction);
3949 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3954 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3959 // start-sanitize-vr4320
3961 // end-sanitize-vr4320
3962 // start-sanitize-vr5400
3964 // end-sanitize-vr5400
3965 // start-sanitize-r5900
3967 // end-sanitize-r5900
3969 // start-sanitize-tx19
3971 // end-sanitize-tx19
3973 unsigned32 instruction = instruction_0;
3974 int destreg = ((instruction >> 6) & 0x0000001F);
3975 int fs = ((instruction >> 11) & 0x0000001F);
3976 int format = ((instruction >> 21) & 0x00000007);
3978 if ((format != fmt_single) && (format != fmt_double))
3979 SignalException(ReservedInstruction,instruction);
3981 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3988 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3989 "c%s<X>c1 r<RT>, f<FS>"
3997 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3999 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4001 PENDING_FILL(COCIDX,0); /* special case */
4004 { /* control from */
4006 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4008 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4012 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4013 "c%s<X>c1 r<RT>, f<FS>"
4016 // start-sanitize-vr4320
4018 // end-sanitize-vr4320
4019 // start-sanitize-vr5400
4021 // end-sanitize-vr5400
4023 // start-sanitize-tx19
4025 // end-sanitize-tx19
4030 TRACE_ALU_INPUT1 (GPR[RT]);
4033 FCR0 = VL4_8(GPR[RT]);
4034 TRACE_ALU_RESULT (FCR0);
4038 FCR31 = VL4_8(GPR[RT]);
4039 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4040 TRACE_ALU_RESULT (FCR31);
4044 TRACE_ALU_RESULT0 ();
4049 { /* control from */
4052 TRACE_ALU_INPUT1 (FCR0);
4053 GPR[RT] = SIGNEXTEND (FCR0, 32);
4057 TRACE_ALU_INPUT1 (FCR31);
4058 GPR[RT] = SIGNEXTEND (FCR31, 32);
4060 TRACE_ALU_RESULT (GPR[RT]);
4067 // FIXME: Does not correctly differentiate between mips*
4069 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4070 "cvt.d.%s<FMT> f<FD>, f<FS>"
4071 *mipsI,mipsII,mipsIII,mipsIV:
4073 // start-sanitize-vr4320
4075 // end-sanitize-vr4320
4076 // start-sanitize-vr5400
4078 // end-sanitize-vr5400
4080 // start-sanitize-tx19
4082 // end-sanitize-tx19
4084 unsigned32 instruction = instruction_0;
4085 int destreg = ((instruction >> 6) & 0x0000001F);
4086 int fs = ((instruction >> 11) & 0x0000001F);
4087 int format = ((instruction >> 21) & 0x00000007);
4089 if ((format == fmt_double) | 0)
4090 SignalException(ReservedInstruction,instruction);
4092 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4097 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4098 "cvt.l.%s<FMT> f<FD>, f<FS>"
4102 // start-sanitize-vr4320
4104 // end-sanitize-vr4320
4105 // start-sanitize-vr5400
4107 // end-sanitize-vr5400
4109 // start-sanitize-tx19
4111 // end-sanitize-tx19
4113 unsigned32 instruction = instruction_0;
4114 int destreg = ((instruction >> 6) & 0x0000001F);
4115 int fs = ((instruction >> 11) & 0x0000001F);
4116 int format = ((instruction >> 21) & 0x00000007);
4118 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4119 SignalException(ReservedInstruction,instruction);
4121 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4127 // FIXME: Does not correctly differentiate between mips*
4129 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4130 "cvt.s.%s<FMT> f<FD>, f<FS>"
4131 *mipsI,mipsII,mipsIII,mipsIV:
4133 // start-sanitize-vr4320
4135 // end-sanitize-vr4320
4136 // start-sanitize-vr5400
4138 // end-sanitize-vr5400
4140 // start-sanitize-tx19
4142 // end-sanitize-tx19
4144 unsigned32 instruction = instruction_0;
4145 int destreg = ((instruction >> 6) & 0x0000001F);
4146 int fs = ((instruction >> 11) & 0x0000001F);
4147 int format = ((instruction >> 21) & 0x00000007);
4149 if ((format == fmt_single) | 0)
4150 SignalException(ReservedInstruction,instruction);
4152 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4157 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4158 "cvt.w.%s<FMT> f<FD>, f<FS>"
4159 *mipsI,mipsII,mipsIII,mipsIV:
4161 // start-sanitize-vr4320
4163 // end-sanitize-vr4320
4164 // start-sanitize-vr5400
4166 // end-sanitize-vr5400
4168 // start-sanitize-tx19
4170 // end-sanitize-tx19
4172 unsigned32 instruction = instruction_0;
4173 int destreg = ((instruction >> 6) & 0x0000001F);
4174 int fs = ((instruction >> 11) & 0x0000001F);
4175 int format = ((instruction >> 21) & 0x00000007);
4177 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4178 SignalException(ReservedInstruction,instruction);
4180 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4185 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4186 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4187 *mipsI,mipsII,mipsIII,mipsIV:
4189 // start-sanitize-vr4320
4191 // end-sanitize-vr4320
4192 // start-sanitize-vr5400
4194 // end-sanitize-vr5400
4196 // start-sanitize-tx19
4198 // end-sanitize-tx19
4200 unsigned32 instruction = instruction_0;
4201 int destreg = ((instruction >> 6) & 0x0000001F);
4202 int fs = ((instruction >> 11) & 0x0000001F);
4203 int ft = ((instruction >> 16) & 0x0000001F);
4204 int format = ((instruction >> 21) & 0x00000007);
4206 if ((format != fmt_single) && (format != fmt_double))
4207 SignalException(ReservedInstruction,instruction);
4209 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4216 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4217 "dm%s<X>c1 r<RT>, f<FS>"
4222 if (SizeFGR() == 64)
4223 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4224 else if ((FS & 0x1) == 0)
4226 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4227 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4232 if (SizeFGR() == 64)
4233 PENDING_FILL(RT,FGR[FS]);
4234 else if ((FS & 0x1) == 0)
4235 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4237 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4240 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4241 "dm%s<X>c1 r<RT>, f<FS>"
4244 // start-sanitize-vr4320
4246 // end-sanitize-vr4320
4247 // start-sanitize-vr5400
4249 // end-sanitize-vr5400
4250 // start-sanitize-r5900
4252 // end-sanitize-r5900
4254 // start-sanitize-tx19
4256 // end-sanitize-tx19
4260 if (SizeFGR() == 64)
4261 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4262 else if ((FS & 0x1) == 0)
4263 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4267 if (SizeFGR() == 64)
4269 else if ((FS & 0x1) == 0)
4270 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4272 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4277 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4278 "floor.l.%s<FMT> f<FD>, f<FS>"
4282 // start-sanitize-vr4320
4284 // end-sanitize-vr4320
4285 // start-sanitize-vr5400
4287 // end-sanitize-vr5400
4288 // start-sanitize-r5900
4290 // end-sanitize-r5900
4292 // start-sanitize-tx19
4294 // end-sanitize-tx19
4296 unsigned32 instruction = instruction_0;
4297 int destreg = ((instruction >> 6) & 0x0000001F);
4298 int fs = ((instruction >> 11) & 0x0000001F);
4299 int format = ((instruction >> 21) & 0x00000007);
4301 if ((format != fmt_single) && (format != fmt_double))
4302 SignalException(ReservedInstruction,instruction);
4304 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4309 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4310 "floor.w.%s<FMT> f<FD>, f<FS>"
4315 // start-sanitize-vr4320
4317 // end-sanitize-vr4320
4318 // start-sanitize-vr5400
4320 // end-sanitize-vr5400
4321 // start-sanitize-r5900
4323 // end-sanitize-r5900
4325 // start-sanitize-tx19
4327 // end-sanitize-tx19
4329 unsigned32 instruction = instruction_0;
4330 int destreg = ((instruction >> 6) & 0x0000001F);
4331 int fs = ((instruction >> 11) & 0x0000001F);
4332 int format = ((instruction >> 21) & 0x00000007);
4334 if ((format != fmt_single) && (format != fmt_double))
4335 SignalException(ReservedInstruction,instruction);
4337 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4342 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4343 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4348 // start-sanitize-vr4320
4350 // end-sanitize-vr4320
4351 // start-sanitize-vr5400
4353 // end-sanitize-vr5400
4355 // start-sanitize-tx19
4357 // end-sanitize-tx19
4359 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4363 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4364 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4367 // start-sanitize-vr4320
4369 // end-sanitize-vr4320
4370 // start-sanitize-vr5400
4372 // end-sanitize-vr5400
4374 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4379 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4380 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4381 *mipsI,mipsII,mipsIII,mipsIV:
4383 // start-sanitize-vr4320
4385 // end-sanitize-vr4320
4386 // start-sanitize-vr5400
4388 // end-sanitize-vr5400
4389 // start-sanitize-r5900
4391 // end-sanitize-r5900
4393 // start-sanitize-tx19
4395 // end-sanitize-tx19
4397 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4401 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4402 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4405 // start-sanitize-vr4320
4407 // end-sanitize-vr4320
4408 // start-sanitize-vr5400
4410 // end-sanitize-vr5400
4412 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4418 // FIXME: Not correct for mips*
4420 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4421 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4424 // start-sanitize-vr4320
4426 // end-sanitize-vr4320
4427 // start-sanitize-vr5400
4429 // end-sanitize-vr5400
4431 unsigned32 instruction = instruction_0;
4432 int destreg = ((instruction >> 6) & 0x0000001F);
4433 int fs = ((instruction >> 11) & 0x0000001F);
4434 int ft = ((instruction >> 16) & 0x0000001F);
4435 int fr = ((instruction >> 21) & 0x0000001F);
4437 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4442 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4443 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4446 // start-sanitize-vr4320
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4451 // end-sanitize-vr5400
4453 unsigned32 instruction = instruction_0;
4454 int destreg = ((instruction >> 6) & 0x0000001F);
4455 int fs = ((instruction >> 11) & 0x0000001F);
4456 int ft = ((instruction >> 16) & 0x0000001F);
4457 int fr = ((instruction >> 21) & 0x0000001F);
4459 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4466 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4467 "m%s<X>c1 r<RT>, f<FS>"
4474 if (SizeFGR() == 64)
4475 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4477 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4480 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4482 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4483 "m%s<X>c1 r<RT>, f<FS>"
4486 // start-sanitize-vr4320
4488 // end-sanitize-vr4320
4489 // start-sanitize-vr5400
4491 // end-sanitize-vr5400
4493 // start-sanitize-tx19
4495 // end-sanitize-tx19
4499 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4501 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4505 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4506 "mov.%s<FMT> f<FD>, f<FS>"
4507 *mipsI,mipsII,mipsIII,mipsIV:
4509 // start-sanitize-vr4320
4511 // end-sanitize-vr4320
4512 // start-sanitize-vr5400
4514 // end-sanitize-vr5400
4516 // start-sanitize-tx19
4518 // end-sanitize-tx19
4520 unsigned32 instruction = instruction_0;
4521 int destreg = ((instruction >> 6) & 0x0000001F);
4522 int fs = ((instruction >> 11) & 0x0000001F);
4523 int format = ((instruction >> 21) & 0x00000007);
4525 StoreFPR(destreg,format,ValueFPR(fs,format));
4531 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4532 "mov%s<TF> r<RD>, r<RS>, <CC>"
4535 // start-sanitize-vr4320
4537 // end-sanitize-vr4320
4538 // start-sanitize-vr5400
4540 // end-sanitize-vr5400
4541 // start-sanitize-r5900
4543 // end-sanitize-r5900
4545 if (GETFCC(CC) == TF)
4551 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4552 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4555 // start-sanitize-vr4320
4557 // end-sanitize-vr4320
4558 // start-sanitize-vr5400
4560 // end-sanitize-vr5400
4561 // start-sanitize-r5900
4563 // end-sanitize-r5900
4565 unsigned32 instruction = instruction_0;
4566 int format = ((instruction >> 21) & 0x00000007);
4568 if (GETFCC(CC) == TF)
4569 StoreFPR (FD, format, ValueFPR (FS, format));
4571 StoreFPR (FD, format, ValueFPR (FD, format));
4576 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4579 // start-sanitize-vr4320
4581 // end-sanitize-vr4320
4582 // start-sanitize-vr5400
4584 // end-sanitize-vr5400
4585 // start-sanitize-r5900
4587 // end-sanitize-r5900
4589 unsigned32 instruction = instruction_0;
4590 int destreg = ((instruction >> 6) & 0x0000001F);
4591 int fs = ((instruction >> 11) & 0x0000001F);
4592 int format = ((instruction >> 21) & 0x00000007);
4594 StoreFPR(destreg,format,ValueFPR(fs,format));
4602 // MOVT.fmt see MOVtf.fmt
4606 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4607 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4610 // start-sanitize-vr4320
4612 // end-sanitize-vr4320
4613 // start-sanitize-vr5400
4615 // end-sanitize-vr5400
4616 // start-sanitize-r5900
4618 // end-sanitize-r5900
4620 unsigned32 instruction = instruction_0;
4621 int destreg = ((instruction >> 6) & 0x0000001F);
4622 int fs = ((instruction >> 11) & 0x0000001F);
4623 int format = ((instruction >> 21) & 0x00000007);
4625 StoreFPR(destreg,format,ValueFPR(fs,format));
4631 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4632 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4635 // start-sanitize-vr4320
4637 // end-sanitize-vr4320
4638 // start-sanitize-vr5400
4640 // end-sanitize-vr5400
4641 // start-sanitize-r5900
4643 // end-sanitize-r5900
4645 unsigned32 instruction = instruction_0;
4646 int destreg = ((instruction >> 6) & 0x0000001F);
4647 int fs = ((instruction >> 11) & 0x0000001F);
4648 int ft = ((instruction >> 16) & 0x0000001F);
4649 int fr = ((instruction >> 21) & 0x0000001F);
4651 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4657 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4658 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4661 // start-sanitize-vr4320
4663 // end-sanitize-vr4320
4664 // start-sanitize-vr5400
4666 // end-sanitize-vr5400
4667 // start-sanitize-r5900
4669 // end-sanitize-r5900
4671 unsigned32 instruction = instruction_0;
4672 int destreg = ((instruction >> 6) & 0x0000001F);
4673 int fs = ((instruction >> 11) & 0x0000001F);
4674 int ft = ((instruction >> 16) & 0x0000001F);
4675 int fr = ((instruction >> 21) & 0x0000001F);
4677 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4685 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4686 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4687 *mipsI,mipsII,mipsIII,mipsIV:
4689 // start-sanitize-vr4320
4691 // end-sanitize-vr4320
4692 // start-sanitize-vr5400
4694 // end-sanitize-vr5400
4696 // start-sanitize-tx19
4698 // end-sanitize-tx19
4700 unsigned32 instruction = instruction_0;
4701 int destreg = ((instruction >> 6) & 0x0000001F);
4702 int fs = ((instruction >> 11) & 0x0000001F);
4703 int ft = ((instruction >> 16) & 0x0000001F);
4704 int format = ((instruction >> 21) & 0x00000007);
4706 if ((format != fmt_single) && (format != fmt_double))
4707 SignalException(ReservedInstruction,instruction);
4709 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4714 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4715 "neg.%s<FMT> f<FD>, f<FS>"
4716 *mipsI,mipsII,mipsIII,mipsIV:
4718 // start-sanitize-vr4320
4720 // end-sanitize-vr4320
4721 // start-sanitize-vr5400
4723 // end-sanitize-vr5400
4725 // start-sanitize-tx19
4727 // end-sanitize-tx19
4729 unsigned32 instruction = instruction_0;
4730 int destreg = ((instruction >> 6) & 0x0000001F);
4731 int fs = ((instruction >> 11) & 0x0000001F);
4732 int format = ((instruction >> 21) & 0x00000007);
4734 if ((format != fmt_single) && (format != fmt_double))
4735 SignalException(ReservedInstruction,instruction);
4737 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4743 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4744 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4747 // start-sanitize-vr4320
4749 // end-sanitize-vr4320
4750 // start-sanitize-vr5400
4752 // end-sanitize-vr5400
4754 unsigned32 instruction = instruction_0;
4755 int destreg = ((instruction >> 6) & 0x0000001F);
4756 int fs = ((instruction >> 11) & 0x0000001F);
4757 int ft = ((instruction >> 16) & 0x0000001F);
4758 int fr = ((instruction >> 21) & 0x0000001F);
4760 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4766 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4767 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4770 // start-sanitize-vr4320
4772 // end-sanitize-vr4320
4773 // start-sanitize-vr5400
4775 // end-sanitize-vr5400
4777 unsigned32 instruction = instruction_0;
4778 int destreg = ((instruction >> 6) & 0x0000001F);
4779 int fs = ((instruction >> 11) & 0x0000001F);
4780 int ft = ((instruction >> 16) & 0x0000001F);
4781 int fr = ((instruction >> 21) & 0x0000001F);
4783 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4789 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4790 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4793 // start-sanitize-vr4320
4795 // end-sanitize-vr4320
4796 // start-sanitize-vr5400
4798 // end-sanitize-vr5400
4800 unsigned32 instruction = instruction_0;
4801 int destreg = ((instruction >> 6) & 0x0000001F);
4802 int fs = ((instruction >> 11) & 0x0000001F);
4803 int ft = ((instruction >> 16) & 0x0000001F);
4804 int fr = ((instruction >> 21) & 0x0000001F);
4806 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4812 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4813 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4816 // start-sanitize-vr4320
4818 // end-sanitize-vr4320
4819 // start-sanitize-vr5400
4821 // end-sanitize-vr5400
4823 unsigned32 instruction = instruction_0;
4824 int destreg = ((instruction >> 6) & 0x0000001F);
4825 int fs = ((instruction >> 11) & 0x0000001F);
4826 int ft = ((instruction >> 16) & 0x0000001F);
4827 int fr = ((instruction >> 21) & 0x0000001F);
4829 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4834 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4835 "prefx <HINT>, r<INDEX>(r<BASE>)"
4838 // start-sanitize-vr4320
4840 // end-sanitize-vr4320
4841 // start-sanitize-vr5400
4843 // end-sanitize-vr5400
4845 unsigned32 instruction = instruction_0;
4846 int fs = ((instruction >> 11) & 0x0000001F);
4847 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4848 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4850 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4853 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4854 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4858 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4860 "recip.%s<FMT> f<FD>, f<FS>"
4862 // start-sanitize-vr4320
4864 // end-sanitize-vr4320
4865 // start-sanitize-vr5400
4867 // end-sanitize-vr5400
4869 unsigned32 instruction = instruction_0;
4870 int destreg = ((instruction >> 6) & 0x0000001F);
4871 int fs = ((instruction >> 11) & 0x0000001F);
4872 int format = ((instruction >> 21) & 0x00000007);
4874 if ((format != fmt_single) && (format != fmt_double))
4875 SignalException(ReservedInstruction,instruction);
4877 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4882 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4883 "round.l.%s<FMT> f<FD>, f<FS>"
4887 // start-sanitize-vr4320
4889 // end-sanitize-vr4320
4890 // start-sanitize-vr5400
4892 // end-sanitize-vr5400
4893 // start-sanitize-r5900
4895 // end-sanitize-r5900
4897 // start-sanitize-tx19
4899 // end-sanitize-tx19
4901 unsigned32 instruction = instruction_0;
4902 int destreg = ((instruction >> 6) & 0x0000001F);
4903 int fs = ((instruction >> 11) & 0x0000001F);
4904 int format = ((instruction >> 21) & 0x00000007);
4906 if ((format != fmt_single) && (format != fmt_double))
4907 SignalException(ReservedInstruction,instruction);
4909 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4914 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4915 "round.w.%s<FMT> f<FD>, f<FS>"
4920 // start-sanitize-vr4320
4922 // end-sanitize-vr4320
4923 // start-sanitize-vr5400
4925 // end-sanitize-vr5400
4926 // start-sanitize-r5900
4928 // end-sanitize-r5900
4930 // start-sanitize-tx19
4932 // end-sanitize-tx19
4934 unsigned32 instruction = instruction_0;
4935 int destreg = ((instruction >> 6) & 0x0000001F);
4936 int fs = ((instruction >> 11) & 0x0000001F);
4937 int format = ((instruction >> 21) & 0x00000007);
4939 if ((format != fmt_single) && (format != fmt_double))
4940 SignalException(ReservedInstruction,instruction);
4942 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4947 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4949 "rsqrt.%s<FMT> f<FD>, f<FS>"
4951 // start-sanitize-vr4320
4953 // end-sanitize-vr4320
4954 // start-sanitize-vr5400
4956 // end-sanitize-vr5400
4958 unsigned32 instruction = instruction_0;
4959 int destreg = ((instruction >> 6) & 0x0000001F);
4960 int fs = ((instruction >> 11) & 0x0000001F);
4961 int format = ((instruction >> 21) & 0x00000007);
4963 if ((format != fmt_single) && (format != fmt_double))
4964 SignalException(ReservedInstruction,instruction);
4966 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4971 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4972 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4977 // start-sanitize-vr4320
4979 // end-sanitize-vr4320
4980 // start-sanitize-vr5400
4982 // end-sanitize-vr5400
4984 // start-sanitize-tx19
4986 // end-sanitize-tx19
4988 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4992 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4993 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4996 // start-sanitize-vr4320
4998 // end-sanitize-vr4320
4999 // start-sanitize-vr5400
5001 // end-sanitize-vr5400
5003 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5007 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5008 "sqrt.%s<FMT> f<FD>, f<FS>"
5013 // start-sanitize-vr4320
5015 // end-sanitize-vr4320
5016 // start-sanitize-vr5400
5018 // end-sanitize-vr5400
5020 // start-sanitize-tx19
5022 // end-sanitize-tx19
5024 unsigned32 instruction = instruction_0;
5025 int destreg = ((instruction >> 6) & 0x0000001F);
5026 int fs = ((instruction >> 11) & 0x0000001F);
5027 int format = ((instruction >> 21) & 0x00000007);
5029 if ((format != fmt_single) && (format != fmt_double))
5030 SignalException(ReservedInstruction,instruction);
5032 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5037 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5038 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5039 *mipsI,mipsII,mipsIII,mipsIV:
5041 // start-sanitize-vr4320
5043 // end-sanitize-vr4320
5044 // start-sanitize-vr5400
5046 // end-sanitize-vr5400
5048 // start-sanitize-tx19
5050 // end-sanitize-tx19
5052 unsigned32 instruction = instruction_0;
5053 int destreg = ((instruction >> 6) & 0x0000001F);
5054 int fs = ((instruction >> 11) & 0x0000001F);
5055 int ft = ((instruction >> 16) & 0x0000001F);
5056 int format = ((instruction >> 21) & 0x00000007);
5058 if ((format != fmt_single) && (format != fmt_double))
5059 SignalException(ReservedInstruction,instruction);
5061 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5067 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5068 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5069 *mipsI,mipsII,mipsIII,mipsIV:
5071 // start-sanitize-vr4320
5073 // end-sanitize-vr4320
5074 // start-sanitize-vr5400
5076 // end-sanitize-vr5400
5077 // start-sanitize-r5900
5079 // end-sanitize-r5900
5081 // start-sanitize-tx19
5083 // end-sanitize-tx19
5085 unsigned32 instruction = instruction_0;
5086 signed_word offset = EXTEND16 (OFFSET);
5087 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5088 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5090 address_word vaddr = ((uword64)op1 + offset);
5093 if ((vaddr & 3) != 0)
5094 SignalExceptionAddressStore();
5097 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5100 uword64 memval1 = 0;
5103 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5104 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5105 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5107 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5115 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5116 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5119 // start-sanitize-vr4320
5121 // end-sanitize-vr4320
5122 // start-sanitize-vr5400
5124 // end-sanitize-vr5400
5126 unsigned32 instruction = instruction_0;
5127 int fs = ((instruction >> 11) & 0x0000001F);
5128 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5129 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5131 address_word vaddr = ((unsigned64)op1 + op2);
5134 if ((vaddr & 3) != 0)
5135 SignalExceptionAddressStore();
5138 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5140 unsigned64 memval = 0;
5141 unsigned64 memval1 = 0;
5142 unsigned64 mask = 0x7;
5144 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5145 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5146 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5148 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5156 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5157 "trunc.l.%s<FMT> f<FD>, f<FS>"
5161 // start-sanitize-vr4320
5163 // end-sanitize-vr4320
5164 // start-sanitize-vr5400
5166 // end-sanitize-vr5400
5167 // start-sanitize-r5900
5169 // end-sanitize-r5900
5171 // start-sanitize-tx19
5173 // end-sanitize-tx19
5175 unsigned32 instruction = instruction_0;
5176 int destreg = ((instruction >> 6) & 0x0000001F);
5177 int fs = ((instruction >> 11) & 0x0000001F);
5178 int format = ((instruction >> 21) & 0x00000007);
5180 if ((format != fmt_single) && (format != fmt_double))
5181 SignalException(ReservedInstruction,instruction);
5183 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5188 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5189 "trunc.w.%s<FMT> f<FD>, f<FS>"
5194 // start-sanitize-vr4320
5196 // end-sanitize-vr4320
5197 // start-sanitize-vr5400
5199 // end-sanitize-vr5400
5200 // start-sanitize-r5900
5202 // end-sanitize-r5900
5204 // start-sanitize-tx19
5206 // end-sanitize-tx19
5208 unsigned32 instruction = instruction_0;
5209 int destreg = ((instruction >> 6) & 0x0000001F);
5210 int fs = ((instruction >> 11) & 0x0000001F);
5211 int format = ((instruction >> 21) & 0x00000007);
5213 if ((format != fmt_single) && (format != fmt_double))
5214 SignalException(ReservedInstruction,instruction);
5216 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5222 // MIPS Architecture:
5224 // System Control Instruction Set (COP0)
5228 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5230 *mipsI,mipsII,mipsIII,mipsIV:
5232 // start-sanitize-vr4320
5234 // end-sanitize-vr4320
5235 // start-sanitize-vr5400
5237 // end-sanitize-vr5400
5238 // start-sanitize-r5900
5240 // end-sanitize-r5900
5243 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5245 *mipsI,mipsII,mipsIII,mipsIV:
5247 // start-sanitize-vr4320
5249 // end-sanitize-vr4320
5250 // start-sanitize-vr5400
5252 // end-sanitize-vr5400
5253 // start-sanitize-r5900
5255 // end-sanitize-r5900
5258 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5260 *mipsI,mipsII,mipsIII,mipsIV:
5261 // start-sanitize-r5900
5263 // end-sanitize-r5900
5267 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5269 *mipsI,mipsII,mipsIII,mipsIV:
5271 // start-sanitize-vr4320
5273 // end-sanitize-vr4320
5274 // start-sanitize-vr5400
5276 // end-sanitize-vr5400
5277 // start-sanitize-r5900
5279 // end-sanitize-r5900
5282 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5286 // start-sanitize-vr4320
5288 // end-sanitize-vr4320
5289 // start-sanitize-vr5400
5291 // end-sanitize-vr5400
5292 // start-sanitize-r5900
5294 // end-sanitize-r5900
5296 // start-sanitize-tx19
5298 // end-sanitize-tx19
5300 unsigned32 instruction = instruction_0;
5301 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5302 int hint = ((instruction >> 16) & 0x0000001F);
5303 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5305 address_word vaddr = (op1 + offset);
5308 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5309 CacheOp(hint,vaddr,paddr,instruction);
5314 010000,10000,000000000000000,111001:COP0:32::DI
5316 *mipsI,mipsII,mipsIII,mipsIV:
5318 // start-sanitize-vr4320
5320 // end-sanitize-vr4320
5321 // start-sanitize-vr5400
5323 // end-sanitize-vr5400
5324 // start-sanitize-r5900
5326 // end-sanitize-r5900
5329 010000,10000,000000000000000,111000:COP0:32::EI
5331 *mipsI,mipsII,mipsIII,mipsIV:
5333 // start-sanitize-vr4320
5335 // end-sanitize-vr4320
5336 // start-sanitize-vr5400
5338 // end-sanitize-vr5400
5339 // start-sanitize-r5900
5341 // end-sanitize-r5900
5344 010000,10000,000000000000000,011000:COP0:32::ERET
5349 // start-sanitize-vr4320
5351 // end-sanitize-vr4320
5352 // start-sanitize-vr5400
5354 // end-sanitize-vr5400
5355 // start-sanitize-r5900
5357 // end-sanitize-r5900
5359 if (SR & status_ERL)
5361 /* Oops, not yet available */
5362 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5374 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5375 "mfc0 r<RT>, r<RD> # <REGX>"
5376 *mipsI,mipsII,mipsIII,mipsIV:
5379 // start-sanitize-vr4320
5381 // end-sanitize-vr4320
5382 // start-sanitize-vr5400
5384 // end-sanitize-vr5400
5385 // start-sanitize-r5900
5387 // end-sanitize-r5900
5389 TRACE_ALU_INPUT0 ();
5390 DecodeCoproc (instruction_0);
5391 TRACE_ALU_RESULT (GPR[RT]);
5394 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5395 "mtc0 r<RT>, r<RD> # <REGX>"
5396 *mipsI,mipsII,mipsIII,mipsIV:
5397 // start-sanitize-tx19
5399 // end-sanitize-tx19
5401 // start-sanitize-vr4320
5403 // end-sanitize-vr4320
5405 // start-sanitize-vr5400
5407 // end-sanitize-vr5400
5408 // start-sanitize-r5900
5410 // end-sanitize-r5900
5412 DecodeCoproc (instruction_0);
5416 010000,10000,000000000000000,010000:COP0:32::RFE
5418 *mipsI,mipsII,mipsIII,mipsIV:
5419 // start-sanitize-tx19
5421 // end-sanitize-tx19
5423 // start-sanitize-vr4320
5425 // end-sanitize-vr4320
5427 // start-sanitize-vr5400
5429 // end-sanitize-vr5400
5430 // start-sanitize-r5900
5432 // end-sanitize-r5900
5434 DecodeCoproc (instruction_0);
5438 010000,10000,000000000000000,001000:COP0:32::TLBP
5440 *mipsI,mipsII,mipsIII,mipsIV:
5442 // start-sanitize-vr4320
5444 // end-sanitize-vr4320
5445 // start-sanitize-vr5400
5447 // end-sanitize-vr5400
5448 // start-sanitize-r5900
5450 // end-sanitize-r5900
5453 010000,10000,000000000000000,000001:COP0:32::TLBR
5455 *mipsI,mipsII,mipsIII,mipsIV:
5457 // start-sanitize-vr4320
5459 // end-sanitize-vr4320
5460 // start-sanitize-vr5400
5462 // end-sanitize-vr5400
5463 // start-sanitize-r5900
5465 // end-sanitize-r5900
5468 010000,10000,000000000000000,000010:COP0:32::TLBWI
5470 *mipsI,mipsII,mipsIII,mipsIV:
5472 // start-sanitize-vr4320
5474 // end-sanitize-vr4320
5475 // start-sanitize-vr5400
5477 // end-sanitize-vr5400
5478 // start-sanitize-r5900
5480 // end-sanitize-r5900
5483 010000,10000,000000000000000,000110:COP0:32::TLBWR
5485 *mipsI,mipsII,mipsIII,mipsIV:
5487 // start-sanitize-vr4320
5489 // end-sanitize-vr4320
5490 // start-sanitize-vr5400
5492 // end-sanitize-vr5400
5493 // start-sanitize-r5900
5495 // end-sanitize-r5900
5499 // start-sanitize-vr4320
5500 :include::vr4320:vr4320.igen
5501 // end-sanitize-vr4320
5502 // start-sanitize-vr5400
5503 :include::vr5400:vr5400.igen
5504 :include:64,f::mdmx.igen
5505 // end-sanitize-vr5400
5506 // start-sanitize-r5900
5507 :include::r5900:r5900.igen
5508 // end-sanitize-r5900
5511 // start-sanitize-cygnus-never
5513 // // FIXME FIXME FIXME What is this instruction?
5514 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5519 // // start-sanitize-r5900
5521 // // end-sanitize-r5900
5523 // // start-sanitize-tx19
5525 // // end-sanitize-tx19
5527 // unsigned32 instruction = instruction_0;
5528 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5529 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5530 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5532 // if (CoProcPresent(3))
5533 // SignalException(CoProcessorUnusable);
5535 // SignalException(ReservedInstruction,instruction);
5539 // end-sanitize-cygnus-never
5540 // start-sanitize-cygnus-never
5542 // // FIXME FIXME FIXME What is this?
5543 // 11100,******,00001:RR:16::SDBBP
5546 // unsigned32 instruction = instruction_0;
5547 // if (have_extendval)
5548 // SignalException (ReservedInstruction, instruction);
5550 // SignalException(DebugBreakPoint,instruction);
5554 // end-sanitize-cygnus-never
5555 // start-sanitize-cygnus-never
5557 // // FIXME FIXME FIXME What is this?
5558 // 000000,********************,001110:SPECIAL:32::SDBBP
5561 // unsigned32 instruction = instruction_0;
5563 // SignalException(DebugBreakPoint,instruction);
5567 // end-sanitize-cygnus-never
5568 // start-sanitize-cygnus-never
5570 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5571 // // isn't yet reconized by this simulator.
5572 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5575 // unsigned32 instruction = instruction_0;
5576 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5577 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5579 // CHECKHILO("Multiply-Add");
5581 // unsigned64 temp = (op1 * op2);
5582 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5583 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5584 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5589 // end-sanitize-cygnus-never
5590 // start-sanitize-cygnus-never
5592 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5593 // // isn't yet reconized by this simulator.
5594 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5597 // unsigned32 instruction = instruction_0;
5598 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5599 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5601 // CHECKHILO("Multiply-Add");
5603 // unsigned64 temp = (op1 * op2);
5609 // end-sanitize-cygnus-never