sim/mn10300/ChangeLog

   1 Fri May 16 16:36:17 1997  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (load_mem): If we get a load from an out of range
   4         address, abort.
   5         (store_mem): Likewise for stores.
   6         (max_mem): New variable.
   7
   8 Tue May  6 13:24:36 1997  Jeffrey A Law  (law@cygnus.com)
   9
  10         * mn10300_sim.h: Fix ordering of bits in the PSW.
  11
  12         * interp.c: Improve hashing routine to avoid long list
  13         traversals for common instructions.  Add HASH_STAT support.
  14         Rewrite opcode dispatch code using a big switch instead of
  15         cascaded if/else statements.  Avoid useless calls to load_mem.
  16
  17 Mon May  5 18:07:48 1997  Jeffrey A Law  (law@cygnus.com)
  18
  19         * mn10300_sim.h (struct _state): Add space for mdrq register.
  20         (REG_MDRQ): Define.
  21         * simops.c: Don't abort for trap.  Add support for the extended
  22         instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
  23         and "bsch".
  24
  25 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
  26
  27         * configure: Regenerated to track ../common/aclocal.m4 changes.
  28
  29 Fri Apr 18 14:04:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  30
  31         * interp.c (sim_stop): Add stub function.
  32
  33 Thu Apr 17 03:26:59 1997  Doug Evans  <dje@canuck.cygnus.com>
  34
  35         * Makefile.in (SIM_OBJS): Add sim-load.o.
  36         * interp.c (sim_kind, myname): New static locals.
  37         (sim_open): Set sim_kind, myname.  Ignore -E arg.
  38         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
  39         load file into simulator.  Set start address from bfd.
  40         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
  41
  42 Wed Apr 16 19:30:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
  43
  44         * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
  45         only include if implemented by host.
  46         (OP_F020): Typecast arg passed to time function;
  47
  48 Mon Apr  7 23:57:49 1997  Jeffrey A Law  (law@cygnus.com)
  49
  50         * simops.c (syscall): Handle new mn10300 calling conventions.
  51
  52 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  53
  54         * configure: Regenerated to track ../common/aclocal.m4 changes.
  55         * config.in: Ditto.
  56
  57 Fri Apr  4 20:02:37 1997  Ian Lance Taylor  <ian@cygnus.com>
  58
  59         * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
  60         corresponding change in opcodes directory.
  61
  62 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
  63
  64         * interp.c (sim_open): New arg `kind'.
  65
  66         * configure: Regenerated to track ../common/aclocal.m4 changes.
  67
  68 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
  69
  70         * configure: Regenerated to track ../common/aclocal.m4 changes.
  71
  72 Thu Mar 20 11:58:02 1997  Jeffrey A Law  (law@cygnus.com)
  73
  74         * simops.c: Fix register extraction for a two "movbu" variants.
  75         Somewhat simplify "sub" instructions.
  76         Correctly sign extend operands for "mul".  Put the correct
  77         half of the result in MDR for "mul" and "mulu".
  78         Implement remaining instructions.
  79         Tweak opcode for "syscall".
  80
  81 Tue Mar 18 14:21:21 1997  Jeffrey A Law  (law@cygnus.com)
  82
  83         * simops.c: Do syscall emulation in "syscall" instruction.  Add
  84         dummy "trap" instruction.
  85
  86 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  87
  88         * configure: Regenerated to track ../common/aclocal.m4 changes.
  89
  90 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
  91
  92         * configure: Re-generate.
  93
  94 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
  95
  96         * configure: Regenerate to track ../common/aclocal.m4 changes.
  97
  98 Thu Mar 13 12:54:45 1997  Doug Evans  <dje@canuck.cygnus.com>
  99
 100         * interp.c (sim_open): New SIM_DESC result.  Argument is now
 101         in argv form.
 102         (other sim_*): New SIM_DESC argument.
 103
 104 Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
 105
 106         * simops.c: Fix carry bit computation for "add" instructions.
 107
 108         * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
 109         for bset imm8,(d8,an) and bclr imm8,(d8,an).
 110
 111 Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
 112
 113         * simops.c: Fix register references when computing Z and N bits
 114         for lsr imm8,dn.
 115
 116 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
 117
 118         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
 119         COMMON_{PRE,POST}_CONFIG_FRAG instead.
 120         * configure.in: sinclude ../common/aclocal.m4.
 121         * configure: Regenerated.
 122
 123 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
 124
 125         * interp.c (init_system): Allocate 2^19 bytes of space for the
 126         simulator.
 127
 128 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
 129
 130         * configure configure.in Makefile.in:  Update to new configure
 131         scheme which is more compatible with WinGDB builds.
 132         * configure.in:  Improve comment on how to run autoconf.
 133         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
 134         * Makefile.in:  Use autoconf substitution to install common
 135         makefile fragment.
 136
 137 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
 138
 139         * simops.c: Undo last change to "rol" and "ror", original code
 140         was correct!
 141
 142 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
 143
 144         * simops.c: Fix "rol" and "ror".
 145
 146 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
 147
 148         * simops.c: Fix typo in last change.
 149
 150 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
 151
 152         * simops.c: Use REG macros in few places not using them yet.
 153
 154 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
 155
 156         * mn10300_sim.h (struct _state): Fix number of registers!
 157
 158 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
 159
 160         * mn10300_sim.h (struct _state): Put all registers into a single
 161         array to make gdb implementation easier.
 162         (REG_*): Add definitions for all registers in the state array.
 163         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
 164         * simops.c: Related changes.
 165
 166 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
 167
 168         * interp.c (sim_resume): Handle 0xff as a single byte insn.
 169
 170         * simops.c: Fix overflow computation for "add" and "inc"
 171         instructions.
 172
 173 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 174
 175         * simops.c: Handle "break" instruction.
 176
 177         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
 178
 179 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
 180
 181         * gencode.c (write_opcodes): Also write out the format of the
 182         opcode.
 183         * mn10300_sim.h (simops): Add "format" field.
 184         * interp.c (sim_resume): Deal with endianness issues here.
 185
 186 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
 187
 188         * simops.c (REG0_4): Define.
 189         Use REG0_4 for indexed loads/stores.
 190
 191 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
 192
 193         * simops.c (REG0_16): Fix typo.
 194
 195 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
 196
 197         * simops.c: Call abort for any instruction that's not currently
 198         simulated.
 199
 200         * simops.c: Define accessor macros to extract register
 201         values from instructions.  Use them consistently.
 202
 203         * interp.c: Delete unused global variable "OP".
 204         (sim_resume): Remove unused variable "opcode".
 205         * simops.c: Fix some uninitialized variable problems, add
 206         parens to fix various -Wall warnings.
 207
 208         * gencode.c (write_header): Add "insn" and "extension" arguments
 209         to the OP_* declarations.
 210         (write_template): Similarly for function templates.
 211         * interp.c (insn, extension): Remove global variables.  Instead
 212         pass them as arguments to the OP_* functions.
 213         * mn10300_sim.h: Remove decls for "insn" and "extension".
 214         * simops.c (OP_*): Accept "insn" and "extension" as arguments
 215         instead of using globals.
 216
 217 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
 218
 219         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
 220
 221         * simops.c: Fix thinkos in last change to "inc dn".
 222
 223 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 224
 225         * simops.c: "add imm,sp" does not effect the condition codes.
 226         "inc dn" does effect the condition codes.
 227
 228 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 229
 230         * simops.c: Treat both operands as signed values for
 231         "div" instruction.
 232
 233         * simops.c: Fix simulation of division instructions.
 234         Fix typos/thinkos in several "cmp" and "sub" instructions.
 235
 236 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 237
 238         * simops.c: Fix carry bit handling in "sub" and "cmp"
 239         instructions.
 240
 241         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 242
 243 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 244
 245         * simops.c: Fix overflow computation for many instructions.
 246
 247         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 248
 249         * simops.c: Fix "mov am, dn".
 250
 251         * simops.c: Fix more bugs in "add imm,an" and
 252         "add imm,dn".
 253
 254 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 255
 256         * simops.c: Fix bugs in "movm" and "add imm,an".
 257
 258         * simops.c: Don't lose the upper 24 bits of the return
 259         pointer in "call" and "calls" instructions.  Rough cut
 260         at emulated system calls.
 261
 262         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 263
 264         * simops.c: Implement remaining 4 byte instructions.
 265
 266         * simops.c: Implement remaining 3 byte instructions.
 267
 268         * simops.c: Implement remaining 2 byte instructions.  Call
 269         abort for instructions we're not implementing now.
 270
 271 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 272
 273         * simops.c: Implement lots of random instructions.
 274
 275         * simops.c: Implement "movm" and "bCC" insns.
 276
 277         * mn10300_sim.h (_state): Add another register (MDR).
 278         (REG_MDR): Define.
 279         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 280         a few additional random insns.
 281
 282         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 283         (REG_D0, REG_A0, REG_SP): Define.
 284         * simops.c: Implement "add", "addc" and a few other random
 285         instructions.
 286
 287         * gencode.c, interp.c: Snapshot current simulator code.
 288
 289 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 290
 291         * Makefile.in, config.in, configure, configure.in: New files.
 292         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 293