1 /* This file is part of the program GDB, the GNU debugger.
3 Copyright (C) 1998-2021 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
21 /* This must come before any other includes. */
26 #include "sim-assert.h"
31 mn103tim - mn103002 timers (8 and 16 bit)
36 Implements the mn103002 8 and 16 bit timers as described in the mn103002 user guide.
41 reg = <8bit-timers-addr> <8bit-timers-size> <16bit-timers-addr> <16bit-timers-size>
49 /* The timers' register address blocks */
51 struct mn103tim_block
{
56 enum { TIMER8_BLOCK
, TIMER16_BLOCK
, NR_TIMER_BLOCKS
};
58 enum timer_register_types
{
60 TM0MD
= FIRST_MODE_REG
,
67 LAST_MODE_REG
= TM6MD
,
69 TM0BR
= FIRST_BASE_REG
,
75 LAST_BASE_REG
= TM5BR
,
77 TM0BC
= FIRST_COUNTER
,
89 LAST_TIMER_REG
= TM6BC
,
93 /* Don't include timer 6 because it's handled specially. */
94 #define NR_8BIT_TIMERS 4
95 #define NR_16BIT_TIMERS 2
96 #define NR_REG_TIMERS 6 /* Exclude timer 6 - it's handled specially. */
99 typedef struct _mn10300_timer_regs
{
102 } mn10300_timer_regs
;
104 typedef struct _mn10300_timer
{
105 unsigned32 div_ratio
, start
;
106 struct hw_event
*event
;
111 struct mn103tim_block block
[NR_TIMER_BLOCKS
];
112 mn10300_timer_regs reg
[NR_REG_TIMERS
];
113 mn10300_timer timer
[NR_TIMERS
];
115 /* treat timer 6 registers specially. */
116 unsigned16 tm6md0
, tm6md1
, tm6bc
, tm6ca
, tm6cb
;
117 unsigned8 tm6mda
, tm6mdb
; /* compare/capture mode regs for timer 6 */
120 /* output port ID's */
136 static const struct hw_port_descriptor mn103tim_ports
[] = {
138 { "timer-0-underflow", TIMER0_UFLOW
, 0, output_port
, },
139 { "timer-1-underflow", TIMER1_UFLOW
, 0, output_port
, },
140 { "timer-2-underflow", TIMER2_UFLOW
, 0, output_port
, },
141 { "timer-3-underflow", TIMER3_UFLOW
, 0, output_port
, },
142 { "timer-4-underflow", TIMER4_UFLOW
, 0, output_port
, },
143 { "timer-5-underflow", TIMER5_UFLOW
, 0, output_port
, },
145 { "timer-6-underflow", TIMER6_UFLOW
, 0, output_port
, },
146 { "timer-6-compare-a", TIMER6_CMPA
, 0, output_port
, },
147 { "timer-6-compare-b", TIMER6_CMPB
, 0, output_port
, },
152 #define bits2to5_mask 0x3c
153 #define bits0to2_mask 0x07
154 #define load_mask 0x40
155 #define count_mask 0x80
156 #define count_and_load_mask (load_mask | count_mask)
157 #define clock_mask 0x03
158 #define clk_ioclk 0x00
159 #define clk_cascaded 0x03
162 /* Finish off the partially created hw device. Attach our local
163 callbacks. Wire up our port names etc */
165 static hw_io_read_buffer_method mn103tim_io_read_buffer
;
166 static hw_io_write_buffer_method mn103tim_io_write_buffer
;
169 attach_mn103tim_regs (struct hw
*me
,
170 struct mn103tim
*timers
)
173 if (hw_find_property (me
, "reg") == NULL
)
174 hw_abort (me
, "Missing \"reg\" property");
175 for (i
= 0; i
< NR_TIMER_BLOCKS
; i
++)
177 unsigned_word attach_address
;
179 unsigned attach_size
;
180 reg_property_spec reg
;
181 if (!hw_find_reg_array_property (me
, "reg", i
, ®
))
182 hw_abort (me
, "\"reg\" property must contain three addr/size entries");
183 hw_unit_address_to_attach_address (hw_parent (me
),
188 timers
->block
[i
].base
= attach_address
;
189 hw_unit_size_to_attach_size (hw_parent (me
),
192 timers
->block
[i
].bound
= attach_address
+ (attach_size
- 1);
193 hw_attach_address (hw_parent (me
),
195 attach_space
, attach_address
, attach_size
,
201 mn103tim_finish (struct hw
*me
)
203 struct mn103tim
*timers
;
206 timers
= HW_ZALLOC (me
, struct mn103tim
);
207 set_hw_data (me
, timers
);
208 set_hw_io_read_buffer (me
, mn103tim_io_read_buffer
);
209 set_hw_io_write_buffer (me
, mn103tim_io_write_buffer
);
210 set_hw_ports (me
, mn103tim_ports
);
212 /* Attach ourself to our parent bus */
213 attach_mn103tim_regs (me
, timers
);
215 /* Initialize the timers */
216 for ( i
=0; i
< NR_REG_TIMERS
; ++i
)
218 timers
->reg
[i
].mode
= 0x00;
219 timers
->reg
[i
].base
= 0;
221 for ( i
=0; i
< NR_TIMERS
; ++i
)
223 timers
->timer
[i
].event
= NULL
;
224 timers
->timer
[i
].div_ratio
= 0;
225 timers
->timer
[i
].start
= 0;
227 timers
->tm6md0
= 0x00;
228 timers
->tm6md1
= 0x00;
229 timers
->tm6bc
= 0x0000;
230 timers
->tm6ca
= 0x0000;
231 timers
->tm6cb
= 0x0000;
232 timers
->tm6mda
= 0x00;
233 timers
->tm6mdb
= 0x00;
241 decode_addr (struct hw
*me
,
242 struct mn103tim
*timers
,
243 unsigned_word address
)
245 unsigned_word offset
;
246 offset
= address
- timers
->block
[0].base
;
250 case 0x00: return TM0MD
;
251 case 0x01: return TM1MD
;
252 case 0x02: return TM2MD
;
253 case 0x03: return TM3MD
;
254 case 0x10: return TM0BR
;
255 case 0x11: return TM1BR
;
256 case 0x12: return TM2BR
;
257 case 0x13: return TM3BR
;
258 case 0x20: return TM0BC
;
259 case 0x21: return TM1BC
;
260 case 0x22: return TM2BC
;
261 case 0x23: return TM3BC
;
262 case 0x80: return TM4MD
;
263 case 0x82: return TM5MD
;
264 case 0x84: /* fall through */
265 case 0x85: return TM6MD
;
266 case 0x90: return TM4BR
;
267 case 0x92: return TM5BR
;
268 case 0xa0: return TM4BC
;
269 case 0xa2: return TM5BC
;
270 case 0xa4: return TM6BC
;
271 case 0xb4: return TM6MDA
;
272 case 0xb5: return TM6MDB
;
273 case 0xc4: return TM6CA
;
274 case 0xd4: return TM6CB
;
277 hw_abort (me
, "bad address");
284 read_mode_reg (struct hw
*me
,
285 struct mn103tim
*timers
,
296 /* Accessing 1 byte is ok for all mode registers. */
299 *(unsigned8
*)dest
= timers
->tm6md0
;
303 *(unsigned8
*)dest
= timers
->reg
[timer_nr
].mode
;
310 *(unsigned16
*)dest
= (timers
->tm6md0
<< 8) | timers
->tm6md1
;
312 else if ( timer_nr
== 0 || timer_nr
== 2 )
314 val16
= (timers
->reg
[timer_nr
].mode
<< 8)
315 | timers
->reg
[timer_nr
+1].mode
;
316 *(unsigned16
*)dest
= val16
;
320 hw_abort (me
, "bad read size of 2 bytes to TM%dMD.", timer_nr
);
327 val32
= (timers
->reg
[0].mode
<< 24 )
328 | (timers
->reg
[1].mode
<< 16)
329 | (timers
->reg
[2].mode
<< 8)
330 | timers
->reg
[3].mode
;
331 *(unsigned32
*)dest
= val32
;
335 hw_abort (me
, "bad read size of 4 bytes to TM%dMD.", timer_nr
);
340 hw_abort (me
, "bad read size of %d bytes to TM%dMD.",
347 read_base_reg (struct hw
*me
,
348 struct mn103tim
*timers
,
356 /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
360 /* Reading 1 byte is ok for all registers. */
361 if ( timer_nr
< NR_8BIT_TIMERS
)
363 *(unsigned8
*)dest
= timers
->reg
[timer_nr
].base
;
368 if ( timer_nr
== 1 || timer_nr
== 3 )
370 hw_abort (me
, "bad read size of 2 bytes to TM%dBR.", timer_nr
);
374 if ( timer_nr
< NR_8BIT_TIMERS
)
376 val16
= (timers
->reg
[timer_nr
].base
<<8)
377 | timers
->reg
[timer_nr
+1].base
;
381 val16
= timers
->reg
[timer_nr
].base
;
383 *(unsigned16
*)dest
= val16
;
390 val32
= (timers
->reg
[0].base
<< 24) | (timers
->reg
[1].base
<< 16)
391 | (timers
->reg
[2].base
<< 8) | timers
->reg
[3].base
;
392 *(unsigned32
*)dest
= val32
;
394 else if ( timer_nr
== 4 )
396 val32
= (timers
->reg
[4].base
<< 16) | timers
->reg
[5].base
;
397 *(unsigned32
*)dest
= val32
;
401 hw_abort (me
, "bad read size of 4 bytes to TM%dBR.", timer_nr
);
406 hw_abort (me
, "bad read size must of %d bytes to TM%dBR.",
413 read_counter (struct hw
*me
,
414 struct mn103tim
*timers
,
421 if ( NULL
== timers
->timer
[timer_nr
].event
)
423 /* Timer is not counting, use value in base register. */
426 val
= 0; /* timer 6 is an up counter */
430 val
= timers
->reg
[timer_nr
].base
;
435 if ( timer_nr
== 6 ) /* timer 6 is an up counter. */
437 val
= hw_event_queue_time(me
) - timers
->timer
[timer_nr
].start
;
441 /* ticks left = start time + div ratio - curr time */
442 /* Cannot use base register because it can be written during counting and it
443 doesn't affect counter until underflow occurs. */
445 val
= timers
->timer
[timer_nr
].start
+ timers
->timer
[timer_nr
].div_ratio
446 - hw_event_queue_time(me
);
452 *(unsigned8
*)dest
= val
;
456 *(unsigned16
*)dest
= val
;
460 *(unsigned32
*)dest
= val
;
464 hw_abort(me
, "bad read size for reading counter");
471 read_special_timer6_reg (struct hw
*me
,
472 struct mn103tim
*timers
,
482 switch ( timer_nr
) {
484 *(unsigned8
*)dest
= timers
->tm6mda
;
488 *(unsigned8
*)dest
= timers
->tm6mdb
;
492 *(unsigned8
*)dest
= timers
->tm6ca
;
496 *(unsigned8
*)dest
= timers
->tm6cb
;
506 if ( timer_nr
== TM6CA
)
508 *(unsigned16
*)dest
= timers
->tm6ca
;
510 else if ( timer_nr
== TM6CB
)
512 *(unsigned16
*)dest
= timers
->tm6cb
;
516 hw_abort(me
, "bad read size for timer 6 mode A/B register");
521 hw_abort(me
, "bad read size for timer 6 register");
528 mn103tim_io_read_buffer (struct hw
*me
,
534 struct mn103tim
*timers
= hw_data (me
);
535 enum timer_register_types timer_reg
;
537 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
539 timer_reg
= decode_addr (me
, timers
, base
);
541 /* It can be either a mode register, a base register, a binary counter, */
542 /* or a special timer 6 register. Check in that order. */
543 if ( timer_reg
>= FIRST_MODE_REG
&& timer_reg
<= LAST_MODE_REG
)
545 read_mode_reg(me
, timers
, timer_reg
-FIRST_MODE_REG
, dest
, nr_bytes
);
547 else if ( timer_reg
<= LAST_BASE_REG
)
549 read_base_reg(me
, timers
, timer_reg
-FIRST_BASE_REG
, dest
, nr_bytes
);
551 else if ( timer_reg
<= LAST_COUNTER
)
553 read_counter(me
, timers
, timer_reg
-FIRST_COUNTER
, dest
, nr_bytes
);
555 else if ( timer_reg
<= LAST_TIMER_REG
)
557 read_special_timer6_reg(me
, timers
, timer_reg
, dest
, nr_bytes
);
561 hw_abort(me
, "invalid timer register address.");
569 do_counter_event (struct hw
*me
,
572 struct mn103tim
*timers
= hw_data(me
);
573 long timer_nr
= (long) data
;
576 /* Check if counting is still enabled. */
577 if ( (timers
->reg
[timer_nr
].mode
& count_mask
) != 0 )
579 /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
581 /* Port event occurs on port of last cascaded timer. */
582 /* This works across timer range from 0 to NR_REG_TIMERS because */
583 /* the first 16 bit timer (timer 4) is not allowed to be set as */
584 /* a cascading timer. */
585 for ( next_timer
= timer_nr
+1; next_timer
< NR_REG_TIMERS
; ++next_timer
)
587 if ( (timers
->reg
[next_timer
].mode
& clock_mask
) != clk_cascaded
)
592 hw_port_event (me
, next_timer
-1, 1);
594 /* Schedule next timeout. */
595 timers
->timer
[timer_nr
].start
= hw_event_queue_time(me
);
596 /* FIX: Check if div_ratio has changed and if it's now 0. */
597 timers
->timer
[timer_nr
].event
598 = hw_event_queue_schedule (me
, timers
->timer
[timer_nr
].div_ratio
,
599 do_counter_event
, (void *)timer_nr
);
603 timers
->timer
[timer_nr
].event
= NULL
;
610 do_counter6_event (struct hw
*me
,
613 struct mn103tim
*timers
= hw_data(me
);
614 long timer_nr
= (long) data
;
617 /* Check if counting is still enabled. */
618 if ( (timers
->reg
[timer_nr
].mode
& count_mask
) != 0 )
620 /* Generate an interrupt for the timer underflow (TIMERn_UFLOW). */
621 hw_port_event (me
, timer_nr
, 1);
623 /* Schedule next timeout. */
624 timers
->timer
[timer_nr
].start
= hw_event_queue_time(me
);
625 /* FIX: Check if div_ratio has changed and if it's now 0. */
626 timers
->timer
[timer_nr
].event
627 = hw_event_queue_schedule (me
, timers
->timer
[timer_nr
].div_ratio
,
628 do_counter6_event
, (void *)timer_nr
);
632 timers
->timer
[timer_nr
].event
= NULL
;
638 write_base_reg (struct hw
*me
,
639 struct mn103tim
*timers
,
645 const unsigned8
*buf8
= source
;
646 const unsigned16
*buf16
= source
;
648 /* If TMnCNE == 0 (counting is off), writing to the base register
649 (TMnBR) causes a simultaneous write to the counter reg (TMnBC).
650 Else, the TMnBC is reloaded with the value from TMnBR when
651 underflow occurs. Since the counter register is not explicitly
652 maintained, this functionality is handled in read_counter. */
654 /* Check nr_bytes: write of 1, 2 or 4 bytes allowed depending on timer. */
658 /* Storing 1 byte is ok for all registers. */
659 timers
->reg
[timer_nr
].base
= buf8
[0];
663 if ( timer_nr
== 1 || timer_nr
== 3 )
665 hw_abort (me
, "bad write size of 2 bytes to TM%dBR.", timer_nr
);
669 if ( timer_nr
< NR_8BIT_TIMERS
)
671 timers
->reg
[timer_nr
].base
= buf8
[0];
672 timers
->reg
[timer_nr
+1].base
= buf8
[1];
676 timers
->reg
[timer_nr
].base
= buf16
[0];
684 timers
->reg
[0].base
= buf8
[0];
685 timers
->reg
[1].base
= buf8
[1];
686 timers
->reg
[2].base
= buf8
[2];
687 timers
->reg
[3].base
= buf8
[3];
689 else if ( timer_nr
== 4 )
691 timers
->reg
[4].base
= buf16
[0];
692 timers
->reg
[5].base
= buf16
[1];
696 hw_abort (me
, "bad write size of 4 bytes to TM%dBR.", timer_nr
);
701 hw_abort (me
, "bad write size must of %d bytes to TM%dBR.",
708 write_mode_reg (struct hw
*me
,
709 struct mn103tim
*timers
,
713 /* for timers 0 to 5 */
716 unsigned8 mode_val
, next_mode_val
;
717 unsigned32 div_ratio
;
721 hw_abort (me
, "bad write size of %d bytes to TM%ldMD.", nr_bytes
,
725 mode_val
= *(unsigned8
*)source
;
726 timers
->reg
[timer_nr
].mode
= mode_val
;
728 if ( ( mode_val
& count_and_load_mask
) == count_and_load_mask
)
730 hw_abort(me
, "Cannot load base reg and start counting simultaneously.");
732 if ( ( mode_val
& bits2to5_mask
) != 0 )
734 hw_abort(me
, "Cannot write to bits 2 to 5 of mode register");
737 if ( mode_val
& count_mask
)
739 /* - de-schedule any previous event. */
740 /* - add new event to queue to start counting. */
741 /* - assert that counter == base reg? */
743 /* For cascaded timers, */
744 if ( (mode_val
& clock_mask
) == clk_cascaded
)
746 if ( timer_nr
== 0 || timer_nr
== 4 )
748 hw_abort(me
, "Timer %ld cannot be cascaded.", timer_nr
);
753 div_ratio
= timers
->reg
[timer_nr
].base
;
755 /* Check for cascading. */
756 if ( timer_nr
< NR_8BIT_TIMERS
)
758 for ( i
= timer_nr
+ 1; i
<= 3; ++i
)
760 next_mode_val
= timers
->reg
[i
].mode
;
761 if ( ( next_mode_val
& clock_mask
) == clk_cascaded
)
763 /* Check that CNE is on. */
764 if ( ( next_mode_val
& count_mask
) == 0 )
766 hw_abort (me
, "cascaded timer not ready for counting");
768 ASSERT(timers
->timer
[i
].event
== NULL
);
769 ASSERT(timers
->timer
[i
].div_ratio
== 0);
770 div_ratio
= div_ratio
771 | (timers
->reg
[i
].base
<< (8*(i
-timer_nr
)));
781 /* Mode register for a 16 bit timer */
782 next_mode_val
= timers
->reg
[timer_nr
+1].mode
;
783 if ( ( next_mode_val
& clock_mask
) == clk_cascaded
)
785 /* Check that CNE is on. */
786 if ( ( next_mode_val
& count_mask
) == 0 )
788 hw_abort (me
, "cascaded timer not ready for counting");
790 ASSERT(timers
->timer
[timer_nr
+1].event
== NULL
);
791 ASSERT(timers
->timer
[timer_nr
+1].div_ratio
== 0);
792 div_ratio
= div_ratio
| (timers
->reg
[timer_nr
+1].base
<< 16);
796 timers
->timer
[timer_nr
].div_ratio
= div_ratio
;
798 if ( NULL
!= timers
->timer
[timer_nr
].event
)
800 hw_event_queue_deschedule (me
, timers
->timer
[timer_nr
].event
);
801 timers
->timer
[timer_nr
].event
= NULL
;
806 /* Set start time. */
807 timers
->timer
[timer_nr
].start
= hw_event_queue_time(me
);
808 timers
->timer
[timer_nr
].event
809 = hw_event_queue_schedule(me
, div_ratio
,
817 /* Turn off counting */
818 if ( NULL
!= timers
->timer
[timer_nr
].event
)
820 ASSERT((timers
->reg
[timer_nr
].mode
& clock_mask
) != clk_cascaded
);
821 hw_event_queue_deschedule (me
, timers
->timer
[timer_nr
].event
);
822 timers
->timer
[timer_nr
].event
= NULL
;
826 if ( (timers
->reg
[timer_nr
].mode
& clock_mask
) == clk_cascaded
)
828 ASSERT(timers
->timer
[timer_nr
].event
== NULL
);
837 write_tm6md (struct hw
*me
,
838 struct mn103tim
*timers
,
839 unsigned_word address
,
843 unsigned8 mode_val0
= 0x00, mode_val1
= 0x00;
844 unsigned32 div_ratio
;
847 unsigned_word offset
= address
- timers
->block
[0].base
;
849 if ((offset
!= 0x84 && nr_bytes
> 1) || nr_bytes
> 2 )
851 hw_abort (me
, "Bad write size of %d bytes to TM6MD", nr_bytes
);
854 if ( offset
== 0x84 ) /* address of TM6MD */
856 /* Fill in first byte of mode */
857 mode_val0
= *(unsigned8
*)source
;
858 timers
->tm6md0
= mode_val0
;
860 if ( ( mode_val0
& 0x26 ) != 0 )
862 hw_abort(me
, "Cannot write to bits 5, 3, and 2 of TM6MD");
866 if ( offset
== 0x85 || nr_bytes
== 2 )
868 /* Fill in second byte of mode */
871 mode_val1
= *(unsigned8
*)source
+1;
875 mode_val1
= *(unsigned8
*)source
;
878 timers
->tm6md1
= mode_val1
;
880 if ( ( mode_val1
& count_and_load_mask
) == count_and_load_mask
)
882 hw_abort(me
, "Cannot load base reg and start counting simultaneously.");
884 if ( ( mode_val1
& bits0to2_mask
) != 0 )
886 hw_abort(me
, "Cannot write to bits 8 to 10 of TM6MD");
890 if ( mode_val1
& count_mask
)
892 /* - de-schedule any previous event. */
893 /* - add new event to queue to start counting. */
894 /* - assert that counter == base reg? */
896 div_ratio
= timers
->tm6ca
; /* binary counter for timer 6 */
897 timers
->timer
[timer_nr
].div_ratio
= div_ratio
;
898 if ( NULL
!= timers
->timer
[timer_nr
].event
)
900 hw_event_queue_deschedule (me
, timers
->timer
[timer_nr
].event
);
901 timers
->timer
[timer_nr
].event
= NULL
;
906 /* Set start time. */
907 timers
->timer
[timer_nr
].start
= hw_event_queue_time(me
);
908 timers
->timer
[timer_nr
].event
909 = hw_event_queue_schedule(me
, div_ratio
,
916 /* Turn off counting */
917 if ( NULL
!= timers
->timer
[timer_nr
].event
)
919 hw_event_queue_deschedule (me
, timers
->timer
[timer_nr
].event
);
920 timers
->timer
[timer_nr
].event
= NULL
;
928 write_special_timer6_reg (struct hw
*me
,
929 struct mn103tim
*timers
,
939 switch ( timer_nr
) {
941 timers
->tm6mda
= *(unsigned8
*)source
;
945 timers
->tm6mdb
= *(unsigned8
*)source
;
949 timers
->tm6ca
= *(unsigned8
*)source
;
953 timers
->tm6cb
= *(unsigned8
*)source
;
963 if ( timer_nr
== TM6CA
)
965 timers
->tm6ca
= *(unsigned16
*)source
;
967 else if ( timer_nr
== TM6CB
)
969 timers
->tm6cb
= *(unsigned16
*)source
;
973 hw_abort(me
, "bad read size for timer 6 mode A/B register");
978 hw_abort(me
, "bad read size for timer 6 register");
985 mn103tim_io_write_buffer (struct hw
*me
,
991 struct mn103tim
*timers
= hw_data (me
);
992 enum timer_register_types timer_reg
;
994 HW_TRACE ((me
, "write to 0x%08lx length %d with 0x%x", (long) base
,
995 (int) nr_bytes
, *(unsigned32
*)source
));
997 timer_reg
= decode_addr (me
, timers
, base
);
999 /* It can be either a mode register, a base register, a binary counter, */
1000 /* or a special timer 6 register. Check in that order. */
1001 if ( timer_reg
<= LAST_MODE_REG
)
1003 if ( timer_reg
== 6 )
1005 write_tm6md(me
, timers
, base
, source
, nr_bytes
);
1009 write_mode_reg(me
, timers
, timer_reg
-FIRST_MODE_REG
,
1013 else if ( timer_reg
<= LAST_BASE_REG
)
1015 write_base_reg(me
, timers
, timer_reg
-FIRST_BASE_REG
, source
, nr_bytes
);
1017 else if ( timer_reg
<= LAST_COUNTER
)
1019 hw_abort(me
, "cannot write to counter");
1021 else if ( timer_reg
<= LAST_TIMER_REG
)
1023 write_special_timer6_reg(me
, timers
, timer_reg
, source
, nr_bytes
);
1027 hw_abort(me
, "invalid reg type");
1034 const struct hw_descriptor dv_mn103tim_descriptor
[] = {
1035 { "mn103tim", mn103tim_finish
, },