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git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/mn10300/op_utils.c
1 /* This must come before any other includes. */
5 #include "sim-syscall.h"
18 #define REG0(X) ((X) & 0x3)
19 #define REG1(X) (((X) & 0xc) >> 2)
20 #define REG0_4(X) (((X) & 0x30) >> 4)
21 #define REG0_8(X) (((X) & 0x300) >> 8)
22 #define REG1_8(X) (((X) & 0xc00) >> 10)
23 #define REG0_16(X) (((X) & 0x30000) >> 16)
24 #define REG1_16(X) (((X) & 0xc0000) >> 18)
27 INLINE_SIM_MAIN (void)
28 genericAdd(unsigned32 source
, unsigned32 destReg
)
33 dest
= State
.regs
[destReg
];
35 State
.regs
[destReg
] = sum
;
38 n
= (sum
& 0x80000000);
39 c
= (sum
< source
) || (sum
< dest
);
40 v
= ((dest
& 0x80000000) == (source
& 0x80000000)
41 && (dest
& 0x80000000) != (sum
& 0x80000000));
43 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
44 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
45 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
51 INLINE_SIM_MAIN (void)
52 genericSub(unsigned32 source
, unsigned32 destReg
)
55 unsigned32 dest
, difference
;
57 dest
= State
.regs
[destReg
];
58 difference
= dest
- source
;
59 State
.regs
[destReg
] = difference
;
61 z
= (difference
== 0);
62 n
= (difference
& 0x80000000);
64 v
= ((dest
& 0x80000000) != (source
& 0x80000000)
65 && (dest
& 0x80000000) != (difference
& 0x80000000));
67 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
68 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
69 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
72 INLINE_SIM_MAIN (void)
73 genericCmp(unsigned32 leftOpnd
, unsigned32 rightOpnd
)
78 value
= rightOpnd
- leftOpnd
;
81 n
= (value
& 0x80000000);
82 c
= (leftOpnd
> rightOpnd
);
83 v
= ((rightOpnd
& 0x80000000) != (leftOpnd
& 0x80000000)
84 && (rightOpnd
& 0x80000000) != (value
& 0x80000000));
86 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
87 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
88 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
92 INLINE_SIM_MAIN (void)
93 genericOr(unsigned32 source
, unsigned32 destReg
)
97 State
.regs
[destReg
] |= source
;
98 z
= (State
.regs
[destReg
] == 0);
99 n
= (State
.regs
[destReg
] & 0x80000000) != 0;
100 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
101 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
105 INLINE_SIM_MAIN (void)
106 genericXor(unsigned32 source
, unsigned32 destReg
)
110 State
.regs
[destReg
] ^= source
;
111 z
= (State
.regs
[destReg
] == 0);
112 n
= (State
.regs
[destReg
] & 0x80000000) != 0;
113 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
114 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
118 INLINE_SIM_MAIN (void)
119 genericBtst(unsigned32 leftOpnd
, unsigned32 rightOpnd
)
126 n
= (temp
& 0x80000000) != 0;
128 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
129 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
133 INLINE_SIM_MAIN (void)
136 /* Registers passed to trap 0. */
138 /* Function number. */
139 reg_t func
= State
.regs
[0];
141 reg_t parm1
= State
.regs
[1];
142 reg_t parm2
= load_word (State
.regs
[REG_SP
] + 12);
143 reg_t parm3
= load_word (State
.regs
[REG_SP
] + 16);
144 reg_t parm4
= load_word (State
.regs
[REG_SP
] + 20);
146 /* We use this for simulated system calls; we may need to change
147 it to a reserved instruction if we conflict with uses at
149 int save_errno
= errno
;
152 if (func
== TARGET_SYS_exit
)
154 /* EXIT - caller can look in parm1 to work out the reason */
155 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
156 (parm1
== 0xdead ? SIM_SIGABRT
: sim_exited
), parm1
);
160 long result
, result2
;
163 sim_syscall_multi (STATE_CPU (simulator
, 0), func
, parm1
, parm2
,
164 parm3
, parm4
, &result
, &result2
, &errcode
);
166 /* Registers set by trap 0. */
167 State
.regs
[0] = errcode
;
168 State
.regs
[1] = result
;