1 /* Simulator for TI MSP430 and MSP430X
3 Copyright (C) 2013-2024 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 /* This must come before any other includes. */
31 #include "opcode/msp430-decode.h"
33 #include "sim-options.h"
34 #include "sim-signal.h"
35 #include "sim-syscall.h"
36 #include "msp430-sim.h"
39 msp430_pc_fetch (SIM_CPU
*cpu
)
41 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
43 return msp430_cpu
->regs
[0];
47 msp430_pc_store (SIM_CPU
*cpu
, sim_cia newpc
)
49 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
51 msp430_cpu
->regs
[0] = newpc
;
55 msp430_reg_fetch (SIM_CPU
*cpu
, int regno
, void *buf
, int len
)
57 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
58 unsigned char *memory
= buf
;
60 if (0 <= regno
&& regno
< 16)
64 int val
= msp430_cpu
->regs
[regno
];
65 memory
[0] = val
& 0xff;
66 memory
[1] = (val
>> 8) & 0xff;
71 int val
= msp430_cpu
->regs
[regno
];
72 memory
[0] = val
& 0xff;
73 memory
[1] = (val
>> 8) & 0xff;
74 memory
[2] = (val
>> 16) & 0x0f; /* Registers are only 20 bits wide. */
86 msp430_reg_store (SIM_CPU
*cpu
, int regno
, const void *buf
, int len
)
88 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
89 const unsigned char *memory
= buf
;
91 if (0 <= regno
&& regno
< 16)
95 msp430_cpu
->regs
[regno
] = (memory
[1] << 8) | memory
[0];
101 msp430_cpu
->regs
[regno
] = ((memory
[2] << 16) & 0xf0000)
102 | (memory
[1] << 8) | memory
[0];
111 sim_open (SIM_OPEN_KIND kind
,
112 struct host_callback_struct
*callback
,
116 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
117 struct msp430_cpu_state
*msp430_cpu
;
121 /* Initialise the simulator. */
123 /* Set default options before parsing user options. */
124 current_target_byte_order
= BFD_ENDIAN_LITTLE
;
126 if (sim_cpu_alloc_all_extra (sd
, 0, sizeof (struct msp430_cpu_state
))
133 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
139 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
145 /* Allocate memory if none specified by user.
146 Note - these values match the memory regions in the libgloss/msp430/msp430[xl]-sim.ld scripts. */
147 if (sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, &c
, 0x2, 1) == 0)
148 sim_do_commandf (sd
, "memory-region 0,0x20"); /* Needed by the GDB testsuite. */
149 if (sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, &c
, 0x500, 1) == 0)
150 sim_do_commandf (sd
, "memory-region 0x500,0xfac0"); /* RAM and/or ROM */
151 if (sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, &c
, 0xfffe, 1) == 0)
152 sim_do_commandf (sd
, "memory-region 0xffc0,0x40"); /* VECTORS. */
153 if (sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, &c
, 0x10000, 1) == 0)
154 sim_do_commandf (sd
, "memory-region 0x10000,0x80000"); /* HIGH FLASH RAM. */
155 if (sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, &c
, 0x90000, 1) == 0)
156 sim_do_commandf (sd
, "memory-region 0x90000,0x70000"); /* HIGH ROM. */
158 /* Check for/establish the a reference program image. */
159 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
165 /* Establish any remaining configuration options. */
166 if (sim_config (sd
) != SIM_RC_OK
)
172 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
178 /* CPU specific initialization. */
179 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
181 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
183 CPU_PC_FETCH (cpu
) = msp430_pc_fetch
;
184 CPU_PC_STORE (cpu
) = msp430_pc_store
;
185 CPU_REG_FETCH (cpu
) = msp430_reg_fetch
;
186 CPU_REG_STORE (cpu
) = msp430_reg_store
;
188 msp430_cpu
= MSP430_SIM_CPU (cpu
);
189 msp430_cpu
->cio_breakpoint
= trace_sym_value (sd
, "C$$IO$$");
190 msp430_cpu
->cio_buffer
= trace_sym_value (sd
, "__CIOBUF__");
191 if (msp430_cpu
->cio_buffer
== -1)
192 msp430_cpu
->cio_buffer
= trace_sym_value (sd
, "_CIOBUF_");
199 sim_create_inferior (SIM_DESC sd
,
204 unsigned char resetv
[2];
207 /* Set the PC to the default reset vector if available. */
208 sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, resetv
, 0xfffe, 2);
209 new_pc
= resetv
[0] + 256 * resetv
[1];
211 /* If the reset vector isn't initialized, then use the ELF entry. */
212 if (abfd
!= NULL
&& !new_pc
)
213 new_pc
= bfd_get_start_address (abfd
);
215 sim_pc_set (STATE_CPU (sd
, 0), new_pc
);
216 msp430_pc_store (STATE_CPU (sd
, 0), new_pc
);
225 } Get_Byte_Local_Data
;
228 msp430_getbyte (void *vld
)
230 Get_Byte_Local_Data
*ld
= (Get_Byte_Local_Data
*)vld
;
232 SIM_DESC sd
= ld
->sd
;
234 sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, buf
, ld
->gb_addr
, 1);
239 #define REG(N) MSP430_SIM_CPU (STATE_CPU (sd, 0))->regs[N]
240 #define PC REG(MSR_PC)
241 #define SP REG(MSR_SP)
242 #define SR REG(MSR_SR)
247 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
248 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
252 trace_reg_put (SIM_DESC sd
, int n
, unsigned int v
)
254 TRACE_REGISTER (STATE_CPU (sd
, 0), "PUT: %#x -> %s", v
, register_names
[n
]);
259 trace_reg_get (SIM_DESC sd
, int n
)
261 TRACE_REGISTER (STATE_CPU (sd
, 0), "GET: %s -> %#x", register_names
[n
], REG (n
));
265 #define REG_PUT(N,V) trace_reg_put (sd, N, V)
266 #define REG_GET(N) trace_reg_get (sd, N)
268 /* Hardware multiply (and accumulate) support. */
271 zero_ext (unsigned int v
, unsigned int bits
)
273 v
&= ((1 << bits
) - 1);
277 static signed long long
278 sign_ext (signed long long v
, unsigned int bits
)
280 signed long long sb
= 1LL << (bits
-1); /* Sign bit. */
281 signed long long mb
= (1LL << (bits
-1)) - 1LL; /* Mantissa bits. */
291 get_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
)
293 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
296 unsigned char buf
[4];
301 case MSP430_Operand_Immediate
:
304 case MSP430_Operand_Register
:
305 rv
= REG_GET (op
->reg
);
307 case MSP430_Operand_Indirect
:
308 case MSP430_Operand_Indirect_Postinc
:
310 if (op
->reg
!= MSR_None
)
312 int reg
= REG_GET (op
->reg
);
313 int sign
= opc
->ofs_430x
? 20 : 16;
315 /* Index values are signed. */
316 if (addr
& (1 << (sign
- 1)))
317 addr
|= -(1 << sign
);
321 /* For MSP430 instructions the sum is limited to 16 bits if the
322 address in the index register is less than 64k even if we are
323 running on an MSP430X CPU. This is for MSP430 compatibility. */
324 if (reg
< 0x10000 && ! opc
->ofs_430x
)
327 fprintf (stderr
, " XXX WRAPPING ADDRESS %x on read\n", addr
);
336 sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, buf
, addr
, 1);
340 sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, buf
, addr
, 2);
341 rv
= buf
[0] | (buf
[1] << 8);
345 sim_core_read_buffer (sd
, STATE_CPU (sd
, 0), read_map
, buf
, addr
, 4);
346 rv
= buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
349 assert (! opc
->size
);
353 /* Hack - MSP430X5438 serial port status register. */
357 if ((addr
>= 0x130 && addr
<= 0x15B)
358 || (addr
>= 0x4C0 && addr
<= 0x4EB))
364 switch (HWMULT (sd
, hwmult_type
))
368 rv
= zero_ext (HWMULT (sd
, hwmult_result
), 16);
372 rv
= sign_ext (HWMULT (sd
, hwmult_signed_result
), 16);
379 switch (HWMULT (sd
, hwmult_type
))
383 rv
= zero_ext (HWMULT (sd
, hwmult_result
) >> 16, 16);
388 rv
= sign_ext (HWMULT (sd
, hwmult_signed_result
) >> 16, 16);
395 switch (HWMULT (sd
, hwmult_type
))
401 rv
= HWMULT (sd
, hwmult_signed_result
) < 0 ? -1 : 0;
404 rv
= 0; /* FIXME: Should be carry of last accumulate. */
407 rv
= HWMULT (sd
, hwmult_signed_accumulator
) < 0 ? -1 : 0;
414 rv
= zero_ext (HWMULT (sd
, hw32mult_result
), 16);
419 rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 16, 16);
424 rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 32, 16);
429 switch (HWMULT (sd
, hw32mult_type
))
431 case UNSIGN_64
: rv
= zero_ext (HWMULT (sd
, hw32mult_result
) >> 48, 16); break;
432 case SIGN_64
: rv
= sign_ext (HWMULT (sd
, hw32mult_result
) >> 48, 16); break;
437 fprintf (stderr
, "unimplemented HW MULT read from %x!\n", addr
);
442 TRACE_MEMORY (STATE_CPU (sd
, 0), "GET: [%#x].%d -> %#x", addr
, opc
->size
,
447 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
471 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
472 REG_PUT (op
->reg
, REG_GET (op
->reg
) + incval
);
478 put_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
, int val
)
480 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
483 unsigned char buf
[4];
504 case MSP430_Operand_Register
:
506 REG_PUT (op
->reg
, val
);
508 case MSP430_Operand_Indirect
:
509 case MSP430_Operand_Indirect_Postinc
:
511 if (op
->reg
!= MSR_None
)
513 int reg
= REG_GET (op
->reg
);
514 int sign
= opc
->ofs_430x
? 20 : 16;
516 /* Index values are signed. */
517 if (addr
& (1 << (sign
- 1)))
518 addr
|= -(1 << sign
);
522 /* For MSP430 instructions the sum is limited to 16 bits if the
523 address in the index register is less than 64k even if we are
524 running on an MSP430X CPU. This is for MSP430 compatibility. */
525 if (reg
< 0x10000 && ! opc
->ofs_430x
)
528 fprintf (stderr
, " XXX WRAPPING ADDRESS %x on write\n", addr
);
535 TRACE_MEMORY (STATE_CPU (sd
, 0), "PUT: [%#x].%d <- %#x", addr
, opc
->size
,
538 /* Hack - MSP430X5438 serial port transmit register. */
542 if ((addr
>= 0x130 && addr
<= 0x15B)
543 || (addr
>= 0x4C0 && addr
<= 0x4EB))
547 /* Hardware Multiply emulation. */
548 assert (opc
->size
== 16);
554 HWMULT (sd
, hwmult_op1
) = val
;
555 HWMULT (sd
, hwmult_type
) = UNSIGN_32
;
560 HWMULT (sd
, hwmult_op1
) = val
;
561 HWMULT (sd
, hwmult_type
) = SIGN_32
;
566 HWMULT (sd
, hwmult_op1
) = val
;
567 HWMULT (sd
, hwmult_type
) = UNSIGN_MAC_32
;
572 HWMULT (sd
, hwmult_op1
) = val
;
573 HWMULT (sd
, hwmult_type
) = SIGN_MAC_32
;
578 HWMULT (sd
, hwmult_op2
) = val
;
579 switch (HWMULT (sd
, hwmult_type
))
582 a
= HWMULT (sd
, hwmult_op1
);
583 b
= HWMULT (sd
, hwmult_op2
);
584 /* For unsigned 32-bit multiplication of 16-bit operands, an
585 explicit cast is required to prevent any implicit
587 HWMULT (sd
, hwmult_result
) = (uint32_t) a
* (uint32_t) b
;
588 HWMULT (sd
, hwmult_signed_result
) = a
* b
;
589 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_signed_accumulator
) = 0;
593 a
= sign_ext (HWMULT (sd
, hwmult_op1
), 16);
594 b
= sign_ext (HWMULT (sd
, hwmult_op2
), 16);
595 HWMULT (sd
, hwmult_signed_result
) = a
* b
;
596 HWMULT (sd
, hwmult_result
) = (uint32_t) a
* (uint32_t) b
;
597 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_signed_accumulator
) = 0;
601 a
= HWMULT (sd
, hwmult_op1
);
602 b
= HWMULT (sd
, hwmult_op2
);
603 HWMULT (sd
, hwmult_accumulator
)
604 += (uint32_t) a
* (uint32_t) b
;
605 HWMULT (sd
, hwmult_signed_accumulator
) += a
* b
;
606 HWMULT (sd
, hwmult_result
) = HWMULT (sd
, hwmult_accumulator
);
607 HWMULT (sd
, hwmult_signed_result
) = HWMULT (sd
, hwmult_signed_accumulator
);
611 a
= sign_ext (HWMULT (sd
, hwmult_op1
), 16);
612 b
= sign_ext (HWMULT (sd
, hwmult_op2
), 16);
613 HWMULT (sd
, hwmult_accumulator
)
614 += (uint32_t) a
* (uint32_t) b
;
615 HWMULT (sd
, hwmult_signed_accumulator
) += a
* b
;
616 HWMULT (sd
, hwmult_result
) = HWMULT (sd
, hwmult_accumulator
);
617 HWMULT (sd
, hwmult_signed_result
) = HWMULT (sd
, hwmult_signed_accumulator
);
624 /* Copy into LOW result... */
625 switch (HWMULT (sd
, hwmult_type
))
629 HWMULT (sd
, hwmult_accumulator
) = HWMULT (sd
, hwmult_result
) = zero_ext (val
, 16);
630 HWMULT (sd
, hwmult_signed_accumulator
) = sign_ext (val
, 16);
634 HWMULT (sd
, hwmult_signed_accumulator
) = HWMULT (sd
, hwmult_result
) = sign_ext (val
, 16);
635 HWMULT (sd
, hwmult_accumulator
) = zero_ext (val
, 16);
642 HWMULT (sd
, hw32mult_op1
) = val
;
643 HWMULT (sd
, hw32mult_type
) = UNSIGN_64
;
648 HWMULT (sd
, hw32mult_op1
) = (HWMULT (sd
, hw32mult_op1
) & 0xFFFF) | (val
<< 16);
653 HWMULT (sd
, hw32mult_op1
) = val
;
654 HWMULT (sd
, hw32mult_type
) = SIGN_64
;
659 HWMULT (sd
, hw32mult_op1
) = (HWMULT (sd
, hw32mult_op1
) & 0xFFFF) | (val
<< 16);
664 HWMULT (sd
, hw32mult_op2
) = val
;
669 HWMULT (sd
, hw32mult_op2
) = (HWMULT (sd
, hw32mult_op2
) & 0xFFFF) | (val
<< 16);
670 switch (HWMULT (sd
, hw32mult_type
))
673 HWMULT (sd
, hw32mult_result
)
674 = (uint64_t) HWMULT (sd
, hw32mult_op1
)
675 * (uint64_t) HWMULT (sd
, hw32mult_op2
);
678 HWMULT (sd
, hw32mult_result
)
679 = sign_ext (HWMULT (sd
, hw32mult_op1
), 32)
680 * sign_ext (HWMULT (sd
, hw32mult_op2
), 32);
686 fprintf (stderr
, "unimplemented HW MULT write to %x!\n", addr
);
695 sim_core_write_buffer (sd
, STATE_CPU (sd
, 0), write_map
, buf
, addr
, 1);
700 sim_core_write_buffer (sd
, STATE_CPU (sd
, 0), write_map
, buf
, addr
, 2);
708 sim_core_write_buffer (sd
, STATE_CPU (sd
, 0), write_map
, buf
, addr
, 4);
711 assert (! opc
->size
);
716 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
740 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
742 int new_val
= REG_GET (op
->reg
) + incval
;
743 /* SP is always word-aligned. */
744 if (op
->reg
== MSR_SP
&& (new_val
& 1))
746 REG_PUT (op
->reg
, new_val
);
753 mem_put_val (SIM_DESC sd
, int addr
, int val
, int bits
)
755 MSP430_Opcode_Decoded opc
;
758 opc
.op
[0].type
= MSP430_Operand_Indirect
;
759 opc
.op
[0].addend
= addr
;
760 opc
.op
[0].reg
= MSR_None
;
761 put_op (sd
, &opc
, 0, val
);
765 mem_get_val (SIM_DESC sd
, int addr
, int bits
)
767 MSP430_Opcode_Decoded opc
;
770 opc
.op
[0].type
= MSP430_Operand_Indirect
;
771 opc
.op
[0].addend
= addr
;
772 opc
.op
[0].reg
= MSR_None
;
773 return get_op (sd
, &opc
, 0);
776 #define CIO_OPEN (0xF0)
777 #define CIO_CLOSE (0xF1)
778 #define CIO_READ (0xF2)
779 #define CIO_WRITE (0xF3)
780 #define CIO_LSEEK (0xF4)
781 #define CIO_UNLINK (0xF5)
782 #define CIO_GETENV (0xF6)
783 #define CIO_RENAME (0xF7)
784 #define CIO_GETTIME (0xF8)
785 #define CIO_GETCLK (0xF9)
786 #define CIO_SYNC (0xFF)
788 #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
789 #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
790 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
793 msp430_cio (SIM_DESC sd
)
795 /* A block of data at __CIOBUF__ describes the I/O operation to
797 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
798 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
799 unsigned char parms
[8];
802 unsigned char buffer
[512];
806 sim_core_read_buffer (sd
, cpu
, 0, parms
, msp430_cpu
->cio_buffer
, 5);
810 sim_core_read_buffer (sd
, cpu
, 0, parms
, msp430_cpu
->cio_buffer
+ 3, 8);
811 sim_core_read_buffer (sd
, cpu
, 0, buffer
, msp430_cpu
->cio_buffer
+ 11, length
);
819 rv
= write (fd
, buffer
, len
);
820 parms
[0] = rv
& 0xff;
826 sim_core_write_buffer (sd
, cpu
, 0, parms
, msp430_cpu
->cio_buffer
+ 4, 8);
828 sim_core_write_buffer (sd
, cpu
, 0, buffer
, msp430_cpu
->cio_buffer
+ 12,
832 #define SRC get_op (sd, opcode, 1)
833 #define DSRC get_op (sd, opcode, 0)
834 #define DEST(V) put_op (sd, opcode, 0, (V))
836 #define DO_ALU(OP,SOP,MORE) \
840 int result = s1 OP s2 MORE; \
841 TRACE_ALU (STATE_CPU (sd, 0), "ALU: %#x %s %#x %s = %#x", s1, SOP, \
842 s2, #MORE, result); \
846 #define SIGN (1 << (opcode->size - 1))
847 #define POS(x) (((x) & SIGN) ? 0 : 1)
848 #define NEG(x) (((x) & SIGN) ? 1 : 0)
850 #define SX(v) sign_ext (v, opcode->size)
851 #define ZX(v) zero_ext (v, opcode->size)
856 static char buf
[2][6];
862 bp
[0] = f
& MSP430_FLAG_V
? 'V' : '-';
863 bp
[1] = f
& MSP430_FLAG_N
? 'N' : '-';
864 bp
[2] = f
& MSP430_FLAG_Z
? 'Z' : '-';
865 bp
[3] = f
& MSP430_FLAG_C
? 'C' : '-';
870 /* Random number that won't show up in our usual logic. */
871 #define MAGIC_OVERFLOW 0x55000F
874 do_flags (SIM_DESC sd
,
875 MSP430_Opcode_Decoded
*opcode
,
876 int vnz_val
, /* Signed result. */
882 int signbit
= 1 << (opcode
->size
- 1);
884 f
&= ~opcode
->flags_0
;
885 f
&= ~opcode
->flags_set
;
886 f
|= opcode
->flags_1
;
888 if (vnz_val
& signbit
)
889 new_f
|= MSP430_FLAG_N
;
890 if (! (vnz_val
& ((signbit
<< 1) - 1)))
891 new_f
|= MSP430_FLAG_Z
;
892 if (overflow
== MAGIC_OVERFLOW
)
894 if (vnz_val
!= SX (vnz_val
))
895 new_f
|= MSP430_FLAG_V
;
899 new_f
|= MSP430_FLAG_V
;
901 new_f
|= MSP430_FLAG_C
;
903 new_f
= f
| (new_f
& opcode
->flags_set
);
905 TRACE_ALU (STATE_CPU (sd
, 0), "FLAGS: %s -> %s", flags2string (SR
),
906 flags2string (new_f
));
908 TRACE_ALU (STATE_CPU (sd
, 0), "FLAGS: %s", flags2string (new_f
));
912 #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
913 #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
915 /* These two assume unsigned 16-bit (four digit) words.
916 Mask off unwanted bits for byte operations. */
919 bcd_to_binary (int v
)
921 int r
= ( ((v
>> 0) & 0xf) * 1
922 + ((v
>> 4) & 0xf) * 10
923 + ((v
>> 8) & 0xf) * 100
924 + ((v
>> 12) & 0xf) * 1000);
929 binary_to_bcd (int v
)
931 int r
= ( ((v
/ 1) % 10) << 0
932 | ((v
/ 10) % 10) << 4
933 | ((v
/ 100) % 10) << 8
934 | ((v
/ 1000) % 10) << 12);
939 cond_string (int cond
)
964 /* Checks a CALL to address CALL_ADDR. If this is a special
965 syscall address then the call is simulated and non-zero is
966 returned. Otherwise 0 is returned. */
969 maybe_perform_syscall (SIM_DESC sd
, int call_addr
)
971 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
972 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
974 if (call_addr
== 0x00160)
978 for (i
= 0; i
< 16; i
++)
981 fprintf (stderr
, "\t");
982 fprintf (stderr
, "R%-2d %05x ", i
, msp430_cpu
->regs
[i
]);
985 int sp
= SP
+ (3 - (i
/ 4)) * 2;
986 unsigned char buf
[2];
988 sim_core_read_buffer (sd
, cpu
, read_map
, buf
, sp
, 2);
990 fprintf (stderr
, "\tSP%+d: %04x", sp
- SP
,
991 buf
[0] + buf
[1] * 256);
997 fprintf (stderr
, flags
& 0x100 ? " V" : " -");
998 fprintf (stderr
, flags
& 0x004 ? "N" : "-");
999 fprintf (stderr
, flags
& 0x002 ? "Z" : "-");
1000 fprintf (stderr
, flags
& 0x001 ? "C" : "-");
1003 fprintf (stderr
, "\n");
1009 if ((call_addr
& ~0x3f) == 0x00180)
1012 int arg1
, arg2
, arg3
, arg4
;
1013 int syscall_num
= call_addr
& 0x3f;
1015 /* syscall_num == 2 is used for the variadic function "open".
1016 The arguments are set up differently for variadic functions.
1017 See slaa534.pdf distributed by TI. */
1018 if (syscall_num
== 2)
1020 arg1
= msp430_cpu
->regs
[12];
1021 arg2
= mem_get_val (sd
, SP
, 16);
1022 arg3
= mem_get_val (sd
, SP
+ 2, 16);
1023 arg4
= mem_get_val (sd
, SP
+ 4, 16);
1027 arg1
= msp430_cpu
->regs
[12];
1028 arg2
= msp430_cpu
->regs
[13];
1029 arg3
= msp430_cpu
->regs
[14];
1030 arg4
= msp430_cpu
->regs
[15];
1033 msp430_cpu
->regs
[12] = sim_syscall (cpu
, syscall_num
, arg1
, arg2
, arg3
,
1042 msp430_step_once (SIM_DESC sd
)
1044 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
1045 struct msp430_cpu_state
*msp430_cpu
= MSP430_SIM_CPU (cpu
);
1046 Get_Byte_Local_Data ld
;
1049 unsigned int opcode_pc
;
1050 MSP430_Opcode_Decoded opcode_buf
;
1051 MSP430_Opcode_Decoded
*opcode
= &opcode_buf
;
1053 int u1
= 0, u2
, uresult
;
1058 int op_bytes
= 0, op_bits
;
1063 if (opcode_pc
< 0x10)
1065 fprintf (stderr
, "Fault: PC(%#x) is less than 0x10\n", opcode_pc
);
1066 sim_engine_halt (sd
, cpu
, NULL
, msp430_cpu
->regs
[0], sim_exited
, -1);
1070 if (PC
== msp430_cpu
->cio_breakpoint
&& STATE_OPEN_KIND (sd
) != SIM_OPEN_DEBUG
)
1075 opsize
= msp430_decode_opcode (msp430_cpu
->regs
[0], opcode
, msp430_getbyte
,
1080 fprintf (stderr
, "Fault: undecodable opcode at %#x\n", opcode_pc
);
1081 sim_engine_halt (sd
, cpu
, NULL
, msp430_cpu
->regs
[0], sim_exited
, -1);
1085 if (opcode
->repeat_reg
)
1086 n_repeats
= (msp430_cpu
->regs
[opcode
->repeats
] & 0x000f) + 1;
1088 n_repeats
= opcode
->repeats
+ 1;
1090 op_bits
= opcode
->size
;
1105 if (TRACE_ANY_P (cpu
))
1106 trace_prefix (sd
, cpu
, NULL_CIA
, opcode_pc
, TRACE_LINENUM_P (cpu
), NULL
,
1109 TRACE_DISASM (cpu
, opcode_pc
);
1117 /* Double-operand instructions. */
1119 if (opcode
->n_bytes
== 2
1120 && opcode
->op
[0].type
== MSP430_Operand_Register
1121 && opcode
->op
[0].reg
== MSR_CG
1122 && opcode
->op
[1].type
== MSP430_Operand_Immediate
1123 && opcode
->op
[1].addend
== 0
1124 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1125 && opcode
->size
== 8)
1127 /* This is the designated software breakpoint instruction. */
1129 sim_engine_halt (sd
, cpu
, NULL
, msp430_cpu
->regs
[0], sim_stopped
,
1134 /* Otherwise, do the move. */
1135 for (rept
= 0; rept
< n_repeats
; rept
++)
1143 for (rept
= 0; rept
< n_repeats
; rept
++)
1145 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1150 uresult
= u1
+ u2
+ carry_to_use
;
1151 result
= s1
+ s2
+ carry_to_use
;
1152 TRACE_ALU (cpu
, "ADDC: %#x + %#x + %d = %#x",
1153 u1
, u2
, carry_to_use
, uresult
);
1155 FLAGS (result
, uresult
!= ZX (uresult
));
1160 for (rept
= 0; rept
< n_repeats
; rept
++)
1168 TRACE_ALU (cpu
, "ADD: %#x + %#x = %#x", u1
, u2
, uresult
);
1170 FLAGS (result
, uresult
!= ZX (uresult
));
1175 for (rept
= 0; rept
< n_repeats
; rept
++)
1177 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1182 uresult
= ZX (~u2
) + u1
+ carry_to_use
;
1183 result
= s1
- s2
+ (carry_to_use
- 1);
1184 TRACE_ALU (cpu
, "SUBC: %#x - %#x + %d = %#x",
1185 u1
, u2
, carry_to_use
, uresult
);
1187 FLAGS (result
, uresult
!= ZX (uresult
));
1192 for (rept
= 0; rept
< n_repeats
; rept
++)
1198 uresult
= ZX (~u2
) + u1
+ 1;
1199 result
= SX (uresult
);
1200 TRACE_ALU (cpu
, "SUB: %#x - %#x = %#x",
1203 FLAGS (result
, uresult
!= ZX (uresult
));
1208 for (rept
= 0; rept
< n_repeats
; rept
++)
1214 uresult
= ZX (~u2
) + u1
+ 1;
1216 TRACE_ALU (cpu
, "CMP: %#x - %#x = %x",
1218 FLAGS (result
, uresult
!= ZX (uresult
));
1223 for (rept
= 0; rept
< n_repeats
; rept
++)
1225 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1228 uresult
= bcd_to_binary (u1
) + bcd_to_binary (u2
) + carry_to_use
;
1229 result
= binary_to_bcd (uresult
);
1230 TRACE_ALU (cpu
, "DADD: %#x + %#x + %d = %#x",
1231 u1
, u2
, carry_to_use
, result
);
1233 FLAGS (result
, uresult
> ((opcode
->size
== 8) ? 99 : 9999));
1238 for (rept
= 0; rept
< n_repeats
; rept
++)
1243 TRACE_ALU (cpu
, "AND: %#x & %#x = %#x",
1246 FLAGS (uresult
, uresult
!= 0);
1251 for (rept
= 0; rept
< n_repeats
; rept
++)
1256 TRACE_ALU (cpu
, "BIT: %#x & %#x -> %#x",
1258 FLAGS (uresult
, uresult
!= 0);
1263 for (rept
= 0; rept
< n_repeats
; rept
++)
1267 uresult
= u1
& ~ u2
;
1268 TRACE_ALU (cpu
, "BIC: %#x & ~ %#x = %#x",
1275 for (rept
= 0; rept
< n_repeats
; rept
++)
1280 TRACE_ALU (cpu
, "BIS: %#x | %#x = %#x",
1287 for (rept
= 0; rept
< n_repeats
; rept
++)
1289 s1
= 1 << (opcode
->size
- 1);
1293 TRACE_ALU (cpu
, "XOR: %#x & %#x = %#x",
1296 FLAGSV (uresult
, uresult
!= 0, (u1
& s1
) && (u2
& s1
));
1300 /* Single-operand instructions. Note: the decoder puts the same
1301 operand in SRC as in DEST, for our convenience. */
1304 for (rept
= 0; rept
< n_repeats
; rept
++)
1307 carry_to_use
= u1
& 1;
1309 /* If the ZC bit of the opcode is set, it means we are synthesizing
1310 RRUX, so the carry bit must be ignored. */
1311 if (opcode
->zc
== 0 && (SR
& MSP430_FLAG_C
))
1312 uresult
|= (1 << (opcode
->size
- 1));
1313 TRACE_ALU (cpu
, "RRC: %#x >>= %#x",
1316 FLAGS (uresult
, carry_to_use
);
1321 for (rept
= 0; rept
< n_repeats
; rept
++)
1324 uresult
= ((u1
>> 8) & 0x00ff) | ((u1
<< 8) & 0xff00);
1325 TRACE_ALU (cpu
, "SWPB: %#x -> %#x",
1332 for (rept
= 0; rept
< n_repeats
; rept
++)
1336 s1
= 1 << (opcode
->size
- 1);
1337 uresult
= (u1
>> 1) | (u1
& s1
);
1338 TRACE_ALU (cpu
, "RRA: %#x >>= %#x",
1346 for (rept
= 0; rept
< n_repeats
; rept
++)
1350 uresult
= (u1
>> 1);
1351 TRACE_ALU (cpu
, "RRU: %#x >>= %#x",
1359 for (rept
= 0; rept
< n_repeats
; rept
++)
1363 uresult
= u1
| 0xfff00;
1365 uresult
= u1
& 0x000ff;
1366 TRACE_ALU (cpu
, "SXT: %#x -> %#x", u1
, uresult
);
1373 for (rept
= 0; rept
< n_repeats
; rept
++)
1377 new_sp
= REG_GET (MSR_SP
) - op_bytes
;
1378 /* SP is always word-aligned. */
1381 REG_PUT (MSR_SP
, new_sp
);
1383 mem_put_val (sd
, SP
, u1
, op_bits
);
1384 if (opcode
->op
[1].type
== MSP430_Operand_Register
)
1385 opcode
->op
[1].reg
--;
1390 for (rept
= 0; rept
< n_repeats
; rept
++)
1394 u1
= mem_get_val (sd
, SP
, op_bits
);
1396 if (opcode
->op
[0].type
== MSP430_Operand_Register
)
1397 opcode
->op
[0].reg
++;
1398 new_sp
= REG_GET (MSR_SP
) + op_bytes
;
1399 /* SP is always word-aligned. */
1402 REG_PUT (MSR_SP
, new_sp
);
1409 if (maybe_perform_syscall (sd
, u1
))
1412 REG_PUT (MSR_SP
, REG_GET (MSR_SP
) - op_bytes
);
1413 mem_put_val (sd
, SP
, PC
, op_bits
);
1414 TRACE_ALU (cpu
, "CALL: func %#x ret %#x, sp %#x",
1416 REG_PUT (MSR_PC
, u1
);
1420 u1
= mem_get_val (sd
, SP
, 16);
1423 PC
= mem_get_val (sd
, SP
, 16);
1425 /* Emulate the RETI action of the 20-bit CPUX architecure.
1426 This is safe for 16-bit CPU architectures as well, since the top
1427 8-bits of SR will have been written to the stack here, and will
1428 have been read as 0. */
1429 PC
|= (u1
& 0xF000) << 4;
1430 TRACE_ALU (cpu
, "RETI: pc %#x sr %#x", PC
, SR
);
1437 switch (opcode
->cond
)
1440 u1
= (SR
& MSP430_FLAG_Z
) ? 0 : 1;
1443 u1
= (SR
& MSP430_FLAG_Z
) ? 1 : 0;
1446 u1
= (SR
& MSP430_FLAG_C
) ? 0 : 1;
1449 u1
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1452 u1
= (SR
& MSP430_FLAG_N
) ? 1 : 0;
1455 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 1 : 0;
1458 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 0 : 1;
1467 TRACE_BRANCH (cpu
, "J%s: pc %#x -> %#x sr %#x, taken",
1468 cond_string (opcode
->cond
), PC
, i
, SR
);
1470 if (PC
== opcode_pc
)
1474 TRACE_BRANCH (cpu
, "J%s: pc %#x to %#x sr %#x, not taken",
1475 cond_string (opcode
->cond
), PC
, i
, SR
);
1479 fprintf (stderr
, "error: unexpected opcode id %d\n", opcode
->id
);
1485 sim_engine_run (SIM_DESC sd
,
1492 msp430_step_once (sd
);
1493 if (sim_events_tick (sd
))
1494 sim_events_process (sd
);