1 /* Simulator for TI MSP430 and MSP430X
3 Copyright (C) 2013-2014 Free Software Foundation, Inc.
4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
7 This file is part of simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "opcode/msp430-decode.h"
32 #include "targ-vals.h"
35 loader_write_mem (SIM_DESC sd
,
37 const unsigned char *buf
,
40 SIM_CPU
*cpu
= MSP430_CPU (sd
);
41 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
45 msp430_pc_fetch (SIM_CPU
*cpu
)
47 return cpu
->state
.regs
[0];
51 msp430_pc_store (SIM_CPU
*cpu
, sim_cia newpc
)
53 cpu
->state
.regs
[0] = newpc
;
57 lookup_symbol (SIM_DESC sd
, const char *name
)
59 struct bfd
*abfd
= STATE_PROG_BFD (sd
);
60 asymbol
**symbol_table
= STATE_SYMBOL_TABLE (sd
);
61 long number_of_symbols
= STATE_NUM_SYMBOLS (sd
);
64 if (symbol_table
== NULL
)
68 storage_needed
= bfd_get_symtab_upper_bound (abfd
);
69 if (storage_needed
<= 0)
72 STATE_SYMBOL_TABLE (sd
) = symbol_table
= xmalloc (storage_needed
);
73 STATE_NUM_SYMBOLS (sd
) = number_of_symbols
=
74 bfd_canonicalize_symtab (abfd
, symbol_table
);
77 for (i
= 0; i
< number_of_symbols
; i
++)
78 if (strcmp (symbol_table
[i
]->name
, name
) == 0)
80 long val
= symbol_table
[i
]->section
->vma
+ symbol_table
[i
]->value
;
87 msp430_reg_fetch (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
89 if (0 <= regno
&& regno
< 16)
93 int val
= cpu
->state
.regs
[regno
];
95 buf
[1] = (val
>> 8) & 0xff;
100 int val
= cpu
->state
.regs
[regno
];
102 buf
[1] = (val
>> 8) & 0xff;
103 buf
[2] = (val
>> 16) & 0x0f; /* Registers are only 20 bits wide. */
115 msp430_reg_store (SIM_CPU
*cpu
, int regno
, unsigned char *buf
, int len
)
117 if (0 <= regno
&& regno
< 16)
121 cpu
->state
.regs
[regno
] = (buf
[1] << 8) | buf
[0];
127 cpu
->state
.regs
[regno
] = ((buf
[2] << 16) & 0xf0000)
128 | (buf
[1] << 8) | buf
[0];
137 msp430_initialize_cpu (SIM_DESC sd
, SIM_CPU
*cpu
)
139 memset (&cpu
->state
, 0, sizeof (cpu
->state
));
143 sim_open (SIM_OPEN_KIND kind
,
144 struct host_callback_struct
*callback
,
148 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
150 struct bfd
*prog_bfd
;
152 /* Initialise the simulator. */
154 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
160 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
166 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
172 CPU_PC_FETCH (MSP430_CPU (sd
)) = msp430_pc_fetch
;
173 CPU_PC_STORE (MSP430_CPU (sd
)) = msp430_pc_store
;
174 CPU_REG_FETCH (MSP430_CPU (sd
)) = msp430_reg_fetch
;
175 CPU_REG_STORE (MSP430_CPU (sd
)) = msp430_reg_store
;
177 /* Allocate memory if none specified by user. */
178 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x200, 1) == 0)
179 sim_do_commandf (sd
, "memory-region 0,0x10000");
180 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0xfffe, 1) == 0)
181 sim_do_commandf (sd
, "memory-region 0xfffe,2");
182 if (sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, &c
, 0x10000, 1) == 0)
183 sim_do_commandf (sd
, "memory-region 0x10000,0x100000");
185 /* Check for/establish the a reference program image. */
186 if (sim_analyze_program (sd
,
187 (STATE_PROG_ARGV (sd
) != NULL
188 ? *STATE_PROG_ARGV (sd
)
189 : NULL
), abfd
) != SIM_RC_OK
)
195 prog_bfd
= sim_load_file (sd
, argv
[0], callback
,
199 1 /* use LMA instead of VMA */,
201 if (prog_bfd
== NULL
)
207 /* Establish any remaining configuration options. */
208 if (sim_config (sd
) != SIM_RC_OK
)
214 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
220 /* CPU specific initialization. */
221 assert (MAX_NR_PROCESSORS
== 1);
222 msp430_initialize_cpu (sd
, MSP430_CPU (sd
));
224 msp430_trace_init (STATE_PROG_BFD (sd
));
226 MSP430_CPU (sd
)->state
.cio_breakpoint
= lookup_symbol (sd
, "C$$IO$$");
227 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "__CIOBUF__");
228 if (MSP430_CPU (sd
)->state
.cio_buffer
== -1)
229 MSP430_CPU (sd
)->state
.cio_buffer
= lookup_symbol (sd
, "_CIOBUF_");
235 sim_close (SIM_DESC sd
,
238 free (STATE_SYMBOL_TABLE (sd
));
243 sim_create_inferior (SIM_DESC sd
,
248 unsigned char resetv
[2];
252 c
= sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, resetv
, 0xfffe, 2);
254 new_pc
= resetv
[0] + 256 * resetv
[1];
255 sim_pc_set (MSP430_CPU (sd
), new_pc
);
256 msp430_pc_store (MSP430_CPU (sd
), new_pc
);
265 } Get_Byte_Local_Data
;
268 msp430_getbyte (void *vld
)
270 Get_Byte_Local_Data
*ld
= (Get_Byte_Local_Data
*)vld
;
272 SIM_DESC sd
= ld
->sd
;
274 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, ld
->gb_addr
, 1);
279 #define REG(N) MSP430_CPU (sd)->state.regs[(N)]
280 #define PC REG(MSR_PC)
281 #define SP REG(MSR_SP)
282 #define SR REG(MSR_SR)
287 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
288 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
292 trace_reg_put (SIM_DESC sd
, int n
, unsigned int v
)
294 if (TRACE_VPU_P (MSP430_CPU (sd
)))
295 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
296 "PUT: %#x -> %s", v
, register_names
[n
]);
301 trace_reg_get (SIM_DESC sd
, int n
)
303 if (TRACE_VPU_P (MSP430_CPU (sd
)))
304 trace_generic (sd
, MSP430_CPU (sd
), TRACE_VPU_IDX
,
305 "GET: %s -> %#x", register_names
[n
], REG (n
));
309 #define REG_PUT(N,V) trace_reg_put (sd, N, V)
310 #define REG_GET(N) trace_reg_get (sd, N)
313 get_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
)
315 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
318 unsigned char buf
[4];
323 case MSP430_Operand_Immediate
:
326 case MSP430_Operand_Register
:
327 rv
= REG_GET (op
->reg
);
329 case MSP430_Operand_Indirect
:
330 case MSP430_Operand_Indirect_Postinc
:
332 if (op
->reg
!= MSR_None
)
335 /* Index values are signed, but the sum is limited to 16
336 bits if the register < 64k, for MSP430 compatibility in
340 reg
= REG_GET (op
->reg
);
342 if (reg
< 0x10000 && ! opc
->ofs_430x
)
349 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 1);
353 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 2);
354 rv
= buf
[0] | (buf
[1] << 8);
358 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, addr
, 4);
359 rv
= buf
[0] | (buf
[1] << 8) | (buf
[2] << 16) | (buf
[3] << 24);
362 assert (! opc
->size
);
366 /* Hack - MSP430X5438 serial port status register. */
370 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
371 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
372 "GET: [%#x].%d -> %#x", addr
, opc
->size
, rv
);
375 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
399 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
400 REG_PUT (op
->reg
, REG_GET (op
->reg
) + incval
);
406 put_op (SIM_DESC sd
, MSP430_Opcode_Decoded
*opc
, int n
, int val
)
408 MSP430_Opcode_Operand
*op
= opc
->op
+ n
;
411 unsigned char buf
[4];
432 case MSP430_Operand_Register
:
434 REG_PUT (op
->reg
, val
);
436 case MSP430_Operand_Indirect
:
437 case MSP430_Operand_Indirect_Postinc
:
439 if (op
->reg
!= MSR_None
)
442 /* Index values are signed, but the sum is limited to 16
443 bits if the register < 64k, for MSP430 compatibility in
447 reg
= REG_GET (op
->reg
);
454 if (TRACE_MEMORY_P (MSP430_CPU (sd
)))
455 trace_generic (sd
, MSP430_CPU (sd
), TRACE_MEMORY_IDX
,
456 "PUT: [%#x].%d <- %#x", addr
, opc
->size
, val
);
458 /* Hack - MSP430X5438 serial port transmit register. */
466 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 1);
471 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 2);
479 sim_core_write_buffer (sd
, MSP430_CPU (sd
), write_map
, buf
, addr
, 4);
482 assert (! opc
->size
);
487 fprintf (stderr
, "invalid operand %d type %d\n", n
, op
->type
);
511 if (op
->type
== MSP430_Operand_Indirect_Postinc
)
513 int new_val
= REG_GET (op
->reg
) + incval
;
514 /* SP is always word-aligned. */
515 if (op
->reg
== MSR_SP
&& (new_val
& 1))
517 REG_PUT (op
->reg
, new_val
);
524 mem_put_val (SIM_DESC sd
, int addr
, int val
, int bits
)
526 MSP430_Opcode_Decoded opc
;
529 opc
.op
[0].type
= MSP430_Operand_Indirect
;
530 opc
.op
[0].addend
= addr
;
531 opc
.op
[0].reg
= MSR_None
;
532 put_op (sd
, &opc
, 0, val
);
536 mem_get_val (SIM_DESC sd
, int addr
, int bits
)
538 MSP430_Opcode_Decoded opc
;
541 opc
.op
[0].type
= MSP430_Operand_Indirect
;
542 opc
.op
[0].addend
= addr
;
543 opc
.op
[0].reg
= MSR_None
;
544 return get_op (sd
, &opc
, 0);
547 #define CIO_OPEN (0xF0)
548 #define CIO_CLOSE (0xF1)
549 #define CIO_READ (0xF2)
550 #define CIO_WRITE (0xF3)
551 #define CIO_LSEEK (0xF4)
552 #define CIO_UNLINK (0xF5)
553 #define CIO_GETENV (0xF6)
554 #define CIO_RENAME (0xF7)
555 #define CIO_GETTIME (0xF8)
556 #define CIO_GETCLK (0xF9)
557 #define CIO_SYNC (0xFF)
559 #define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
560 #define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
561 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
564 msp430_cio (SIM_DESC sd
)
566 /* A block of data at __CIOBUF__ describes the I/O operation to
569 unsigned char raw_parms
[13];
570 unsigned char parms
[8];
573 unsigned char buffer
[512];
575 long fd
, addr
, len
, rv
;
577 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
578 MSP430_CPU (sd
)->state
.cio_buffer
, 5);
582 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
583 MSP430_CPU (sd
)->state
.cio_buffer
+ 3, 8);
585 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
586 MSP430_CPU (sd
)->state
.cio_buffer
+ 11, length
);
594 rv
= write (fd
, buffer
, len
);
595 parms
[0] = rv
& 0xff;
601 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, parms
,
602 MSP430_CPU (sd
)->state
.cio_buffer
+ 4, 8);
604 sim_core_write_buffer (sd
, MSP430_CPU (sd
), 0, buffer
,
605 MSP430_CPU (sd
)->state
.cio_buffer
+ 12, ret_buflen
);
608 #define SRC get_op (sd, opcode, 1)
609 #define DSRC get_op (sd, opcode, 0)
610 #define DEST(V) put_op (sd, opcode, 0, (V))
613 msp430_dis_read (bfd_vma memaddr
,
616 struct disassemble_info
*dinfo
)
618 SIM_DESC sd
= dinfo
->private_data
;
619 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, myaddr
, memaddr
, length
);
623 #define DO_ALU(OP,SOP,MORE) \
627 int result = s1 OP s2 MORE; \
628 if (TRACE_ALU_P (MSP430_CPU (sd))) \
629 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \
630 "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \
634 #define SIGN (1 << (opcode->size - 1))
635 #define POS(x) (((x) & SIGN) ? 0 : 1)
636 #define NEG(x) (((x) & SIGN) ? 1 : 0)
639 zero_ext (int v
, int bits
)
641 v
&= ((1 << bits
) - 1);
646 sign_ext (int v
, int bits
)
648 int sb
= 1 << (bits
-1); /* Sign bit. */
649 int mb
= (1 << (bits
-1)) - 1; /* Mantissa bits. */
658 #define SX(v) sign_ext (v, opcode->size)
659 #define ZX(v) zero_ext (v, opcode->size)
664 static char buf
[2][6];
670 bp
[0] = f
& MSP430_FLAG_V
? 'V' : '-';
671 bp
[1] = f
& MSP430_FLAG_N
? 'N' : '-';
672 bp
[2] = f
& MSP430_FLAG_Z
? 'Z' : '-';
673 bp
[3] = f
& MSP430_FLAG_C
? 'C' : '-';
678 /* Random number that won't show up in our usual logic. */
679 #define MAGIC_OVERFLOW 0x55000F
682 do_flags (SIM_DESC sd
,
683 MSP430_Opcode_Decoded
*opcode
,
684 int vnz_val
, /* Signed result. */
690 int signbit
= 1 << (opcode
->size
- 1);
692 f
&= ~opcode
->flags_0
;
693 f
&= ~opcode
->flags_set
;
694 f
|= opcode
->flags_1
;
696 if (vnz_val
& signbit
)
697 new_f
|= MSP430_FLAG_N
;
698 if (! (vnz_val
& ((signbit
<< 1) - 1)))
699 new_f
|= MSP430_FLAG_Z
;
700 if (overflow
== MAGIC_OVERFLOW
)
702 if (vnz_val
!= SX (vnz_val
))
703 new_f
|= MSP430_FLAG_V
;
707 new_f
|= MSP430_FLAG_V
;
709 new_f
|= MSP430_FLAG_C
;
711 new_f
= f
| (new_f
& opcode
->flags_set
);
712 if (TRACE_ALU_P (MSP430_CPU (sd
)))
715 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
716 "FLAGS: %s -> %s", flags2string (SR
),
717 flags2string (new_f
));
719 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
720 "FLAGS: %s", flags2string (new_f
));
725 #define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
726 #define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
728 /* These two assume unsigned 16-bit (four digit) words.
729 Mask off unwanted bits for byte operations. */
732 bcd_to_binary (int v
)
734 int r
= ( ((v
>> 0) & 0xf) * 1
735 + ((v
>> 4) & 0xf) * 10
736 + ((v
>> 8) & 0xf) * 100
737 + ((v
>> 12) & 0xf) * 1000);
742 binary_to_bcd (int v
)
744 int r
= ( ((v
/ 1) % 10) << 0
745 | ((v
/ 10) % 10) << 4
746 | ((v
/ 100) % 10) << 8
747 | ((v
/ 1000) % 10) << 12);
752 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
753 unsigned long taddr
, char *buf
, int bytes
)
755 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
756 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
758 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
762 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
763 unsigned long taddr
, const char *buf
, int bytes
)
765 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
766 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
768 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
772 cond_string (int cond
)
797 /* Checks a CALL to address CALL_ADDR. If this is a special
798 syscall address then the call is simulated and non-zero is
799 returned. Otherwise 0 is returned. */
802 maybe_perform_syscall (SIM_DESC sd
, int call_addr
)
804 if (call_addr
== 0x00160)
808 for (i
= 0; i
< 16; i
++)
811 fprintf (stderr
, "\t");
812 fprintf (stderr
, "R%-2d %05x ", i
, MSP430_CPU (sd
)->state
.regs
[i
]);
815 int sp
= SP
+ (3 - (i
/ 4)) * 2;
816 unsigned char buf
[2];
818 sim_core_read_buffer (sd
, MSP430_CPU (sd
), read_map
, buf
, sp
, 2);
820 fprintf (stderr
, "\tSP%+d: %04x", sp
- SP
,
821 buf
[0] + buf
[1] * 256);
827 fprintf (stderr
, flags
& 0x100 ? " V" : " -");
828 fprintf (stderr
, flags
& 0x004 ? "N" : "-");
829 fprintf (stderr
, flags
& 0x002 ? "Z" : "-");
830 fprintf (stderr
, flags
& 0x001 ? "C" : "-");
833 fprintf (stderr
, "\n");
839 if ((call_addr
& ~0x3f) == 0x00180)
842 int syscall_num
= call_addr
& 0x3f;
843 host_callback
*cb
= STATE_CALLBACK (sd
);
846 CB_SYSCALL_INIT (&sc
);
848 sc
.func
= syscall_num
;
849 sc
.arg1
= MSP430_CPU (sd
)->state
.regs
[12];
850 sc
.arg2
= MSP430_CPU (sd
)->state
.regs
[13];
851 sc
.arg3
= MSP430_CPU (sd
)->state
.regs
[14];
852 sc
.arg4
= MSP430_CPU (sd
)->state
.regs
[15];
854 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
856 const char *syscall_name
= "*unknown*";
860 case TARGET_SYS_exit
:
861 syscall_name
= "exit(%d)";
863 case TARGET_SYS_open
:
864 syscall_name
= "open(%#x,%#x)";
866 case TARGET_SYS_close
:
867 syscall_name
= "close(%d)";
869 case TARGET_SYS_read
:
870 syscall_name
= "read(%d,%#x,%d)";
872 case TARGET_SYS_write
:
873 syscall_name
= "write(%d,%#x,%d)";
876 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
877 syscall_name
, sc
.arg1
, sc
.arg2
, sc
.arg3
, sc
.arg4
);
880 /* Handle SYS_exit here. */
881 if (syscall_num
== 1)
883 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
884 MSP430_CPU (sd
)->state
.regs
[0],
885 sim_exited
, sc
.arg1
);
890 sc
.p2
= MSP430_CPU (sd
);
891 sc
.read_mem
= syscall_read_mem
;
892 sc
.write_mem
= syscall_write_mem
;
894 cb_syscall (cb
, &sc
);
896 if (TRACE_SYSCALL_P (MSP430_CPU (sd
)))
897 trace_generic (sd
, MSP430_CPU (sd
), TRACE_SYSCALL_IDX
,
898 "returns %d", sc
.result
);
900 MSP430_CPU (sd
)->state
.regs
[12] = sc
.result
;
908 msp430_step_once (SIM_DESC sd
)
910 Get_Byte_Local_Data ld
;
911 unsigned char buf
[100];
914 unsigned int opcode_pc
;
915 MSP430_Opcode_Decoded opcode_buf
;
916 MSP430_Opcode_Decoded
*opcode
= &opcode_buf
;
924 int op_bytes
, op_bits
;
929 if (opcode_pc
< 0x10)
931 fprintf (stderr
, "Fault: PC(%#x) is less than 0x10\n", opcode_pc
);
932 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
933 MSP430_CPU (sd
)->state
.regs
[0],
938 if (PC
== MSP430_CPU (sd
)->state
.cio_breakpoint
939 && STATE_OPEN_KIND (sd
) != SIM_OPEN_DEBUG
)
944 opsize
= msp430_decode_opcode (MSP430_CPU (sd
)->state
.regs
[0],
945 opcode
, msp430_getbyte
, &ld
);
949 fprintf (stderr
, "Fault: undecodable opcode at %#x\n", opcode_pc
);
950 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
951 MSP430_CPU (sd
)->state
.regs
[0],
956 if (opcode
->repeat_reg
)
957 n_repeats
= (MSP430_CPU (sd
)->state
.regs
[opcode
->repeats
] & 0x000f) + 1;
959 n_repeats
= opcode
->repeats
+ 1;
961 op_bits
= opcode
->size
;
976 if (TRACE_INSN_P (MSP430_CPU (sd
)))
978 disassemble_info info
;
981 msp430_trace_one (opcode_pc
);
983 sim_core_read_buffer (sd
, MSP430_CPU (sd
), 0, b
, opcode_pc
, opsize
);
985 init_disassemble_info (&info
, stderr
, fprintf
);
986 info
.private_data
= sd
;
987 info
.read_memory_func
= msp430_dis_read
;
988 fprintf (stderr
, "%#8x ", opcode_pc
);
989 for (i
= 0; i
< opsize
; i
+= 2)
990 fprintf (stderr
, " %02x%02x", b
[i
+1], b
[i
]);
991 for (; i
< 6; i
+= 2)
992 fprintf (stderr
, " ");
993 fprintf (stderr
, " ");
994 print_insn_msp430 (opcode_pc
, &info
);
995 fprintf (stderr
, "\n");
999 if (TRACE_ANY_P (MSP430_CPU (sd
)))
1000 trace_prefix (sd
, MSP430_CPU (sd
), NULL_CIA
, opcode_pc
,
1001 TRACE_LINENUM_P (MSP430_CPU (sd
)), NULL
, 0, "");
1009 /* Double-operand instructions. */
1011 if (opcode
->n_bytes
== 2
1012 && opcode
->op
[0].type
== MSP430_Operand_Register
1013 && opcode
->op
[0].reg
== MSR_CG
1014 && opcode
->op
[1].type
== MSP430_Operand_Immediate
1015 && opcode
->op
[1].addend
== 0
1016 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1017 && opcode
->size
== 8)
1019 /* This is the designated software breakpoint instruction. */
1021 sim_engine_halt (sd
, MSP430_CPU (sd
), NULL
,
1022 MSP430_CPU (sd
)->state
.regs
[0],
1023 sim_stopped
, SIM_SIGTRAP
);
1028 /* Otherwise, do the move. */
1029 for (rept
= 0; rept
< n_repeats
; rept
++)
1037 for (rept
= 0; rept
< n_repeats
; rept
++)
1039 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1044 uresult
= u1
+ u2
+ carry_to_use
;
1045 result
= s1
+ s2
+ carry_to_use
;
1046 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1047 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1048 "ADDC: %#x + %#x + %d = %#x",
1049 u1
, u2
, carry_to_use
, uresult
);
1051 FLAGS (result
, uresult
!= ZX (uresult
));
1056 for (rept
= 0; rept
< n_repeats
; rept
++)
1064 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1065 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1066 "ADD: %#x + %#x = %#x",
1069 FLAGS (result
, uresult
!= ZX (uresult
));
1074 for (rept
= 0; rept
< n_repeats
; rept
++)
1076 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1081 uresult
= ZX (~u2
) + u1
+ carry_to_use
;
1082 result
= s1
- s2
+ (carry_to_use
- 1);
1083 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1084 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1085 "SUBC: %#x - %#x + %d = %#x",
1086 u1
, u2
, carry_to_use
, uresult
);
1088 FLAGS (result
, uresult
!= ZX (uresult
));
1093 for (rept
= 0; rept
< n_repeats
; rept
++)
1099 uresult
= ZX (~u2
) + u1
+ 1;
1100 result
= SX (uresult
);
1101 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1102 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1103 "SUB: %#x - %#x = %#x",
1106 FLAGS (result
, uresult
!= ZX (uresult
));
1111 for (rept
= 0; rept
< n_repeats
; rept
++)
1117 uresult
= ZX (~u2
) + u1
+ 1;
1119 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1120 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1121 "CMP: %#x - %#x = %x",
1123 FLAGS (result
, uresult
!= ZX (uresult
));
1128 for (rept
= 0; rept
< n_repeats
; rept
++)
1130 carry_to_use
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1133 uresult
= bcd_to_binary (u1
) + bcd_to_binary (u2
) + carry_to_use
;
1134 result
= binary_to_bcd (uresult
);
1135 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1136 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1137 "DADD: %#x + %#x + %d = %#x",
1138 u1
, u2
, carry_to_use
, result
);
1140 FLAGS (result
, uresult
> ((opcode
->size
== 8) ? 99 : 9999));
1145 for (rept
= 0; rept
< n_repeats
; rept
++)
1150 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1151 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1152 "AND: %#x & %#x = %#x",
1155 FLAGS (uresult
, uresult
!= 0);
1160 for (rept
= 0; rept
< n_repeats
; rept
++)
1165 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1166 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1167 "BIT: %#x & %#x -> %#x",
1169 FLAGS (uresult
, uresult
!= 0);
1174 for (rept
= 0; rept
< n_repeats
; rept
++)
1178 uresult
= u1
& ~ u2
;
1179 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1180 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1181 "BIC: %#x & ~ %#x = %#x",
1188 for (rept
= 0; rept
< n_repeats
; rept
++)
1193 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1194 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1195 "BIS: %#x | %#x = %#x",
1202 for (rept
= 0; rept
< n_repeats
; rept
++)
1204 s1
= 1 << (opcode
->size
- 1);
1208 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1209 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1210 "XOR: %#x & %#x = %#x",
1213 FLAGSV (uresult
, uresult
!= 0, (u1
& s1
) && (u2
& s1
));
1217 /* Single-operand instructions. Note: the decoder puts the same
1218 operand in SRC as in DEST, for our convenience. */
1221 for (rept
= 0; rept
< n_repeats
; rept
++)
1224 carry_to_use
= u1
& 1;
1226 if (SR
& MSP430_FLAG_C
)
1227 uresult
|= (1 << (opcode
->size
- 1));
1228 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1229 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1233 FLAGS (uresult
, carry_to_use
);
1238 for (rept
= 0; rept
< n_repeats
; rept
++)
1241 uresult
= ((u1
>> 8) & 0x00ff) | ((u1
<< 8) & 0xff00);
1242 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1243 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1251 for (rept
= 0; rept
< n_repeats
; rept
++)
1255 s1
= 1 << (opcode
->size
- 1);
1256 uresult
= (u1
>> 1) | (u1
& s1
);
1257 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1258 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1267 for (rept
= 0; rept
< n_repeats
; rept
++)
1271 uresult
= (u1
>> 1);
1272 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1273 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1282 for (rept
= 0; rept
< n_repeats
; rept
++)
1286 uresult
= u1
| 0xfff00;
1288 uresult
= u1
& 0x000ff;
1289 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1290 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1299 for (rept
= 0; rept
< n_repeats
; rept
++)
1303 new_sp
= REG_GET (MSR_SP
) - op_bytes
;
1304 /* SP is always word-aligned. */
1307 REG_PUT (MSR_SP
, new_sp
);
1309 mem_put_val (sd
, SP
, u1
, op_bits
);
1310 if (opcode
->op
[1].type
== MSP430_Operand_Register
)
1311 opcode
->op
[1].reg
--;
1316 for (rept
= 0; rept
< n_repeats
; rept
++)
1320 u1
= mem_get_val (sd
, SP
, op_bits
);
1322 if (opcode
->op
[0].type
== MSP430_Operand_Register
)
1323 opcode
->op
[0].reg
++;
1324 new_sp
= REG_GET (MSR_SP
) + op_bytes
;
1325 /* SP is always word-aligned. */
1328 REG_PUT (MSR_SP
, new_sp
);
1335 if (maybe_perform_syscall (sd
, u1
))
1338 REG_PUT (MSR_SP
, REG_GET (MSR_SP
) - op_bytes
);
1339 mem_put_val (sd
, SP
, PC
, op_bits
);
1340 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1341 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1342 "CALL: func %#x ret %#x, sp %#x",
1344 REG_PUT (MSR_PC
, u1
);
1348 SR
= mem_get_val (sd
, SP
, op_bits
);
1350 PC
= mem_get_val (sd
, SP
, op_bits
);
1352 if (TRACE_ALU_P (MSP430_CPU (sd
)))
1353 trace_generic (sd
, MSP430_CPU (sd
), TRACE_ALU_IDX
,
1354 "RETI: pc %#x sr %#x",
1362 switch (opcode
->cond
)
1365 u1
= (SR
& MSP430_FLAG_Z
) ? 0 : 1;
1368 u1
= (SR
& MSP430_FLAG_Z
) ? 1 : 0;
1371 u1
= (SR
& MSP430_FLAG_C
) ? 0 : 1;
1374 u1
= (SR
& MSP430_FLAG_C
) ? 1 : 0;
1377 u1
= (SR
& MSP430_FLAG_N
) ? 1 : 0;
1380 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 1 : 0;
1383 u1
= (!!(SR
& MSP430_FLAG_N
) == !!(SR
& MSP430_FLAG_V
)) ? 0 : 1;
1392 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1393 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1394 "J%s: pc %#x -> %#x sr %#x, taken",
1395 cond_string (opcode
->cond
), PC
, i
, SR
);
1397 if (PC
== opcode_pc
)
1401 if (TRACE_BRANCH_P (MSP430_CPU (sd
)))
1402 trace_generic (sd
, MSP430_CPU (sd
), TRACE_BRANCH_IDX
,
1403 "J%s: pc %#x to %#x sr %#x, not taken",
1404 cond_string (opcode
->cond
), PC
, i
, SR
);
1408 fprintf (stderr
, "error: unexpected opcode id %d\n", opcode
->id
);
1414 sim_engine_run (SIM_DESC sd
,
1421 msp430_step_once (sd
);
1422 if (sim_events_tick (sd
))
1423 sim_events_process (sd
);