1 /* OpenRISC exception, interrupts, syscall and trap support
2 Copyright (C) 2017-2021 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* This must come before any other includes. */
22 #define WANT_CPU_OR1K32BF
28 /* Implement the sim invalid instruction function. This will set the error
29 effective address to that of the invalid instruction then call the
33 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
35 SET_H_SYS_EEAR0 (cia
);
37 #ifdef WANT_CPU_OR1K32BF
38 or1k32bf_exception (current_cpu
, cia
, EXCEPT_ILLEGAL
);
44 /* Generate the appropriate OpenRISC fpu exception based on the status code from
47 or1k32bf_fpu_error (CGEN_FPU
* fpu
, int status
)
49 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
51 /* If floating point exceptions are enabled. */
52 if (GET_H_SYS_FPCSR_FPEE() != 0)
54 /* Set all of the status flag bits. */
56 & (sim_fpu_status_invalid_snan
57 | sim_fpu_status_invalid_qnan
58 | sim_fpu_status_invalid_isi
59 | sim_fpu_status_invalid_idi
60 | sim_fpu_status_invalid_zdz
61 | sim_fpu_status_invalid_imz
62 | sim_fpu_status_invalid_cvi
63 | sim_fpu_status_invalid_cmp
64 | sim_fpu_status_invalid_sqrt
))
65 SET_H_SYS_FPCSR_IVF (1);
67 if (status
& sim_fpu_status_invalid_snan
)
68 SET_H_SYS_FPCSR_SNF (1);
70 if (status
& sim_fpu_status_invalid_qnan
)
71 SET_H_SYS_FPCSR_QNF (1);
73 if (status
& sim_fpu_status_overflow
)
74 SET_H_SYS_FPCSR_OVF (1);
76 if (status
& sim_fpu_status_underflow
)
77 SET_H_SYS_FPCSR_UNF (1);
80 & (sim_fpu_status_invalid_isi
81 | sim_fpu_status_invalid_idi
))
82 SET_H_SYS_FPCSR_INF (1);
84 if (status
& sim_fpu_status_invalid_div0
)
85 SET_H_SYS_FPCSR_DZF (1);
87 if (status
& sim_fpu_status_inexact
)
88 SET_H_SYS_FPCSR_IXF (1);
90 /* If any of the exception bits were actually set. */
92 & (SPR_FIELD_MASK_SYS_FPCSR_IVF
93 | SPR_FIELD_MASK_SYS_FPCSR_SNF
94 | SPR_FIELD_MASK_SYS_FPCSR_QNF
95 | SPR_FIELD_MASK_SYS_FPCSR_OVF
96 | SPR_FIELD_MASK_SYS_FPCSR_UNF
97 | SPR_FIELD_MASK_SYS_FPCSR_INF
98 | SPR_FIELD_MASK_SYS_FPCSR_DZF
99 | SPR_FIELD_MASK_SYS_FPCSR_IXF
))
101 SIM_DESC sd
= CPU_STATE (current_cpu
);
103 /* If the sim is running in fast mode, i.e. not profiling,
104 per-instruction callbacks are not triggered which would allow
105 us to track the PC. This means we cannot track which
106 instruction caused the FPU error. */
107 if (STATE_RUN_FAST_P (sd
) == 1)
109 (sd
, "WARNING: ignoring fpu error caught in fast mode.\n");
111 or1k32bf_exception (current_cpu
, GET_H_SYS_PPC (), EXCEPT_FPE
);
117 /* Implement the OpenRISC exception function. This is mostly used by the
118 CGEN generated files. For example, this is used when handling a
119 overflow exception during a multiplication instruction. */
122 or1k32bf_exception (sim_cpu
*current_cpu
, USI pc
, USI exnum
)
124 SIM_DESC sd
= CPU_STATE (current_cpu
);
126 if (exnum
== EXCEPT_TRAP
)
128 /* Trap, used for breakpoints, sends control back to gdb breakpoint
130 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
136 /* Calculate the exception program counter. */
144 SET_H_SYS_EPCR0 (pc
+ 4 - (current_cpu
->delay_slot
? 4 : 0));
151 SET_H_SYS_EPCR0 (pc
- (current_cpu
->delay_slot
? 4 : 0));
155 sim_io_error (sd
, "unexpected exception 0x%x raised at PC 0x%08x",
160 /* Store the current SR into ESR0. */
161 SET_H_SYS_ESR0 (GET_H_SYS_SR ());
163 /* Indicate in SR if the failed instruction is in delay slot or not. */
164 SET_H_SYS_SR_DSX (current_cpu
->delay_slot
);
166 current_cpu
->next_delay_slot
= 0;
168 /* Jump program counter into handler. */
170 (GET_H_SYS_SR_EPH () ? 0xf0000000 : 0x00000000) + (exnum
<< 8);
172 sim_engine_restart (sd
, current_cpu
, NULL
, handler_pc
);
176 /* Implement the return from exception instruction. This is used to return
177 the CPU to its previous state from within an exception handler. */
180 or1k32bf_rfe (sim_cpu
*current_cpu
)
182 SET_H_SYS_SR (GET_H_SYS_ESR0 ());
185 current_cpu
->next_delay_slot
= 0;
187 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
,
191 /* Implement the move from SPR instruction. This is used to read from the
192 CPU's special purpose registers. */
195 or1k32bf_mfspr (sim_cpu
*current_cpu
, USI addr
)
197 SIM_DESC sd
= CPU_STATE (current_cpu
);
200 if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
202 sim_io_eprintf (sd
, "WARNING: l.mfspr in user mode (SR 0x%x)\n",
210 val
= GET_H_SPR (addr
);
215 case SPR_ADDR (SYS
, VR
):
216 case SPR_ADDR (SYS
, UPR
):
217 case SPR_ADDR (SYS
, CPUCFGR
):
218 case SPR_ADDR (SYS
, SR
):
219 case SPR_ADDR (SYS
, PPC
):
220 case SPR_ADDR (SYS
, FPCSR
):
221 case SPR_ADDR (SYS
, EPCR0
):
222 case SPR_ADDR (MAC
, MACLO
):
223 case SPR_ADDR (MAC
, MACHI
):
227 if (addr
< SPR_ADDR (SYS
, GPR0
) || addr
> SPR_ADDR (SYS
, GPR511
))
236 sim_io_eprintf (sd
, "WARNING: l.mfspr with invalid SPR address 0x%x\n", addr
);
241 /* Implement the move to SPR instruction. This is used to write too the
242 CPU's special purpose registers. */
245 or1k32bf_mtspr (sim_cpu
*current_cpu
, USI addr
, USI val
)
247 SIM_DESC sd
= CPU_STATE (current_cpu
);
249 if (!GET_H_SYS_SR_SM () && !GET_H_SYS_SR_SUMRA ())
252 (sd
, "WARNING: l.mtspr with address 0x%x in user mode (SR 0x%x)\n",
253 addr
, GET_H_SYS_SR ());
263 case SPR_ADDR (SYS
, FPCSR
):
264 case SPR_ADDR (SYS
, EPCR0
):
265 case SPR_ADDR (SYS
, ESR0
):
266 case SPR_ADDR (MAC
, MACHI
):
267 case SPR_ADDR (MAC
, MACLO
):
268 SET_H_SPR (addr
, val
);
271 case SPR_ADDR (SYS
, SR
):
272 SET_H_SPR (addr
, val
);
276 case SPR_ADDR (SYS
, NPC
):
277 current_cpu
->next_delay_slot
= 0;
279 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
, val
);
282 case SPR_ADDR (TICK
, TTMR
):
283 /* Allow some registers to be silently cleared. */
286 (sd
, "WARNING: l.mtspr to SPR address 0x%x with invalid value 0x%x\n",
291 if (addr
>= SPR_ADDR (SYS
, GPR0
) && addr
<= SPR_ADDR (SYS
, GPR511
))
292 SET_H_SPR (addr
, val
);
302 sim_io_eprintf (sd
, "WARNING: l.mtspr with invalid SPR address 0x%x\n", addr
);