sim/ppc/std-config.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 3 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, see <http://www.gnu.org/licenses/>.
  17
  18     */
  19
  20
  21 #ifndef _PSIM_CONFIG_H_
  22 #define _PSIM_CONFIG_H_
  23
  24 #include "bfd.h"
  25
  26 /* endianness of the host/target:
  27
  28    If the build process is aware (at compile time) of the endianness
  29    of the host/target it is able to eliminate slower generic endian
  30    handling code.
  31
  32    Possible values are BFD_ENDIAN_UNKNOWN, BFD_ENDIAN_LITTLE,
  33    BFD_ENDIAN_BIG.  */
  34
  35 #ifdef WORDS_BIGENDIAN
  36 # define HOST_BYTE_ORDER BFD_ENDIAN_BIG
  37 #else
  38 # define HOST_BYTE_ORDER BFD_ENDIAN_LITTLE
  39 #endif
  40
  41 #ifndef WITH_TARGET_BYTE_ORDER
  42 #define WITH_TARGET_BYTE_ORDER          BFD_ENDIAN_UNKNOWN
  43 #endif
  44
  45 extern enum bfd_endian current_target_byte_order;
  46 #define CURRENT_TARGET_BYTE_ORDER \
  47   (WITH_TARGET_BYTE_ORDER != BFD_ENDIAN_UNKNOWN \
  48    ? WITH_TARGET_BYTE_ORDER : current_target_byte_order)
  49
  50
  51 /* PowerPC XOR endian.
  52
  53    In addition to the above, the simulator can support the PowerPC's
  54    horrible XOR endian mode.  This feature makes it possible to
  55    control the endian mode of a processor using the MSR. */
  56
  57 #ifndef WITH_XOR_ENDIAN
  58 #define WITH_XOR_ENDIAN         8
  59 #endif
  60
  61
  62 /* SMP support:
  63
  64    Sets a limit on the number of processors that can be simulated.  If
  65    WITH_SMP is set to zero (0), the simulator is restricted to
  66    suporting only on processor (and as a consequence leaves the SMP
  67    code out of the build process).
  68
  69    The actual number of processors is taken from the device
  70    /options/smp@<nr-cpu> */
  71
  72 #ifndef WITH_SMP
  73 #define WITH_SMP                        5
  74 #endif
  75 #if WITH_SMP
  76 #define MAX_NR_PROCESSORS               WITH_SMP
  77 #else
  78 #define MAX_NR_PROCESSORS               1
  79 #endif
  80
  81
  82 /* Word size of host/target:
  83
  84    Set these according to your host and target requirements.  At this
  85    point in time, I've only compiled (not run) for a 64bit and never
  86    built for a 64bit host.  This will always remain a compile time
  87    option */
  88
  89 #ifndef WITH_TARGET_WORD_BITSIZE
  90 #define WITH_TARGET_WORD_BITSIZE        32 /* compiled only */
  91 #endif
  92
  93 #ifndef WITH_HOST_WORD_BITSIZE
  94 #define WITH_HOST_WORD_BITSIZE          32 /* 64bit ready? */
  95 #endif
  96
  97
  98 /* Program environment:
  99
 100    Three environments are available - UEA (user), VEA (virtual) and
 101    OEA (perating).  The former two are environment that users would
 102    expect to see (VEA includes things like coherency and the time
 103    base) while OEA is what an operating system expects to see.  By
 104    setting these to specific values, the build process is able to
 105    eliminate non relevent environment code
 106
 107    CURRENT_ENVIRONMENT specifies which of vea or oea is required for
 108    the current runtime. */
 109
 110 #define ALL_ENVIRONMENT                 0
 111 #define USER_ENVIRONMENT                1
 112 #define VIRTUAL_ENVIRONMENT             2
 113 #define OPERATING_ENVIRONMENT           3
 114
 115 extern int current_environment;
 116 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
 117                              ? WITH_ENVIRONMENT \
 118                              : current_environment)
 119
 120
 121 /* Optional VEA/OEA code:
 122
 123    The below, required for the OEA model may also be included in the
 124    VEA model however, as far as I can tell only make things
 125    slower... */
 126
 127
 128 /* Events.  Devices modeling real H/W need to be able to efficiently
 129    schedule things to do at known times in the future.  The event
 130    queue implements this.  Unfortunatly this adds the need to check
 131    for any events once each full instruction cycle. */
 132
 133 #define WITH_EVENTS                     (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 134
 135
 136 /* Time base:
 137
 138    The PowerPC architecture includes the addition of both a time base
 139    register and a decrement timer.  Like events adds to the overhead
 140    of of some instruction cycles. */
 141
 142 #ifndef WITH_TIME_BASE
 143 #define WITH_TIME_BASE                  (WITH_ENVIRONMENT != USER_ENVIRONMENT)
 144 #endif
 145
 146
 147 /* Callback/Default Memory.
 148
 149    Core includes a builtin memory type (raw_memory) that is
 150    implemented using an array.  raw_memory does not require any
 151    additional functions etc.
 152
 153    Callback memory is where the core calls a core device for the data
 154    it requires.
 155
 156    Default memory is an extenstion of this where for addresses that do
 157    not map into either a callback or core memory range a default map
 158    can be used.
 159
 160    The OEA model uses callback memory for devices and default memory
 161    for buses.
 162
 163    The VEA model uses callback memory to capture `page faults'.
 164
 165    While it may be possible to eliminate callback/default memory (and
 166    hence also eliminate an additional test per memory fetch) it
 167    probably is not worth the effort.
 168
 169    BTW, while raw_memory could have been implemented as a callback,
 170    profiling has shown that there is a biger win (at least for the
 171    x86) in eliminating a function call for the most common
 172    (raw_memory) case. */
 173
 174 #define WITH_CALLBACK_MEMORY            1
 175
 176
 177 /* Alignment:
 178
 179    The PowerPC may or may not handle miss aligned transfers.  An
 180    implementation normally handles miss aligned transfers in big
 181    endian mode but generates an exception in little endian mode.
 182
 183    This model.  Instead allows both little and big endian modes to
 184    either take exceptions or handle miss aligned transfers.
 185
 186    If 0 is specified then for big-endian mode miss alligned accesses
 187    are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
 188    processor will fault on them (STRICT_ALIGNMENT). */
 189
 190 #define NONSTRICT_ALIGNMENT             1
 191 #define STRICT_ALIGNMENT                2
 192
 193 #ifndef WITH_ALIGNMENT
 194 #define WITH_ALIGNMENT                  0
 195 #endif
 196
 197 extern int current_alignment;
 198 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
 199                            ? WITH_ALIGNMENT \
 200                            : current_alignment)
 201
 202
 203 /* Floating point suport:
 204
 205    Still under development. */
 206
 207 #define SOFT_FLOATING_POINT             1
 208 #define HARD_FLOATING_POINT             2
 209
 210 #ifndef WITH_FLOATING_POINT
 211 #define WITH_FLOATING_POINT             HARD_FLOATING_POINT
 212 #endif
 213 extern int current_floating_point;
 214 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
 215                                 ? WITH_FLOATING_POINT \
 216                                 : current_floating_point)
 217
 218
 219 /* Debugging:
 220
 221    Control the inclusion of debugging code. */
 222
 223 /* include monitoring code */
 224
 225 #define MONITOR_INSTRUCTION_ISSUE       1
 226 #define MONITOR_LOAD_STORE_UNIT         2
 227 #ifndef WITH_MON
 228 #define WITH_MON                        (MONITOR_LOAD_STORE_UNIT \
 229                                          | MONITOR_INSTRUCTION_ISSUE)
 230 #endif
 231
 232 /* Current CPU model (models are in the generated models.h include file)  */
 233 #ifndef WITH_MODEL
 234 #define WITH_MODEL                      0
 235 #endif
 236
 237 #define CURRENT_MODEL (WITH_MODEL       \
 238                        ? WITH_MODEL     \
 239                        : current_model)
 240
 241 #ifndef WITH_DEFAULT_MODEL
 242 #define WITH_DEFAULT_MODEL              DEFAULT_MODEL
 243 #endif
 244
 245 #define MODEL_ISSUE_IGNORE              (-1)
 246 #define MODEL_ISSUE_PROCESS             1
 247
 248 #ifndef WITH_MODEL_ISSUE
 249 #define WITH_MODEL_ISSUE                0
 250 #endif
 251
 252 extern int current_model_issue;
 253 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE   \
 254                              ? WITH_MODEL_ISSUE \
 255                              : current_model_issue)
 256
 257 /* Whether or not input/output just uses stdio, or uses printf_filtered for
 258    output, and polling input for input.  */
 259
 260 #define DONT_USE_STDIO                  2
 261 #define DO_USE_STDIO                    1
 262
 263 extern int current_stdio;
 264 #define CURRENT_STDIO (WITH_STDIO       \
 265                        ? WITH_STDIO     \
 266                        : current_stdio)
 267
 268
 269
 270 /* INLINE CODE SELECTION:
 271
 272    GCC -O3 attempts to inline any function or procedure in scope.  The
 273    options below facilitate fine grained control over what is and what
 274    isn't made inline.  For instance it can control things down to a
 275    specific modules static routines.  Doing this allows the compiler
 276    to both eliminate the overhead of function calls and (as a
 277    consequence) also eliminate further dead code.
 278
 279    On a CISC (x86) I've found that I can achieve an order of magnitude
 280    speed improvement (x3-x5).  In the case of RISC (sparc) while the
 281    performance gain isn't as great it is still significant.
 282
 283    Each module is controled by the macro <module>_INLINE which can
 284    have the values described below
 285
 286        0  Do not inline any thing for the given module
 287
 288    The following additional values are `bit fields' and can be
 289    combined.
 290
 291       REVEAL_MODULE:
 292
 293          Include the C file for the module into the file being compiled
 294          but do not make the functions within the module inline.
 295
 296          While of no apparent benefit, this makes it possible for the
 297          included module, when compiled to inline its calls to what
 298          would otherwize be external functions.
 299
 300       INLINE_MODULE:
 301
 302          Make external functions within the module `inline'.  Thus if
 303          the module is included into a file being compiled, calls to
 304          its funtions can be eliminated. 2 implies 1.
 305
 306       INLINE_LOCALS:
 307
 308          Make internal (static) functions within the module `inline'.
 309
 310    The following abreviations are available:
 311
 312       INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE)
 313
 314       ALL_C_INLINE == (REVEAL_MODULE | INLINE_MODULE | INLINE_LOCALS)
 315
 316    In addition to this, modules have been put into two categories.
 317
 318          Simple modules - eg sim-endian.h bits.h
 319
 320          Because these modules are small and simple and do not have
 321          any complex interpendencies they are configured, if
 322          <module>_INLINE is so enabled, to inline themselves in all
 323          modules that include those files.
 324
 325          For the default build, this is a real win as all byte
 326          conversion and bit manipulation functions are inlined.
 327
 328          Complex modules - the rest
 329
 330          These are all handled using the files inline.h and inline.c.
 331          psim.c includes the above which in turn include any remaining
 332          code.
 333
 334    IMPLEMENTATION:
 335
 336    The inline ability is enabled by prefixing every data / function
 337    declaration and definition with one of the following:
 338
 339
 340        INLINE_<module>
 341
 342        Prefix to any global function that is a candidate for being
 343        inline.
 344
 345        values - `', `static', `static INLINE'
 346
 347
 348        EXTERN_<module>
 349
 350        Prefix to any global data structures for the module.  Global
 351        functions that are not to be inlined shall also be prefixed
 352        with this.
 353
 354        values - `', `static', `static'
 355
 356
 357        STATIC_INLINE_<module>
 358
 359        Prefix to any local (static) function that is a candidate for
 360        being made inline.
 361
 362        values - `static', `static INLINE'
 363
 364
 365        static
 366
 367        Prefix all local data structures.  Local functions that are not
 368        to be inlined shall also be prefixed with this.
 369
 370        values - `static', `static'
 371
 372        nb: will not work for modules that are being inlined for every
 373        use (white lie).
 374
 375
 376        extern
 377        #ifndef _INLINE_C_
 378        #endif
 379
 380        Prefix to any declaration of a global object (function or
 381        variable) that should not be inlined and should have only one
 382        definition.  The #ifndef wrapper goes around the definition
 383        propper to ensure that only one copy is generated.
 384
 385        nb: this will not work when a module is being inlined for every
 386        use.
 387
 388
 389        STATIC_<module>
 390
 391        Replaced by either `static' or `EXTERN_MODULE'.
 392
 393
 394    REALITY CHECK:
 395
 396    This is not for the faint hearted.  I've seen GCC get up to 500mb
 397    trying to compile what this can create.
 398
 399    Some of the modules do not yet implement the WITH_INLINE_STATIC
 400    option.  Instead they use the macro STATIC_INLINE to control their
 401    local function.
 402
 403    Because of the way that GCC parses __attribute__(), the macro's
 404    need to be adjacent to the function name rather than at the start
 405    of the line vis:
 406
 407         int STATIC_INLINE_MODULE f(void);
 408         void INLINE_MODULE *g(void);
 409
 410    */
 411
 412 #include "../common/sim-inline.h"
 413 #define REVEAL_MODULE                   H_REVEALS_MODULE
 414 #define INLINE_MODULE                   C_REVEALS_MODULE
 415 #define INCLUDE_MODULE                  (INLINE_MODULE | REVEAL_MODULE)
 416
 417 /* Your compilers inline reserved word */
 418
 419 #ifndef INLINE
 420 #if defined(__GNUC__) && defined(__OPTIMIZE__)
 421 #define INLINE __inline__
 422 #else
 423 #define INLINE /*inline*/
 424 #endif
 425 #endif
 426
 427
 428 /* Default prefix for static functions */
 429
 430 #ifndef STATIC_INLINE
 431 #define STATIC_INLINE static INLINE
 432 #endif
 433
 434 /* Default macro to simplify control several of key the inlines */
 435
 436 #ifndef DEFAULT_INLINE
 437 #define DEFAULT_INLINE                  INLINE_LOCALS
 438 #endif
 439
 440 /* Code that converts between hosts and target byte order.  Used on
 441    every memory access (instruction and data).  See sim-endian.h for
 442    additional byte swapping configuration information.  This module
 443    can inline for all callers */
 444
 445 #ifndef SIM_ENDIAN_INLINE
 446 #define SIM_ENDIAN_INLINE               (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 447 #endif
 448
 449 /* Low level bit manipulation routines. This module can inline for all
 450    callers */
 451
 452 #ifndef BITS_INLINE
 453 #define BITS_INLINE                     (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 454 #endif
 455
 456 /* Code that gives access to various CPU internals such as registers.
 457    Used every time an instruction is executed */
 458
 459 #ifndef CPU_INLINE
 460 #define CPU_INLINE                      (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 461 #endif
 462
 463 /* Code that translates between an effective and real address.  Used
 464    by every load or store. */
 465
 466 #ifndef VM_INLINE
 467 #define VM_INLINE                       DEFAULT_INLINE
 468 #endif
 469
 470 /* Code that loads/stores data to/from the memory data structure.
 471    Used by every load or store */
 472
 473 #ifndef CORE_INLINE
 474 #define CORE_INLINE                     DEFAULT_INLINE
 475 #endif
 476
 477 /* Code to check for and process any events scheduled in the future.
 478    Called once per instruction cycle */
 479
 480 #ifndef EVENTS_INLINE
 481 #define EVENTS_INLINE                   (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 482 #endif
 483
 484 /* Code monotoring the processors performance.  It counts events on
 485    every instruction cycle */
 486
 487 #ifndef MON_INLINE
 488 #define MON_INLINE                      (DEFAULT_INLINE ? ALL_C_INLINE : 0)
 489 #endif
 490
 491 /* Code called on the rare occasions that an interrupt occures. */
 492
 493 #ifndef INTERRUPTS_INLINE
 494 #define INTERRUPTS_INLINE               DEFAULT_INLINE
 495 #endif
 496
 497 /* Code called on the rare occasion that either gdb or the device tree
 498    need to manipulate a register within a processor */
 499
 500 #ifndef REGISTERS_INLINE
 501 #define REGISTERS_INLINE                DEFAULT_INLINE
 502 #endif
 503
 504 /* Code called on the rare occasion that a processor is manipulating
 505    real hardware instead of RAM.
 506
 507    Also, most of the functions in devices.c are always called through
 508    a jump table. */
 509
 510 #ifndef DEVICE_INLINE
 511 #define DEVICE_INLINE                   (DEFAULT_INLINE ? INLINE_LOCALS : 0)
 512 #endif
 513
 514 /* Code called used while the device tree is being built.
 515
 516    Inlining this is of no benefit */
 517
 518 #ifndef TREE_INLINE
 519 #define TREE_INLINE                     (DEFAULT_INLINE ? INLINE_LOCALS : 0)
 520 #endif
 521
 522 /* Code called whenever information on a Special Purpose Register is
 523    required.  Called by the mflr/mtlr pseudo instructions */
 524
 525 #ifndef SPREG_INLINE
 526 #define SPREG_INLINE                    DEFAULT_INLINE
 527 #endif
 528
 529 /* Functions modeling the semantics of each instruction.  Two cases to
 530    consider, firstly of idecode is implemented with a switch then this
 531    allows the idecode function to inline each semantic function
 532    (avoiding a call).  The second case is when idecode is using a
 533    table, even then while the semantic functions can't be inlined,
 534    setting it to one still enables each semantic function to inline
 535    anything they call (if that code is marked for being inlined).
 536
 537    WARNING: you need lots (like 200mb of swap) of swap.  Setting this
 538    to 1 is useful when using a table as it enables the sematic code to
 539    inline all of their called functions */
 540
 541 #ifndef SEMANTICS_INLINE
 542 #define SEMANTICS_INLINE                (DEFAULT_INLINE & ~INLINE_MODULE)
 543 #endif
 544
 545 /* When using the instruction cache, code to decode an instruction and
 546    install it into the cache.  Normally called when ever there is a
 547    miss in the instruction cache. */
 548
 549 #ifndef ICACHE_INLINE
 550 #define ICACHE_INLINE                   (DEFAULT_INLINE & ~INLINE_MODULE)
 551 #endif
 552
 553 /* General functions called by semantics functions but part of the
 554    instruction table.  Although called by the semantic functions the
 555    frequency of calls is low.  Consequently the need to inline this
 556    code is reduced. */
 557
 558 #ifndef SUPPORT_INLINE
 559 #define SUPPORT_INLINE                  INLINE_LOCALS
 560 #endif
 561
 562 /* Model specific code used in simulating functional units.  Note, it actaully
 563    pays NOT to inline the PowerPC model functions (at least on the x86).  This
 564    is because if it is inlined, each PowerPC instruction gets a separate copy
 565    of the code, which is not friendly to the cache.  */
 566
 567 #ifndef MODEL_INLINE
 568 #define MODEL_INLINE                    (DEFAULT_INLINE & ~INLINE_MODULE)
 569 #endif
 570
 571 /* Code to print out what options we were compiled with.  Because this
 572    is called at process startup, it doesn't have to be inlined, but
 573    if it isn't brought in and the model routines are inline, the model
 574    routines will be pulled in twice.  */
 575
 576 #ifndef OPTIONS_INLINE
 577 #define OPTIONS_INLINE                  MODEL_INLINE
 578 #endif
 579
 580 /* idecode acts as the hub of the system, everything else is imported
 581    into this file */
 582
 583 #ifndef IDECOCE_INLINE
 584 #define IDECODE_INLINE                  INLINE_LOCALS
 585 #endif
 586
 587 /* psim, isn't actually inlined */
 588
 589 #ifndef PSIM_INLINE
 590 #define PSIM_INLINE                     INLINE_LOCALS
 591 #endif
 592
 593 /* Code to emulate os or rom compatibility.  This code is called via a
 594    table and hence there is little benefit in making it inline */
 595
 596 #ifndef OS_EMUL_INLINE
 597 #define OS_EMUL_INLINE                  0
 598 #endif
 599
 600 #endif /* _PSIM_CONFIG_H */