1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 /* This must come before any other includes. */
34 # define MAP_FAILED -1
36 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
37 # define MAP_ANONYMOUS MAP_ANON
43 #ifdef HAVE_SYS_STAT_H
56 #include "sim/callback.h"
58 #include "gdb/sim-sh.h"
62 #include "sim-options.h"
64 #include "target-newlib-syscall.h"
69 #include <float.h> /* Needed for _isnan() */
76 #define SIGBUS SIGSEGV
80 #define SIGQUIT SIGTERM
87 /* TODO: Stop using these names. */
91 extern unsigned short sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
93 #define O_RECOMPILE 85
95 #define DISASSEMBLER_TABLE
97 /* Define the rate at which the simulator should poll the host
99 #define POLL_QUIT_INTERVAL 0x60000
101 /* TODO: Move into sim_cpu. */
102 saved_state_type saved_state
;
104 struct loop_bounds
{ unsigned char *start
, *end
; };
106 /* These variables are at file scope so that functions other than
107 sim_resume can use the fetch/store macros */
109 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
110 static int global_endianw
, endianb
;
111 static int target_dsp
;
112 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
114 static int maskw
= 0;
115 static int maskl
= 0;
117 /* Short hand definitions of the registers */
119 #define SBIT(x) ((x)&sbit)
120 #define R0 saved_state.asregs.regs[0]
121 #define Rn saved_state.asregs.regs[n]
122 #define Rm saved_state.asregs.regs[m]
123 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
124 #define UR (unsigned int) R
125 #define UR (unsigned int) R
126 #define SR0 saved_state.asregs.regs[0]
127 #define CREG(n) (saved_state.asregs.cregs[(n)])
128 #define GBR saved_state.asregs.gbr
129 #define VBR saved_state.asregs.vbr
130 #define DBR saved_state.asregs.dbr
131 #define TBR saved_state.asregs.tbr
132 #define IBCR saved_state.asregs.ibcr
133 #define IBNR saved_state.asregs.ibnr
134 #define BANKN (saved_state.asregs.ibnr & 0x1ff)
135 #define ME ((saved_state.asregs.ibnr >> 14) & 0x3)
136 #define SSR saved_state.asregs.ssr
137 #define SPC saved_state.asregs.spc
138 #define SGR saved_state.asregs.sgr
139 #define SREG(n) (saved_state.asregs.sregs[(n)])
140 #define MACH saved_state.asregs.mach
141 #define MACL saved_state.asregs.macl
142 #define PR saved_state.asregs.pr
143 #define FPUL saved_state.asregs.fpul
149 /* Alternate bank of registers r0-r7 */
151 /* Note: code controling SR handles flips between BANK0 and BANK1 */
152 #define Rn_BANK(n) (saved_state.asregs.bank[(n)])
153 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0)
158 #define SR_MASK_BO (1 << 14)
159 #define SR_MASK_CS (1 << 13)
160 #define SR_MASK_DMY (1 << 11)
161 #define SR_MASK_DMX (1 << 10)
162 #define SR_MASK_M (1 << 9)
163 #define SR_MASK_Q (1 << 8)
164 #define SR_MASK_I (0xf << 4)
165 #define SR_MASK_S (1 << 1)
166 #define SR_MASK_T (1 << 0)
168 #define SR_MASK_BL (1 << 28)
169 #define SR_MASK_RB (1 << 29)
170 #define SR_MASK_MD (1 << 30)
171 #define SR_MASK_RC 0x0fff0000
172 #define SR_RC_INCREMENT -0x00010000
174 #define BO ((saved_state.asregs.sr & SR_MASK_BO) != 0)
175 #define CS ((saved_state.asregs.sr & SR_MASK_CS) != 0)
176 #define M ((saved_state.asregs.sr & SR_MASK_M) != 0)
177 #define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0)
178 #define S ((saved_state.asregs.sr & SR_MASK_S) != 0)
179 #define T ((saved_state.asregs.sr & SR_MASK_T) != 0)
180 #define LDST ((saved_state.asregs.ldst) != 0)
182 #define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0)
183 #define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0)
184 #define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0)
185 #define SR_DMY ((saved_state.asregs.sr & SR_MASK_DMY) != 0)
186 #define SR_DMX ((saved_state.asregs.sr & SR_MASK_DMX) != 0)
187 #define SR_RC ((saved_state.asregs.sr & SR_MASK_RC))
189 /* Note: don't use this for privileged bits */
190 #define SET_SR_BIT(EXP, BIT) \
193 saved_state.asregs.sr |= (BIT); \
195 saved_state.asregs.sr &= ~(BIT); \
198 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
199 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
200 #define SET_BANKN(EXP) \
202 IBNR = (IBNR & 0xfe00) | ((EXP) & 0x1f); \
204 #define SET_ME(EXP) \
206 IBNR = (IBNR & 0x3fff) | (((EXP) & 0x3) << 14); \
208 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
209 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
210 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
211 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
212 #define SET_LDST(EXP) (saved_state.asregs.ldst = ((EXP) != 0))
214 /* stc currently relies on being able to read SR without modifications. */
215 #define GET_SR() (saved_state.asregs.sr - 0)
217 #define SET_SR(x) set_sr (x)
220 (saved_state.asregs.sr \
221 = (saved_state.asregs.sr & 0xf000ffff) | ((x) & 0xfff) << 16)
223 /* Manipulate FPSCR */
225 #define FPSCR_MASK_FR (1 << 21)
226 #define FPSCR_MASK_SZ (1 << 20)
227 #define FPSCR_MASK_PR (1 << 19)
229 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
230 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
231 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
236 int old
= saved_state
.asregs
.fpscr
;
237 saved_state
.asregs
.fpscr
= (x
);
238 /* swap the floating point register banks */
239 if ((saved_state
.asregs
.fpscr
^ old
) & FPSCR_MASK_FR
240 /* Ignore bit change if simulating sh-dsp. */
243 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
244 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
245 saved_state
.asregs
.fregs
[1] = tmpf
;
249 /* sts relies on being able to read fpscr directly. */
250 #define GET_FPSCR() (saved_state.asregs.fpscr)
251 #define SET_FPSCR(x) \
256 #define DSR (saved_state.asregs.fpscr)
258 #define RAISE_EXCEPTION(x) \
259 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
261 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
262 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
264 /* This function exists mainly for the purpose of setting a breakpoint to
265 catch simulated bus errors when running the simulator under GDB. */
268 raise_exception (int x
)
274 raise_buserror (void)
276 raise_exception (SIGBUS
);
279 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
280 forbidden_addr_bits, data, retval) \
282 if (addr & forbidden_addr_bits) \
287 else if ((addr & saved_state.asregs.xyram_select) \
288 == saved_state.asregs.xram_start) \
289 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
290 else if ((addr & saved_state.asregs.xyram_select) \
291 == saved_state.asregs.yram_start) \
292 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
293 else if ((unsigned) addr >> 24 == 0xf0 \
294 && bits_written == 32 && (data & 1) == 0) \
295 /* This invalidates (if not associative) or might invalidate \
296 (if associative) an instruction cache line. This is used for \
297 trampolines. Since we don't simulate the cache, this is a no-op \
298 as far as the simulator is concerned. */ \
302 if (bits_written == 8 && addr > 0x5000000) \
303 IOMEM (addr, 1, data); \
304 /* We can't do anything useful with the other stuff, so fail. */ \
310 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
311 being implemented by ../common/sim_resume.c and the below should
312 make a call to sim_engine_halt */
314 #define BUSERROR(addr, mask) ((addr) & (mask))
316 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
321 addr_func (addr, data); \
327 #define READ_BUSERROR(addr, mask, addr_func) \
331 return addr_func (addr); \
335 /* Define this to enable register lifetime checking.
336 The compiler generates "add #0,rn" insns to mark registers as invalid,
337 the simulator uses this info to call fail if it finds a ref to an invalid
338 register before a def
345 #define CREF(x) if (!valid[x]) fail ();
346 #define CDEF(x) valid[x] = 1;
347 #define UNDEF(x) valid[x] = 0;
354 static void parse_and_set_memory_size (SIM_DESC sd
, const char *str
);
355 static int IOMEM (int addr
, int write
, int value
);
356 static struct loop_bounds
get_loop_bounds (int, int, unsigned char *,
357 unsigned char *, int, int);
358 static void process_wlat_addr (int, int);
359 static void process_wwat_addr (int, int);
360 static void process_wbat_addr (int, int);
361 static int process_rlat_addr (int);
362 static int process_rwat_addr (int);
363 static int process_rbat_addr (int);
365 /* Floating point registers */
367 #define DR(n) (get_dr (n))
372 if (host_little_endian
)
379 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
380 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
384 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
387 #define SET_DR(n, EXP) set_dr ((n), (EXP))
389 set_dr (int n
, double exp
)
392 if (host_little_endian
)
400 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
401 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
404 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
407 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
408 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
410 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
411 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
413 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
414 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
415 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
417 #define RS saved_state.asregs.rs
418 #define RE saved_state.asregs.re
419 #define MOD (saved_state.asregs.mod)
422 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
423 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
425 #define DSP_R(n) saved_state.asregs.sregs[(n)]
426 #define DSP_GRD(n) DSP_R ((n) + 8)
427 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
432 #define Y0 DSP_R (10)
433 #define Y1 DSP_R (11)
434 #define M0 DSP_R (12)
435 #define A1G DSP_R (13)
436 #define M1 DSP_R (14)
437 #define A0G DSP_R (15)
438 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
439 #define MOD_ME DSP_GRD (17)
440 #define MOD_DELTA DSP_GRD (18)
442 #define FP_OP(n, OP, m) \
446 if (((n) & 1) || ((m) & 1)) \
447 RAISE_EXCEPTION (SIGILL); \
449 SET_DR (n, (DR (n) OP DR (m))); \
452 SET_FR (n, (FR (n) OP FR (m))); \
455 #define FP_UNARY(n, OP) \
460 RAISE_EXCEPTION (SIGILL); \
462 SET_DR (n, (OP (DR (n)))); \
465 SET_FR (n, (OP (FR (n)))); \
468 #define FP_CMP(n, OP, m) \
472 if (((n) & 1) || ((m) & 1)) \
473 RAISE_EXCEPTION (SIGILL); \
475 SET_SR_T (DR (n) OP DR (m)); \
478 SET_SR_T (FR (n) OP FR (m)); \
484 /* do we need to swap banks */
485 int old_gpr
= SR_MD
&& SR_RB
;
486 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
487 if (old_gpr
!= new_gpr
)
490 for (i
= 0; i
< 8; i
++)
492 tmp
= saved_state
.asregs
.bank
[i
];
493 saved_state
.asregs
.bank
[i
] = saved_state
.asregs
.regs
[i
];
494 saved_state
.asregs
.regs
[i
] = tmp
;
497 saved_state
.asregs
.sr
= new_sr
;
502 wlat_fast (unsigned char *memory
, int x
, int value
, int maskl
)
505 unsigned int *p
= (unsigned int *) (memory
+ x
);
506 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
511 wwat_fast (unsigned char *memory
, int x
, int value
, int maskw
, int endianw
)
514 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
515 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
520 wbat_fast (unsigned char *memory
, int x
, int value
, int maskb
)
522 unsigned char *p
= memory
+ (x
^ endianb
);
523 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
531 rlat_fast (unsigned char *memory
, int x
, int maskl
)
533 unsigned int *p
= (unsigned int *) (memory
+ x
);
534 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
540 rwat_fast (unsigned char *memory
, int x
, int maskw
, int endianw
)
542 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
543 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
549 riat_fast (unsigned char *insn_ptr
, int endianw
)
551 unsigned short *p
= (unsigned short *) ((uintptr_t) insn_ptr
^ endianw
);
557 rbat_fast (unsigned char *memory
, int x
, int maskb
)
559 unsigned char *p
= memory
+ (x
^ endianb
);
560 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
565 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
566 #define RLAT(x) (rlat_fast (memory, x, maskl))
567 #define RBAT(x) (rbat_fast (memory, x, maskb))
568 #define RIAT(p) (riat_fast ((p), endianw))
569 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
570 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
571 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
573 #define RUWAT(x) (RWAT (x) & 0xffff)
574 #define RSWAT(x) ((short) (RWAT (x)))
575 #define RSLAT(x) ((long) (RLAT (x)))
576 #define RSBAT(x) (SEXT (RBAT (x)))
578 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
580 do_rdat (unsigned char *memory
, int x
, int n
, int maskl
)
586 f0
= rlat_fast (memory
, x
+ 0, maskl
);
587 f1
= rlat_fast (memory
, x
+ 4, maskl
);
588 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
589 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
593 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
595 do_wdat (unsigned char *memory
, int x
, int n
, int maskl
)
601 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
602 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
603 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
604 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
609 process_wlat_addr (int addr
, int value
)
613 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
618 process_wwat_addr (int addr
, int value
)
622 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
627 process_wbat_addr (int addr
, int value
)
631 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
636 process_rlat_addr (int addr
)
640 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
645 process_rwat_addr (int addr
)
649 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
654 process_rbat_addr (int addr
)
658 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
662 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
663 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
664 #define SEXTW(y) ((int) ((short) y))
666 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
668 #define SEXT32(x) ((int) (x))
670 #define SIGN32(x) (SEXT32 (x) >> 31)
672 /* convert pointer from target to host value. */
673 #define PT2H(x) ((x) + memory)
674 /* convert pointer from host to target value. */
675 #define PH2T(x) ((x) - memory)
677 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
679 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
681 static int in_delay_slot
= 0;
682 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
684 #define CHECK_INSN_PTR(p) \
686 if (saved_state.asregs.exception || PH2T (p) & maskw) \
687 saved_state.asregs.insn_end = 0; \
688 else if (p < loop.end) \
689 saved_state.asregs.insn_end = loop.end; \
691 saved_state.asregs.insn_end = mem_end; \
704 do { memstalls += ((((uintptr_t) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
706 #define L(x) thislock = x;
707 #define TL(x) if ((x) == prevlock) stalls++;
708 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
712 #if defined(__GO32__)
713 int sim_memory_size
= 19;
715 int sim_memory_size
= 30;
718 static int sim_profile_size
= 17;
724 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
725 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
726 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
727 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
728 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
729 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
731 #define SCI_RDRF 0x40 /* Recieve data register full */
732 #define SCI_TDRE 0x80 /* Transmit data register empty */
735 IOMEM (int addr
, int write
, int value
)
773 static FILE *profile_file
;
775 static INLINE
unsigned
779 n
= (n
<< 24 | (n
& 0xff00) << 8
780 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
784 static INLINE
unsigned short
785 swap16 (unsigned short n
)
788 n
= n
<< 8 | (n
& 0xff00) >> 8;
797 union { char b
[4]; int n
; } u
;
799 fwrite (u
.b
, 4, 1, profile_file
);
806 union { char b
[4]; int n
; } u
;
808 fwrite (u
.b
, 2, 1, profile_file
);
811 /* Turn a pointer in a register into a pointer into real memory. */
816 return (char *) (x
+ saved_state
.asregs
.memory
);
819 /* STR points to a zero-terminated string in target byte order. Return
820 the number of bytes that need to be converted to host byte order in order
821 to use this string as a zero-terminated string on the host.
822 (Not counting the rounding up needed to operate on entire words.) */
826 unsigned char *memory
= saved_state
.asregs
.memory
;
828 int endian
= endianb
;
833 for (end
= str
; memory
[end
^ endian
]; end
++) ;
834 return end
- str
+ 1;
838 strnswap (int str
, int len
)
842 if (! endianb
|| ! len
)
844 start
= (int *) ptr (str
& ~3);
845 end
= (int *) ptr (str
+ len
);
849 *start
= (old
<< 24 | (old
& 0xff00) << 8
850 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
856 /* Simulate a monitor trap, put the result into r0 and errno into r1
857 return offset by which to adjust pc. */
860 trap (SIM_DESC sd
, int i
, int *regs
, unsigned char *insn_ptr
,
861 unsigned char *memory
, int maskl
, int maskw
, int endianw
)
863 host_callback
*callback
= STATE_CALLBACK (sd
);
864 char **prog_argv
= STATE_PROG_ARGV (sd
);
869 printf ("%c", regs
[0]);
872 raise_exception (SIGQUIT
);
874 case 3: /* FIXME: for backwards compat, should be removed */
877 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
879 WLAT (countp
, RLAT (countp
) + 1);
890 #if !defined(__GO32__) && !defined(_WIN32)
891 case TARGET_NEWLIB_SH_SYS_fork
:
894 /* This would work only if endianness matched between host and target.
895 Besides, it's quite dangerous. */
897 case TARGET_NEWLIB_SH_SYS_execve
:
898 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]),
899 (char **) ptr (regs
[7]));
901 case TARGET_NEWLIB_SH_SYS_execv
:
902 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]), 0);
905 case TARGET_NEWLIB_SH_SYS_pipe
:
907 regs
[0] = (BUSERROR (regs
[5], maskl
)
909 : pipe ((int *) ptr (regs
[5])));
913 case TARGET_NEWLIB_SH_SYS_wait
:
914 regs
[0] = wait ((int *) ptr (regs
[5]));
916 #endif /* !defined(__GO32__) && !defined(_WIN32) */
918 case TARGET_NEWLIB_SH_SYS_read
:
919 strnswap (regs
[6], regs
[7]);
921 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
922 strnswap (regs
[6], regs
[7]);
924 case TARGET_NEWLIB_SH_SYS_write
:
925 strnswap (regs
[6], regs
[7]);
927 regs
[0] = (int) callback
->write_stdout (callback
,
928 ptr (regs
[6]), regs
[7]);
930 regs
[0] = (int) callback
->write (callback
, regs
[5],
931 ptr (regs
[6]), regs
[7]);
932 strnswap (regs
[6], regs
[7]);
934 case TARGET_NEWLIB_SH_SYS_lseek
:
935 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
937 case TARGET_NEWLIB_SH_SYS_close
:
938 regs
[0] = callback
->close (callback
,regs
[5]);
940 case TARGET_NEWLIB_SH_SYS_open
:
942 int len
= strswaplen (regs
[5]);
943 strnswap (regs
[5], len
);
944 regs
[0] = callback
->open (callback
, ptr (regs
[5]), regs
[6]);
945 strnswap (regs
[5], len
);
948 case TARGET_NEWLIB_SH_SYS_exit
:
949 /* EXIT - caller can look in r5 to work out the reason */
950 raise_exception (SIGQUIT
);
954 case TARGET_NEWLIB_SH_SYS_stat
: /* added at hmsi */
955 /* stat system call */
957 struct stat host_stat
;
959 int len
= strswaplen (regs
[5]);
961 strnswap (regs
[5], len
);
962 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
963 strnswap (regs
[5], len
);
967 WWAT (buf
, host_stat
.st_dev
);
969 WWAT (buf
, host_stat
.st_ino
);
971 WLAT (buf
, host_stat
.st_mode
);
973 WWAT (buf
, host_stat
.st_nlink
);
975 WWAT (buf
, host_stat
.st_uid
);
977 WWAT (buf
, host_stat
.st_gid
);
979 WWAT (buf
, host_stat
.st_rdev
);
981 WLAT (buf
, host_stat
.st_size
);
983 WLAT (buf
, host_stat
.st_atime
);
987 WLAT (buf
, host_stat
.st_mtime
);
991 WLAT (buf
, host_stat
.st_ctime
);
1003 case TARGET_NEWLIB_SH_SYS_chown
:
1005 int len
= strswaplen (regs
[5]);
1007 strnswap (regs
[5], len
);
1008 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1009 strnswap (regs
[5], len
);
1013 case TARGET_NEWLIB_SH_SYS_chmod
:
1015 int len
= strswaplen (regs
[5]);
1017 strnswap (regs
[5], len
);
1018 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1019 strnswap (regs
[5], len
);
1022 case TARGET_NEWLIB_SH_SYS_utime
:
1024 /* Cast the second argument to void *, to avoid type mismatch
1025 if a prototype is present. */
1026 int len
= strswaplen (regs
[5]);
1028 strnswap (regs
[5], len
);
1030 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1035 strnswap (regs
[5], len
);
1038 case TARGET_NEWLIB_SH_SYS_argc
:
1039 regs
[0] = countargv (prog_argv
);
1041 case TARGET_NEWLIB_SH_SYS_argnlen
:
1042 if (regs
[5] < countargv (prog_argv
))
1043 regs
[0] = strlen (prog_argv
[regs
[5]]);
1047 case TARGET_NEWLIB_SH_SYS_argn
:
1048 if (regs
[5] < countargv (prog_argv
))
1050 /* Include the termination byte. */
1051 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1052 regs
[0] = sim_write (0, regs
[6], prog_argv
[regs
[5]], i
);
1057 case TARGET_NEWLIB_SH_SYS_time
:
1058 regs
[0] = get_now ();
1060 case TARGET_NEWLIB_SH_SYS_ftruncate
:
1061 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1063 case TARGET_NEWLIB_SH_SYS_truncate
:
1065 int len
= strswaplen (regs
[5]);
1066 strnswap (regs
[5], len
);
1067 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1068 strnswap (regs
[5], len
);
1075 regs
[1] = callback
->get_errno (callback
);
1080 case 13: /* Set IBNR */
1081 IBNR
= regs
[0] & 0xffff;
1083 case 14: /* Set IBCR */
1084 IBCR
= regs
[0] & 0xffff;
1088 raise_exception (SIGTRAP
);
1097 div1 (int *R
, int iRn2
, int iRn1
/*, int T*/)
1100 unsigned char old_q
, tmp1
;
1103 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1105 R
[iRn1
] |= (unsigned long) T
;
1113 tmp1
= (R
[iRn1
] > tmp0
);
1117 SET_SR_Q ((unsigned char) (tmp1
== 0));
1123 tmp1
= (R
[iRn1
] < tmp0
);
1125 SET_SR_Q ((unsigned char) (tmp1
== 0));
1136 tmp1
= (R
[iRn1
] < tmp0
);
1140 SET_SR_Q ((unsigned char) (tmp1
== 0));
1146 tmp1
= (R
[iRn1
] > tmp0
);
1148 SET_SR_Q ((unsigned char) (tmp1
== 0));
1159 dmul_s (uint32_t rm
, uint32_t rn
)
1161 int64_t res
= (int64_t)(int32_t)rm
* (int64_t)(int32_t)rn
;
1162 MACH
= (uint32_t)((uint64_t)res
>> 32);
1163 MACL
= (uint32_t)res
;
1167 dmul_u (uint32_t rm
, uint32_t rn
)
1169 uint64_t res
= (uint64_t)(uint32_t)rm
* (uint64_t)(uint32_t)rn
;
1170 MACH
= (uint32_t)(res
>> 32);
1171 MACL
= (uint32_t)res
;
1175 macw (int *regs
, unsigned char *memory
, int n
, int m
, int endianw
)
1178 long prod
, macl
, sum
;
1180 tempm
=RSWAT (regs
[m
]); regs
[m
]+=2;
1181 tempn
=RSWAT (regs
[n
]); regs
[n
]+=2;
1184 prod
= (long) (short) tempm
* (long) (short) tempn
;
1188 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1190 /* MACH's lsb is a sticky overflow bit. */
1192 /* Store the smallest negative number in MACL if prod is
1193 negative, and the largest positive number otherwise. */
1194 sum
= 0x7fffffff + (prod
< 0);
1200 /* Add to MACH the sign extended product, and carry from low sum. */
1201 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1202 /* Sign extend at 10:th bit in MACH. */
1203 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1209 macl (int *regs
, unsigned char *memory
, int n
, int m
)
1216 tempm
= RSLAT (regs
[m
]);
1219 tempn
= RSLAT (regs
[n
]);
1225 mac64
= ((long long) macl
& 0xffffffff) |
1226 ((long long) mach
& 0xffffffff) << 32;
1228 ans
= (long long) tempm
* (long long) tempn
; /* Multiply 32bit * 32bit */
1230 mac64
+= ans
; /* Accumulate 64bit + 64 bit */
1232 macl
= (long) (mac64
& 0xffffffff);
1233 mach
= (long) ((mac64
>> 32) & 0xffffffff);
1235 if (S
) /* Store only 48 bits of the result */
1237 if (mach
< 0) /* Result is negative */
1239 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1240 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1243 mach
= mach
& 0x00007fff; /* Postive Result */
1274 /* Do extended displacement move instructions. */
1276 do_long_move_insn (int op
, int disp12
, int m
, int n
, int *thatlock
)
1279 int thislock
= *thatlock
;
1280 int endianw
= global_endianw
;
1281 int *R
= &(saved_state
.asregs
.regs
[0]);
1282 unsigned char *memory
= saved_state
.asregs
.memory
;
1283 int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1284 unsigned char *insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1287 case MOVB_RM
: /* signed */
1288 WBAT (disp12
* 1 + R
[n
], R
[m
]);
1291 WWAT (disp12
* 2 + R
[n
], R
[m
]);
1294 WLAT (disp12
* 4 + R
[n
], R
[m
]);
1296 case FMOV_RM
: /* floating point */
1300 WDAT (R
[n
] + 8 * disp12
, m
);
1303 WLAT (R
[n
] + 4 * disp12
, FI (m
));
1306 R
[n
] = RSBAT (disp12
* 1 + R
[m
]);
1310 R
[n
] = RSWAT (disp12
* 2 + R
[m
]);
1314 R
[n
] = RLAT (disp12
* 4 + R
[m
]);
1320 RDAT (R
[m
] + 8 * disp12
, n
);
1323 SET_FI (n
, RLAT (R
[m
] + 4 * disp12
));
1325 case MOVU_BMR
: /* unsigned */
1326 R
[n
] = RBAT (disp12
* 1 + R
[m
]);
1330 R
[n
] = RWAT (disp12
* 2 + R
[m
]);
1334 RAISE_EXCEPTION (SIGINT
);
1337 saved_state
.asregs
.memstalls
+= memstalls
;
1338 *thatlock
= thislock
;
1341 /* Do binary logical bit-manipulation insns. */
1343 do_blog_insn (int imm
, int addr
, int binop
,
1344 unsigned char *memory
, int maskb
)
1346 int oldval
= RBAT (addr
);
1349 case B_BCLR
: /* bclr.b */
1350 WBAT (addr
, oldval
& ~imm
);
1352 case B_BSET
: /* bset.b */
1353 WBAT (addr
, oldval
| imm
);
1355 case B_BST
: /* bst.b */
1357 WBAT (addr
, oldval
| imm
);
1359 WBAT (addr
, oldval
& ~imm
);
1361 case B_BLD
: /* bld.b */
1362 SET_SR_T ((oldval
& imm
) != 0);
1364 case B_BAND
: /* band.b */
1365 SET_SR_T (T
&& ((oldval
& imm
) != 0));
1367 case B_BOR
: /* bor.b */
1368 SET_SR_T (T
|| ((oldval
& imm
) != 0));
1370 case B_BXOR
: /* bxor.b */
1371 SET_SR_T (T
^ ((oldval
& imm
) != 0));
1373 case B_BLDNOT
: /* bldnot.b */
1374 SET_SR_T ((oldval
& imm
) == 0);
1376 case B_BANDNOT
: /* bandnot.b */
1377 SET_SR_T (T
&& ((oldval
& imm
) == 0));
1379 case B_BORNOT
: /* bornot.b */
1380 SET_SR_T (T
|| ((oldval
& imm
) == 0));
1386 fsca_s (int in
, double (*f
) (double))
1388 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1389 double result
= (*f
) (rad
);
1390 double error
, upper
, lower
, frac
;
1393 /* Search the value with the maximum error that is still within the
1394 architectural spec. */
1395 error
= ldexp (1., -21);
1396 /* compensate for calculation inaccuracy by reducing error. */
1397 error
= error
- ldexp (1., -50);
1398 upper
= result
+ error
;
1399 frac
= frexp (upper
, &exp
);
1400 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1401 lower
= result
- error
;
1402 frac
= frexp (lower
, &exp
);
1403 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1404 return fabs (upper
- result
) >= fabs (lower
- result
) ? upper
: lower
;
1410 double result
= 1. / sqrt (in
);
1412 double frac
, upper
, lower
, error
, eps
;
1415 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1416 /* Search the value with the maximum error that is still within the
1417 architectural spec. */
1418 frac
= frexp (result
, &exp
);
1419 frac
= ldexp (frac
, 24);
1420 error
= 4.0; /* 1 << 24-1-21 */
1421 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1422 eps
= ldexp (1., -29);
1423 upper
= floor (frac
+ error
- eps
);
1424 if (upper
> 16777216.)
1425 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1426 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1427 if (lower
> 8388608.)
1428 lower
= ceil (frac
- error
+ eps
);
1429 upper
= ldexp (upper
, exp
- 24);
1430 lower
= ldexp (lower
, exp
- 24);
1431 return upper
- result
>= result
- lower
? upper
: lower
;
1435 /* GET_LOOP_BOUNDS {EXTENDED}
1436 These two functions compute the actual starting and ending point
1437 of the repeat loop, based on the RS and RE registers (repeat start,
1438 repeat stop). The extended version is called for LDRC, and the
1439 regular version is called for SETRC. The difference is that for
1440 LDRC, the loop start and end instructions are literally the ones
1441 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1443 static struct loop_bounds
1444 get_loop_bounds_ext (int rs
, int re
, unsigned char *memory
,
1445 unsigned char *mem_end
, int maskw
, int endianw
)
1447 struct loop_bounds loop
;
1449 /* FIXME: should I verify RS < RE? */
1450 loop
.start
= PT2H (RS
); /* FIXME not using the params? */
1451 loop
.end
= PT2H (RE
& ~1); /* Ignore bit 0 of RE. */
1452 SKIP_INSN (loop
.end
);
1453 if (loop
.end
>= mem_end
)
1454 loop
.end
= PT2H (0);
1458 static struct loop_bounds
1459 get_loop_bounds (int rs
, int re
, unsigned char *memory
, unsigned char *mem_end
,
1460 int maskw
, int endianw
)
1462 struct loop_bounds loop
;
1468 loop
.start
= PT2H (RE
- 4);
1469 SKIP_INSN (loop
.start
);
1470 loop
.end
= loop
.start
;
1472 SKIP_INSN (loop
.end
);
1474 SKIP_INSN (loop
.end
);
1475 SKIP_INSN (loop
.end
);
1479 loop
.start
= PT2H (RS
);
1480 loop
.end
= PT2H (RE
- 4);
1481 SKIP_INSN (loop
.end
);
1482 SKIP_INSN (loop
.end
);
1483 SKIP_INSN (loop
.end
);
1484 SKIP_INSN (loop
.end
);
1486 if (loop
.end
>= mem_end
)
1487 loop
.end
= PT2H (0);
1490 loop
.end
= PT2H (0);
1497 /* Provide calloc / free versions that use an anonymous mmap. This can
1498 significantly cut the start-up time when a large simulator memory is
1499 required, because pages are only zeroed on demand. */
1500 #ifdef MAP_ANONYMOUS
1502 mcalloc (size_t nmemb
, size_t size
)
1508 return mmap (0, size
, PROT_READ
| PROT_WRITE
, MAP_PRIVATE
| MAP_ANONYMOUS
,
1512 #define mfree(start,length) munmap ((start), (length))
1514 #define mcalloc calloc
1515 #define mfree(start,length) free(start)
1518 /* Set the memory size to the power of two provided. */
1521 sim_size (int power
)
1523 sim_memory_size
= power
;
1525 if (saved_state
.asregs
.memory
)
1527 mfree (saved_state
.asregs
.memory
, saved_state
.asregs
.msize
);
1530 saved_state
.asregs
.msize
= 1 << power
;
1532 saved_state
.asregs
.memory
=
1533 (unsigned char *) mcalloc (1, saved_state
.asregs
.msize
);
1535 if (!saved_state
.asregs
.memory
)
1538 "Not enough VM for simulation of %d bytes of RAM\n",
1539 saved_state
.asregs
.msize
);
1541 saved_state
.asregs
.msize
= 1;
1542 saved_state
.asregs
.memory
= (unsigned char *) mcalloc (1, 1);
1547 init_dsp (struct bfd
*abfd
)
1549 int was_dsp
= target_dsp
;
1550 unsigned long mach
= bfd_get_mach (abfd
);
1552 if (mach
== bfd_mach_sh_dsp
||
1553 mach
== bfd_mach_sh4al_dsp
||
1554 mach
== bfd_mach_sh3_dsp
)
1556 int ram_area_size
, xram_start
, yram_start
;
1560 if (mach
== bfd_mach_sh_dsp
)
1562 /* SH7410 (orig. sh-sdp):
1563 4KB each for X & Y memory;
1564 On-chip X RAM 0x0800f000-0x0800ffff
1565 On-chip Y RAM 0x0801f000-0x0801ffff */
1566 xram_start
= 0x0800f000;
1567 ram_area_size
= 0x1000;
1569 if (mach
== bfd_mach_sh3_dsp
|| mach
== bfd_mach_sh4al_dsp
)
1572 8KB each for X & Y memory;
1573 On-chip X RAM 0x1000e000-0x1000ffff
1574 On-chip Y RAM 0x1001e000-0x1001ffff */
1575 xram_start
= 0x1000e000;
1576 ram_area_size
= 0x2000;
1578 yram_start
= xram_start
+ 0x10000;
1579 new_select
= ~(ram_area_size
- 1);
1580 if (saved_state
.asregs
.xyram_select
!= new_select
)
1582 saved_state
.asregs
.xyram_select
= new_select
;
1583 free (saved_state
.asregs
.xmem
);
1584 free (saved_state
.asregs
.ymem
);
1585 saved_state
.asregs
.xmem
=
1586 (unsigned char *) calloc (1, ram_area_size
);
1587 saved_state
.asregs
.ymem
=
1588 (unsigned char *) calloc (1, ram_area_size
);
1590 /* Disable use of X / Y mmeory if not allocated. */
1591 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1593 saved_state
.asregs
.xyram_select
= 0;
1594 if (saved_state
.asregs
.xmem
)
1595 free (saved_state
.asregs
.xmem
);
1596 if (saved_state
.asregs
.ymem
)
1597 free (saved_state
.asregs
.ymem
);
1600 saved_state
.asregs
.xram_start
= xram_start
;
1601 saved_state
.asregs
.yram_start
= yram_start
;
1602 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1603 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1608 if (saved_state
.asregs
.xyram_select
)
1610 saved_state
.asregs
.xyram_select
= 0;
1611 free (saved_state
.asregs
.xmem
);
1612 free (saved_state
.asregs
.ymem
);
1616 if (! saved_state
.asregs
.xyram_select
)
1618 saved_state
.asregs
.xram_start
= 1;
1619 saved_state
.asregs
.yram_start
= 1;
1622 if (saved_state
.asregs
.regstack
== NULL
)
1623 saved_state
.asregs
.regstack
=
1624 calloc (512, sizeof *saved_state
.asregs
.regstack
);
1626 if (target_dsp
!= was_dsp
)
1630 for (i
= ARRAY_SIZE (sh_dsp_table
) - 1; i
>= 0; i
--)
1632 tmp
= sh_jump_table
[0xf000 + i
];
1633 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1634 sh_dsp_table
[i
] = tmp
;
1640 init_pointers (void)
1642 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1644 sim_size (sim_memory_size
);
1647 if (saved_state
.asregs
.profile
&& !profile_file
)
1649 profile_file
= fopen ("gmon.out", "wb");
1650 /* Seek to where to put the call arc data */
1651 nsamples
= (1 << sim_profile_size
);
1653 fseek (profile_file
, nsamples
* 2 + 12, 0);
1657 fprintf (stderr
, "Can't open gmon.out\n");
1661 saved_state
.asregs
.profile_hist
=
1662 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1675 p
= saved_state
.asregs
.profile_hist
;
1677 maxpc
= (1 << sim_profile_size
);
1679 fseek (profile_file
, 0L, 0);
1680 swapout (minpc
<< PROFILE_SHIFT
);
1681 swapout (maxpc
<< PROFILE_SHIFT
);
1682 swapout (nsamples
* 2 + 12);
1683 for (i
= 0; i
< nsamples
; i
++)
1684 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1689 gotcall (int from
, int to
)
1696 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1699 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1701 register unsigned char *insn_ptr
;
1702 unsigned char *mem_end
;
1703 struct loop_bounds loop
;
1704 register int cycles
= 0;
1705 register int stalls
= 0;
1706 register int memstalls
= 0;
1707 register int insts
= 0;
1708 register int prevlock
;
1712 register int thislock
;
1714 register unsigned int doprofile
;
1715 register int pollcount
= 0;
1716 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1717 endianb is used less often. */
1718 register int endianw
= global_endianw
;
1720 int tick_start
= get_now ();
1721 void (*prev_fpe
) ();
1723 register unsigned short *jump_table
= sh_jump_table
;
1725 register int *R
= &(saved_state
.asregs
.regs
[0]);
1731 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1732 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1733 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1734 register unsigned char *memory
;
1735 register unsigned int sbit
= ((unsigned int) 1 << 31);
1737 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1740 saved_state
.asregs
.exception
= 0;
1742 memory
= saved_state
.asregs
.memory
;
1743 mem_end
= memory
+ saved_state
.asregs
.msize
;
1746 loop
= get_loop_bounds_ext (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1748 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1750 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1751 CHECK_INSN_PTR (insn_ptr
);
1754 PR
= saved_state
.asregs
.pr
;
1756 /*T = GET_SR () & SR_MASK_T;*/
1757 prevlock
= saved_state
.asregs
.prevlock
;
1758 thislock
= saved_state
.asregs
.thislock
;
1759 doprofile
= saved_state
.asregs
.profile
;
1761 /* If profiling not enabled, disable it by asking for
1762 profiles infrequently. */
1767 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1769 if (saved_state
.asregs
.exception
)
1770 /* This can happen if we've already been single-stepping and
1771 encountered a loop end. */
1772 saved_state
.asregs
.insn_end
= insn_ptr
;
1775 saved_state
.asregs
.exception
= SIGTRAP
;
1776 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1780 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1782 register unsigned int iword
= RIAT (insn_ptr
);
1783 register unsigned int ult
;
1784 register unsigned char *nip
= insn_ptr
+ 2;
1797 if (--pollcount
< 0)
1799 host_callback
*callback
= STATE_CALLBACK (sd
);
1801 pollcount
= POLL_QUIT_INTERVAL
;
1802 if ((*callback
->poll_quit
) != NULL
1803 && (*callback
->poll_quit
) (callback
))
1810 prevlock
= thislock
;
1814 if (cycles
>= doprofile
)
1817 saved_state
.asregs
.cycles
+= doprofile
;
1818 cycles
-= doprofile
;
1819 if (saved_state
.asregs
.profile_hist
)
1821 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1824 int i
= saved_state
.asregs
.profile_hist
[n
];
1826 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1833 if (saved_state
.asregs
.insn_end
== loop
.end
)
1835 saved_state
.asregs
.sr
+= SR_RC_INCREMENT
;
1837 insn_ptr
= loop
.start
;
1840 saved_state
.asregs
.insn_end
= mem_end
;
1841 loop
.end
= PT2H (0);
1846 if (saved_state
.asregs
.exception
== SIGILL
1847 || saved_state
.asregs
.exception
== SIGBUS
)
1851 /* Check for SIGBUS due to insn fetch. */
1852 else if (! saved_state
.asregs
.exception
)
1853 saved_state
.asregs
.exception
= SIGBUS
;
1855 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1856 saved_state
.asregs
.cycles
+= cycles
;
1857 saved_state
.asregs
.stalls
+= stalls
;
1858 saved_state
.asregs
.memstalls
+= memstalls
;
1859 saved_state
.asregs
.insts
+= insts
;
1860 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1862 saved_state
.asregs
.pr
= PR
;
1865 saved_state
.asregs
.prevlock
= prevlock
;
1866 saved_state
.asregs
.thislock
= thislock
;
1873 signal (SIGFPE
, prev_fpe
);
1877 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const void *buffer
, int size
)
1880 const unsigned char *data
= buffer
;
1884 for (i
= 0; i
< size
; i
++)
1886 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = data
[i
];
1892 sim_read (SIM_DESC sd
, SIM_ADDR addr
, void *buffer
, int size
)
1895 unsigned char *data
= buffer
;
1899 for (i
= 0; i
< size
; i
++)
1901 data
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1906 static int gdb_bank_number
;
1916 sh_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1921 val
= swap (* (int *) memory
);
1924 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
1925 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
1926 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
1927 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
1928 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
1929 case SIM_SH_R15_REGNUM
:
1930 saved_state
.asregs
.regs
[rn
] = val
;
1932 case SIM_SH_PC_REGNUM
:
1933 saved_state
.asregs
.pc
= val
;
1935 case SIM_SH_PR_REGNUM
:
1938 case SIM_SH_GBR_REGNUM
:
1941 case SIM_SH_VBR_REGNUM
:
1944 case SIM_SH_MACH_REGNUM
:
1947 case SIM_SH_MACL_REGNUM
:
1950 case SIM_SH_SR_REGNUM
:
1953 case SIM_SH_FPUL_REGNUM
:
1956 case SIM_SH_FPSCR_REGNUM
:
1959 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
1960 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
1961 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
1962 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
1963 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
1964 case SIM_SH_FR15_REGNUM
:
1965 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
1967 case SIM_SH_DSR_REGNUM
:
1970 case SIM_SH_A0G_REGNUM
:
1973 case SIM_SH_A0_REGNUM
:
1976 case SIM_SH_A1G_REGNUM
:
1979 case SIM_SH_A1_REGNUM
:
1982 case SIM_SH_M0_REGNUM
:
1985 case SIM_SH_M1_REGNUM
:
1988 case SIM_SH_X0_REGNUM
:
1991 case SIM_SH_X1_REGNUM
:
1994 case SIM_SH_Y0_REGNUM
:
1997 case SIM_SH_Y1_REGNUM
:
2000 case SIM_SH_MOD_REGNUM
:
2003 case SIM_SH_RS_REGNUM
:
2006 case SIM_SH_RE_REGNUM
:
2009 case SIM_SH_SSR_REGNUM
:
2012 case SIM_SH_SPC_REGNUM
:
2015 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2016 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2017 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2018 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2019 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2020 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2021 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2023 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2024 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
] = val
;
2028 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2030 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2032 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2033 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2034 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2035 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2036 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2038 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2039 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8] = val
;
2043 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2045 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2047 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2048 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2049 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2050 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2051 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2053 case SIM_SH_TBR_REGNUM
:
2056 case SIM_SH_IBNR_REGNUM
:
2059 case SIM_SH_IBCR_REGNUM
:
2062 case SIM_SH_BANK_REGNUM
:
2063 /* This is a pseudo-register maintained just for gdb.
2064 It tells us what register bank gdb would like to read/write. */
2065 gdb_bank_number
= val
;
2067 case SIM_SH_BANK_MACL_REGNUM
:
2068 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
] = val
;
2070 case SIM_SH_BANK_GBR_REGNUM
:
2071 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
] = val
;
2073 case SIM_SH_BANK_PR_REGNUM
:
2074 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
] = val
;
2076 case SIM_SH_BANK_IVN_REGNUM
:
2077 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
] = val
;
2079 case SIM_SH_BANK_MACH_REGNUM
:
2080 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
] = val
;
2089 sh_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
2096 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2097 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2098 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2099 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2100 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2101 case SIM_SH_R15_REGNUM
:
2102 val
= saved_state
.asregs
.regs
[rn
];
2104 case SIM_SH_PC_REGNUM
:
2105 val
= saved_state
.asregs
.pc
;
2107 case SIM_SH_PR_REGNUM
:
2110 case SIM_SH_GBR_REGNUM
:
2113 case SIM_SH_VBR_REGNUM
:
2116 case SIM_SH_MACH_REGNUM
:
2119 case SIM_SH_MACL_REGNUM
:
2122 case SIM_SH_SR_REGNUM
:
2125 case SIM_SH_FPUL_REGNUM
:
2128 case SIM_SH_FPSCR_REGNUM
:
2131 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2132 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2133 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2134 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2135 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2136 case SIM_SH_FR15_REGNUM
:
2137 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2139 case SIM_SH_DSR_REGNUM
:
2142 case SIM_SH_A0G_REGNUM
:
2145 case SIM_SH_A0_REGNUM
:
2148 case SIM_SH_A1G_REGNUM
:
2151 case SIM_SH_A1_REGNUM
:
2154 case SIM_SH_M0_REGNUM
:
2157 case SIM_SH_M1_REGNUM
:
2160 case SIM_SH_X0_REGNUM
:
2163 case SIM_SH_X1_REGNUM
:
2166 case SIM_SH_Y0_REGNUM
:
2169 case SIM_SH_Y1_REGNUM
:
2172 case SIM_SH_MOD_REGNUM
:
2175 case SIM_SH_RS_REGNUM
:
2178 case SIM_SH_RE_REGNUM
:
2181 case SIM_SH_SSR_REGNUM
:
2184 case SIM_SH_SPC_REGNUM
:
2187 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2188 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2189 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2190 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2191 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2192 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2193 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2195 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2196 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
];
2199 val
= (SR_MD
&& SR_RB
2200 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2201 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2203 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2204 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2205 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2206 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2207 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2209 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2210 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8];
2213 val
= (! SR_MD
|| ! SR_RB
2214 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2215 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2217 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2218 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2219 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2220 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2221 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2223 case SIM_SH_TBR_REGNUM
:
2226 case SIM_SH_IBNR_REGNUM
:
2229 case SIM_SH_IBCR_REGNUM
:
2232 case SIM_SH_BANK_REGNUM
:
2233 /* This is a pseudo-register maintained just for gdb.
2234 It tells us what register bank gdb would like to read/write. */
2235 val
= gdb_bank_number
;
2237 case SIM_SH_BANK_MACL_REGNUM
:
2238 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
];
2240 case SIM_SH_BANK_GBR_REGNUM
:
2241 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
];
2243 case SIM_SH_BANK_PR_REGNUM
:
2244 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
];
2246 case SIM_SH_BANK_IVN_REGNUM
:
2247 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
];
2249 case SIM_SH_BANK_MACH_REGNUM
:
2250 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
];
2255 * (int *) memory
= swap (val
);
2260 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
2262 /* The SH simulator uses SIGQUIT to indicate that the program has
2263 exited, so we must check for it here and translate it to exit. */
2264 if (saved_state
.asregs
.exception
== SIGQUIT
)
2266 *reason
= sim_exited
;
2267 *sigrc
= saved_state
.asregs
.regs
[5];
2271 *reason
= sim_stopped
;
2272 *sigrc
= saved_state
.asregs
.exception
;
2277 sim_info (SIM_DESC sd
, int verbose
)
2280 (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2281 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2283 sim_io_printf (sd
, "\n\n# instructions executed %10d\n",
2284 saved_state
.asregs
.insts
);
2285 sim_io_printf (sd
, "# cycles %10d\n",
2286 saved_state
.asregs
.cycles
);
2287 sim_io_printf (sd
, "# pipeline stalls %10d\n",
2288 saved_state
.asregs
.stalls
);
2289 sim_io_printf (sd
, "# misaligned load/store %10d\n",
2290 saved_state
.asregs
.memstalls
);
2291 sim_io_printf (sd
, "# real time taken %10.4f\n", timetaken
);
2292 sim_io_printf (sd
, "# virtual time taken %10.4f\n", virttime
);
2293 sim_io_printf (sd
, "# profiling size %10d\n", sim_profile_size
);
2294 sim_io_printf (sd
, "# profiling frequency %10d\n",
2295 saved_state
.asregs
.profile
);
2296 sim_io_printf (sd
, "# profile maxpc %10x\n",
2297 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2301 sim_io_printf (sd
, "# cycles/second %10d\n",
2302 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2303 sim_io_printf (sd
, "# simulation ratio %10.4f\n",
2304 virttime
/ timetaken
);
2309 sh_pc_get (sim_cpu
*cpu
)
2311 return saved_state
.asregs
.pc
;
2315 sh_pc_set (sim_cpu
*cpu
, sim_cia pc
)
2317 saved_state
.asregs
.pc
= pc
;
2321 free_state (SIM_DESC sd
)
2323 if (STATE_MODULES (sd
) != NULL
)
2324 sim_module_uninstall (sd
);
2325 sim_cpu_free_all (sd
);
2326 sim_state_free (sd
);
2330 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
2331 struct bfd
*abfd
, char * const *argv
)
2343 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
2344 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
2346 /* Set default options before parsing user options. */
2347 current_alignment
= STRICT_ALIGNMENT
;
2348 cb
->syscall_map
= cb_sh_syscall_map
;
2350 /* The cpu data is kept in a separately allocated chunk of memory. */
2351 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
2357 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
2363 /* The parser will print an error message for us, so we silently return. */
2364 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
2370 /* Check for/establish the a reference program image. */
2371 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
2377 /* Configure/verify the target byte order and other runtime
2378 configuration options. */
2379 if (sim_config (sd
) != SIM_RC_OK
)
2381 sim_module_uninstall (sd
);
2385 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
2387 /* Uninstall the modules to avoid memory leaks,
2388 file descriptor leaks, etc. */
2389 sim_module_uninstall (sd
);
2393 /* CPU specific initialization. */
2394 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
2396 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
2398 CPU_REG_FETCH (cpu
) = sh_reg_fetch
;
2399 CPU_REG_STORE (cpu
) = sh_reg_store
;
2400 CPU_PC_FETCH (cpu
) = sh_pc_get
;
2401 CPU_PC_STORE (cpu
) = sh_pc_set
;
2404 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2407 parse_and_set_memory_size (sd
, *p
);
2413 for (i
= 4; (i
-= 2) >= 0; )
2414 mem_word
.s
[i
>> 1] = i
;
2415 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2417 for (i
= 4; --i
>= 0; )
2419 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2425 parse_and_set_memory_size (SIM_DESC sd
, const char *str
)
2429 n
= strtol (str
, NULL
, 10);
2430 if (n
> 0 && n
<= 31)
2431 sim_memory_size
= n
;
2433 sim_io_printf (sd
, "Bad memory size %d; must be 1 to 31, inclusive\n", n
);
2437 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
2438 char * const *argv
, char * const *env
)
2440 /* Clear the registers. */
2441 memset (&saved_state
, 0,
2442 (char*) &saved_state
.asregs
.end_of_registers
- (char*) &saved_state
);
2445 if (prog_bfd
!= NULL
)
2446 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2448 /* Set the bfd machine type. */
2449 if (prog_bfd
!= NULL
)
2450 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2452 if (prog_bfd
!= NULL
)
2453 init_dsp (prog_bfd
);
2459 sim_do_command (SIM_DESC sd
, const char *cmd
)
2461 const char *sms_cmd
= "set-memory-size";
2464 if (cmd
== NULL
|| *cmd
== '\0')
2469 cmdsize
= strlen (sms_cmd
);
2470 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0
2471 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2473 parse_and_set_memory_size (sd
, cmd
+ cmdsize
+ 1);
2475 else if (strcmp (cmd
, "help") == 0)
2477 sim_io_printf (sd
, "List of SH simulator commands:\n\n");
2478 sim_io_printf (sd
, "set-memory-size <n> -- Set the number of address bits to use\n");
2479 sim_io_printf (sd
, "\n");
2483 sim_io_printf (sd
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);