1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
33 # define MAP_FAILED -1
35 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
36 # define MAP_ANONYMOUS MAP_ANON
42 #ifdef HAVE_SYS_STAT_H
46 #ifdef HAVE_SYS_TIME_H
55 #include "gdb/callback.h"
56 #include "gdb/remote-sim.h"
57 #include "gdb/sim-sh.h"
61 #include "sim-options.h"
63 /* This file is local - if newlib changes, then so should this. */
69 #include <float.h> /* Needed for _isnan() */
74 #define SIGBUS SIGSEGV
78 #define SIGQUIT SIGTERM
85 /* TODO: Stop using these names. */
89 extern unsigned short sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
91 #define O_RECOMPILE 85
93 #define DISASSEMBLER_TABLE
95 /* Define the rate at which the simulator should poll the host
97 #define POLL_QUIT_INTERVAL 0x60000
99 /* TODO: Move into sim_cpu. */
100 saved_state_type saved_state
;
102 struct loop_bounds
{ unsigned char *start
, *end
; };
104 /* These variables are at file scope so that functions other than
105 sim_resume can use the fetch/store macros */
107 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
108 static int global_endianw
, endianb
;
109 static int target_dsp
;
110 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
112 static int maskw
= 0;
113 static int maskl
= 0;
115 /* Short hand definitions of the registers */
117 #define SBIT(x) ((x)&sbit)
118 #define R0 saved_state.asregs.regs[0]
119 #define Rn saved_state.asregs.regs[n]
120 #define Rm saved_state.asregs.regs[m]
121 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
122 #define UR (unsigned int) R
123 #define UR (unsigned int) R
124 #define SR0 saved_state.asregs.regs[0]
125 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
126 #define GBR saved_state.asregs.cregs.named.gbr
127 #define VBR saved_state.asregs.cregs.named.vbr
128 #define DBR saved_state.asregs.cregs.named.dbr
129 #define TBR saved_state.asregs.cregs.named.tbr
130 #define IBCR saved_state.asregs.cregs.named.ibcr
131 #define IBNR saved_state.asregs.cregs.named.ibnr
132 #define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
133 #define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
134 #define SSR saved_state.asregs.cregs.named.ssr
135 #define SPC saved_state.asregs.cregs.named.spc
136 #define SGR saved_state.asregs.cregs.named.sgr
137 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
138 #define MACH saved_state.asregs.sregs.named.mach
139 #define MACL saved_state.asregs.sregs.named.macl
140 #define PR saved_state.asregs.sregs.named.pr
141 #define FPUL saved_state.asregs.sregs.named.fpul
147 /* Alternate bank of registers r0-r7 */
149 /* Note: code controling SR handles flips between BANK0 and BANK1 */
150 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
151 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
156 #define SR_MASK_BO (1 << 14)
157 #define SR_MASK_CS (1 << 13)
158 #define SR_MASK_DMY (1 << 11)
159 #define SR_MASK_DMX (1 << 10)
160 #define SR_MASK_M (1 << 9)
161 #define SR_MASK_Q (1 << 8)
162 #define SR_MASK_I (0xf << 4)
163 #define SR_MASK_S (1 << 1)
164 #define SR_MASK_T (1 << 0)
166 #define SR_MASK_BL (1 << 28)
167 #define SR_MASK_RB (1 << 29)
168 #define SR_MASK_MD (1 << 30)
169 #define SR_MASK_RC 0x0fff0000
170 #define SR_RC_INCREMENT -0x00010000
172 #define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
173 #define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
174 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
175 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
176 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
177 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
178 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
180 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
181 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
182 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
183 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
184 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
185 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
187 /* Note: don't use this for privileged bits */
188 #define SET_SR_BIT(EXP, BIT) \
191 saved_state.asregs.cregs.named.sr |= (BIT); \
193 saved_state.asregs.cregs.named.sr &= ~(BIT); \
196 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
197 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
198 #define SET_BANKN(EXP) \
200 IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
202 #define SET_ME(EXP) \
204 IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
206 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
207 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
208 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
209 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
210 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
212 /* stc currently relies on being able to read SR without modifications. */
213 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
215 #define SET_SR(x) set_sr (x)
218 (saved_state.asregs.cregs.named.sr \
219 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
221 /* Manipulate FPSCR */
223 #define FPSCR_MASK_FR (1 << 21)
224 #define FPSCR_MASK_SZ (1 << 20)
225 #define FPSCR_MASK_PR (1 << 19)
227 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
228 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
229 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
234 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
235 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
236 /* swap the floating point register banks */
237 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
238 /* Ignore bit change if simulating sh-dsp. */
241 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
242 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
243 saved_state
.asregs
.fregs
[1] = tmpf
;
247 /* sts relies on being able to read fpscr directly. */
248 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
249 #define SET_FPSCR(x) \
254 #define DSR (saved_state.asregs.sregs.named.fpscr)
256 #define RAISE_EXCEPTION(x) \
257 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
259 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
260 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
262 /* This function exists mainly for the purpose of setting a breakpoint to
263 catch simulated bus errors when running the simulator under GDB. */
266 raise_exception (int x
)
272 raise_buserror (void)
274 raise_exception (SIGBUS
);
277 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
278 forbidden_addr_bits, data, retval) \
280 if (addr & forbidden_addr_bits) \
285 else if ((addr & saved_state.asregs.xyram_select) \
286 == saved_state.asregs.xram_start) \
287 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
288 else if ((addr & saved_state.asregs.xyram_select) \
289 == saved_state.asregs.yram_start) \
290 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
291 else if ((unsigned) addr >> 24 == 0xf0 \
292 && bits_written == 32 && (data & 1) == 0) \
293 /* This invalidates (if not associative) or might invalidate \
294 (if associative) an instruction cache line. This is used for \
295 trampolines. Since we don't simulate the cache, this is a no-op \
296 as far as the simulator is concerned. */ \
300 if (bits_written == 8 && addr > 0x5000000) \
301 IOMEM (addr, 1, data); \
302 /* We can't do anything useful with the other stuff, so fail. */ \
308 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
309 being implemented by ../common/sim_resume.c and the below should
310 make a call to sim_engine_halt */
312 #define BUSERROR(addr, mask) ((addr) & (mask))
314 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
319 addr_func (addr, data); \
325 #define READ_BUSERROR(addr, mask, addr_func) \
329 return addr_func (addr); \
333 /* Define this to enable register lifetime checking.
334 The compiler generates "add #0,rn" insns to mark registers as invalid,
335 the simulator uses this info to call fail if it finds a ref to an invalid
336 register before a def
343 #define CREF(x) if (!valid[x]) fail ();
344 #define CDEF(x) valid[x] = 1;
345 #define UNDEF(x) valid[x] = 0;
352 static void parse_and_set_memory_size (SIM_DESC sd
, const char *str
);
353 static int IOMEM (int addr
, int write
, int value
);
354 static struct loop_bounds
get_loop_bounds (int, int, unsigned char *,
355 unsigned char *, int, int);
356 static void process_wlat_addr (int, int);
357 static void process_wwat_addr (int, int);
358 static void process_wbat_addr (int, int);
359 static int process_rlat_addr (int);
360 static int process_rwat_addr (int);
361 static int process_rbat_addr (int);
363 /* Floating point registers */
365 #define DR(n) (get_dr (n))
370 if (host_little_endian
)
377 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
378 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
382 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
385 #define SET_DR(n, EXP) set_dr ((n), (EXP))
387 set_dr (int n
, double exp
)
390 if (host_little_endian
)
398 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
399 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
402 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
405 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
406 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
408 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
409 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
411 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
412 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
413 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
415 #define RS saved_state.asregs.cregs.named.rs
416 #define RE saved_state.asregs.cregs.named.re
417 #define MOD (saved_state.asregs.cregs.named.mod)
420 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
421 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
423 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
424 #define DSP_GRD(n) DSP_R ((n) + 8)
425 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
430 #define Y0 DSP_R (10)
431 #define Y1 DSP_R (11)
432 #define M0 DSP_R (12)
433 #define A1G DSP_R (13)
434 #define M1 DSP_R (14)
435 #define A0G DSP_R (15)
436 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
437 #define MOD_ME DSP_GRD (17)
438 #define MOD_DELTA DSP_GRD (18)
440 #define FP_OP(n, OP, m) \
444 if (((n) & 1) || ((m) & 1)) \
445 RAISE_EXCEPTION (SIGILL); \
447 SET_DR (n, (DR (n) OP DR (m))); \
450 SET_FR (n, (FR (n) OP FR (m))); \
453 #define FP_UNARY(n, OP) \
458 RAISE_EXCEPTION (SIGILL); \
460 SET_DR (n, (OP (DR (n)))); \
463 SET_FR (n, (OP (FR (n)))); \
466 #define FP_CMP(n, OP, m) \
470 if (((n) & 1) || ((m) & 1)) \
471 RAISE_EXCEPTION (SIGILL); \
473 SET_SR_T (DR (n) OP DR (m)); \
476 SET_SR_T (FR (n) OP FR (m)); \
482 /* do we need to swap banks */
483 int old_gpr
= SR_MD
&& SR_RB
;
484 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
485 if (old_gpr
!= new_gpr
)
488 for (i
= 0; i
< 8; i
++)
490 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
491 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
492 saved_state
.asregs
.regs
[i
] = tmp
;
495 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
500 wlat_fast (unsigned char *memory
, int x
, int value
, int maskl
)
503 unsigned int *p
= (unsigned int *) (memory
+ x
);
504 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
509 wwat_fast (unsigned char *memory
, int x
, int value
, int maskw
, int endianw
)
512 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
513 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
518 wbat_fast (unsigned char *memory
, int x
, int value
, int maskb
)
520 unsigned char *p
= memory
+ (x
^ endianb
);
521 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
529 rlat_fast (unsigned char *memory
, int x
, int maskl
)
531 unsigned int *p
= (unsigned int *) (memory
+ x
);
532 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
538 rwat_fast (unsigned char *memory
, int x
, int maskw
, int endianw
)
540 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
541 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
547 riat_fast (unsigned char *insn_ptr
, int endianw
)
549 unsigned short *p
= (unsigned short *) ((uintptr_t) insn_ptr
^ endianw
);
555 rbat_fast (unsigned char *memory
, int x
, int maskb
)
557 unsigned char *p
= memory
+ (x
^ endianb
);
558 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
563 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
564 #define RLAT(x) (rlat_fast (memory, x, maskl))
565 #define RBAT(x) (rbat_fast (memory, x, maskb))
566 #define RIAT(p) (riat_fast ((p), endianw))
567 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
568 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
569 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
571 #define RUWAT(x) (RWAT (x) & 0xffff)
572 #define RSWAT(x) ((short) (RWAT (x)))
573 #define RSLAT(x) ((long) (RLAT (x)))
574 #define RSBAT(x) (SEXT (RBAT (x)))
576 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
578 do_rdat (unsigned char *memory
, int x
, int n
, int maskl
)
584 f0
= rlat_fast (memory
, x
+ 0, maskl
);
585 f1
= rlat_fast (memory
, x
+ 4, maskl
);
586 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
587 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
591 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
593 do_wdat (unsigned char *memory
, int x
, int n
, int maskl
)
599 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
600 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
601 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
602 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
607 process_wlat_addr (int addr
, int value
)
611 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
616 process_wwat_addr (int addr
, int value
)
620 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
625 process_wbat_addr (int addr
, int value
)
629 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
634 process_rlat_addr (int addr
)
638 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
643 process_rwat_addr (int addr
)
647 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
652 process_rbat_addr (int addr
)
656 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
660 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
661 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
662 #define SEXTW(y) ((int) ((short) y))
664 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
666 #define SEXT32(x) ((int) (x))
668 #define SIGN32(x) (SEXT32 (x) >> 31)
670 /* convert pointer from target to host value. */
671 #define PT2H(x) ((x) + memory)
672 /* convert pointer from host to target value. */
673 #define PH2T(x) ((x) - memory)
675 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
677 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
679 static int in_delay_slot
= 0;
680 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
682 #define CHECK_INSN_PTR(p) \
684 if (saved_state.asregs.exception || PH2T (p) & maskw) \
685 saved_state.asregs.insn_end = 0; \
686 else if (p < loop.end) \
687 saved_state.asregs.insn_end = loop.end; \
689 saved_state.asregs.insn_end = mem_end; \
702 do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
704 #define L(x) thislock = x;
705 #define TL(x) if ((x) == prevlock) stalls++;
706 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
710 #if defined(__GO32__)
711 int sim_memory_size
= 19;
713 int sim_memory_size
= 30;
716 static int sim_profile_size
= 17;
722 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
723 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
724 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
725 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
726 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
727 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
729 #define SCI_RDRF 0x40 /* Recieve data register full */
730 #define SCI_TDRE 0x80 /* Transmit data register empty */
733 IOMEM (int addr
, int write
, int value
)
762 return time ((long *) 0);
771 static FILE *profile_file
;
773 static INLINE
unsigned
777 n
= (n
<< 24 | (n
& 0xff00) << 8
778 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
782 static INLINE
unsigned short
783 swap16 (unsigned short n
)
786 n
= n
<< 8 | (n
& 0xff00) >> 8;
795 union { char b
[4]; int n
; } u
;
797 fwrite (u
.b
, 4, 1, profile_file
);
804 union { char b
[4]; int n
; } u
;
806 fwrite (u
.b
, 2, 1, profile_file
);
809 /* Turn a pointer in a register into a pointer into real memory. */
814 return (char *) (x
+ saved_state
.asregs
.memory
);
817 /* STR points to a zero-terminated string in target byte order. Return
818 the number of bytes that need to be converted to host byte order in order
819 to use this string as a zero-terminated string on the host.
820 (Not counting the rounding up needed to operate on entire words.) */
824 unsigned char *memory
= saved_state
.asregs
.memory
;
826 int endian
= endianb
;
831 for (end
= str
; memory
[end
^ endian
]; end
++) ;
832 return end
- str
+ 1;
836 strnswap (int str
, int len
)
840 if (! endianb
|| ! len
)
842 start
= (int *) ptr (str
& ~3);
843 end
= (int *) ptr (str
+ len
);
847 *start
= (old
<< 24 | (old
& 0xff00) << 8
848 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
854 /* Simulate a monitor trap, put the result into r0 and errno into r1
855 return offset by which to adjust pc. */
858 trap (SIM_DESC sd
, int i
, int *regs
, unsigned char *insn_ptr
,
859 unsigned char *memory
, int maskl
, int maskw
, int endianw
)
861 host_callback
*callback
= STATE_CALLBACK (sd
);
862 char **prog_argv
= STATE_PROG_ARGV (sd
);
867 printf ("%c", regs
[0]);
870 raise_exception (SIGQUIT
);
872 case 3: /* FIXME: for backwards compat, should be removed */
875 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
877 WLAT (countp
, RLAT (countp
) + 1);
889 #if !defined(__GO32__) && !defined(_WIN32)
893 /* This would work only if endianness matched between host and target.
894 Besides, it's quite dangerous. */
897 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]),
898 (char **) ptr (regs
[7]));
901 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]), 0);
906 regs
[0] = (BUSERROR (regs
[5], maskl
)
908 : pipe ((int *) ptr (regs
[5])));
913 regs
[0] = wait ((int *) ptr (regs
[5]));
915 #endif /* !defined(__GO32__) && !defined(_WIN32) */
918 strnswap (regs
[6], regs
[7]);
920 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
921 strnswap (regs
[6], regs
[7]);
924 strnswap (regs
[6], regs
[7]);
926 regs
[0] = (int) callback
->write_stdout (callback
,
927 ptr (regs
[6]), regs
[7]);
929 regs
[0] = (int) callback
->write (callback
, regs
[5],
930 ptr (regs
[6]), regs
[7]);
931 strnswap (regs
[6], regs
[7]);
934 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
937 regs
[0] = callback
->close (callback
,regs
[5]);
941 int len
= strswaplen (regs
[5]);
942 strnswap (regs
[5], len
);
943 regs
[0] = callback
->open (callback
, ptr (regs
[5]), regs
[6]);
944 strnswap (regs
[5], len
);
948 /* EXIT - caller can look in r5 to work out the reason */
949 raise_exception (SIGQUIT
);
953 case SYS_stat
: /* added at hmsi */
954 /* stat system call */
956 struct stat host_stat
;
958 int len
= strswaplen (regs
[5]);
960 strnswap (regs
[5], len
);
961 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
962 strnswap (regs
[5], len
);
966 WWAT (buf
, host_stat
.st_dev
);
968 WWAT (buf
, host_stat
.st_ino
);
970 WLAT (buf
, host_stat
.st_mode
);
972 WWAT (buf
, host_stat
.st_nlink
);
974 WWAT (buf
, host_stat
.st_uid
);
976 WWAT (buf
, host_stat
.st_gid
);
978 WWAT (buf
, host_stat
.st_rdev
);
980 WLAT (buf
, host_stat
.st_size
);
982 WLAT (buf
, host_stat
.st_atime
);
986 WLAT (buf
, host_stat
.st_mtime
);
990 WLAT (buf
, host_stat
.st_ctime
);
1004 int len
= strswaplen (regs
[5]);
1006 strnswap (regs
[5], len
);
1007 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1008 strnswap (regs
[5], len
);
1014 int len
= strswaplen (regs
[5]);
1016 strnswap (regs
[5], len
);
1017 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1018 strnswap (regs
[5], len
);
1023 /* Cast the second argument to void *, to avoid type mismatch
1024 if a prototype is present. */
1025 int len
= strswaplen (regs
[5]);
1027 strnswap (regs
[5], len
);
1028 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1029 strnswap (regs
[5], len
);
1033 regs
[0] = countargv (prog_argv
);
1036 if (regs
[5] < countargv (prog_argv
))
1037 regs
[0] = strlen (prog_argv
[regs
[5]]);
1042 if (regs
[5] < countargv (prog_argv
))
1044 /* Include the termination byte. */
1045 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1046 regs
[0] = sim_write (0, regs
[6], (void *) prog_argv
[regs
[5]], i
);
1052 regs
[0] = get_now ();
1055 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1059 int len
= strswaplen (regs
[5]);
1060 strnswap (regs
[5], len
);
1061 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1062 strnswap (regs
[5], len
);
1069 regs
[1] = callback
->get_errno (callback
);
1074 case 13: /* Set IBNR */
1075 IBNR
= regs
[0] & 0xffff;
1077 case 14: /* Set IBCR */
1078 IBCR
= regs
[0] & 0xffff;
1082 raise_exception (SIGTRAP
);
1091 div1 (int *R
, int iRn2
, int iRn1
/*, int T*/)
1094 unsigned char old_q
, tmp1
;
1097 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1099 R
[iRn1
] |= (unsigned long) T
;
1109 tmp1
= (R
[iRn1
] > tmp0
);
1116 SET_SR_Q ((unsigned char) (tmp1
== 0));
1123 tmp1
= (R
[iRn1
] < tmp0
);
1127 SET_SR_Q ((unsigned char) (tmp1
== 0));
1142 tmp1
= (R
[iRn1
] < tmp0
);
1149 SET_SR_Q ((unsigned char) (tmp1
== 0));
1156 tmp1
= (R
[iRn1
] > tmp0
);
1160 SET_SR_Q ((unsigned char) (tmp1
== 0));
1176 dmul_s (uint32_t rm
, uint32_t rn
)
1178 int64_t res
= (int64_t)(int32_t)rm
* (int64_t)(int32_t)rn
;
1179 MACH
= (uint32_t)((uint64_t)res
>> 32);
1180 MACL
= (uint32_t)res
;
1184 dmul_u (uint32_t rm
, uint32_t rn
)
1186 uint64_t res
= (uint64_t)(uint32_t)rm
* (uint64_t)(uint32_t)rn
;
1187 MACH
= (uint32_t)(res
>> 32);
1188 MACL
= (uint32_t)res
;
1192 macw (int *regs
, unsigned char *memory
, int n
, int m
, int endianw
)
1195 long prod
, macl
, sum
;
1197 tempm
=RSWAT (regs
[m
]); regs
[m
]+=2;
1198 tempn
=RSWAT (regs
[n
]); regs
[n
]+=2;
1201 prod
= (long) (short) tempm
* (long) (short) tempn
;
1205 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1207 /* MACH's lsb is a sticky overflow bit. */
1209 /* Store the smallest negative number in MACL if prod is
1210 negative, and the largest positive number otherwise. */
1211 sum
= 0x7fffffff + (prod
< 0);
1217 /* Add to MACH the sign extended product, and carry from low sum. */
1218 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1219 /* Sign extend at 10:th bit in MACH. */
1220 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1226 macl (int *regs
, unsigned char *memory
, int n
, int m
)
1233 tempm
= RSLAT (regs
[m
]);
1236 tempn
= RSLAT (regs
[n
]);
1242 mac64
= ((long long) macl
& 0xffffffff) |
1243 ((long long) mach
& 0xffffffff) << 32;
1245 ans
= (long long) tempm
* (long long) tempn
; /* Multiply 32bit * 32bit */
1247 mac64
+= ans
; /* Accumulate 64bit + 64 bit */
1249 macl
= (long) (mac64
& 0xffffffff);
1250 mach
= (long) ((mac64
>> 32) & 0xffffffff);
1252 if (S
) /* Store only 48 bits of the result */
1254 if (mach
< 0) /* Result is negative */
1256 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1257 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1260 mach
= mach
& 0x00007fff; /* Postive Result */
1291 /* Do extended displacement move instructions. */
1293 do_long_move_insn (int op
, int disp12
, int m
, int n
, int *thatlock
)
1296 int thislock
= *thatlock
;
1297 int endianw
= global_endianw
;
1298 int *R
= &(saved_state
.asregs
.regs
[0]);
1299 unsigned char *memory
= saved_state
.asregs
.memory
;
1300 int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1301 unsigned char *insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1304 case MOVB_RM
: /* signed */
1305 WBAT (disp12
* 1 + R
[n
], R
[m
]);
1308 WWAT (disp12
* 2 + R
[n
], R
[m
]);
1311 WLAT (disp12
* 4 + R
[n
], R
[m
]);
1313 case FMOV_RM
: /* floating point */
1317 WDAT (R
[n
] + 8 * disp12
, m
);
1320 WLAT (R
[n
] + 4 * disp12
, FI (m
));
1323 R
[n
] = RSBAT (disp12
* 1 + R
[m
]);
1327 R
[n
] = RSWAT (disp12
* 2 + R
[m
]);
1331 R
[n
] = RLAT (disp12
* 4 + R
[m
]);
1337 RDAT (R
[m
] + 8 * disp12
, n
);
1340 SET_FI (n
, RLAT (R
[m
] + 4 * disp12
));
1342 case MOVU_BMR
: /* unsigned */
1343 R
[n
] = RBAT (disp12
* 1 + R
[m
]);
1347 R
[n
] = RWAT (disp12
* 2 + R
[m
]);
1351 RAISE_EXCEPTION (SIGINT
);
1354 saved_state
.asregs
.memstalls
+= memstalls
;
1355 *thatlock
= thislock
;
1358 /* Do binary logical bit-manipulation insns. */
1360 do_blog_insn (int imm
, int addr
, int binop
,
1361 unsigned char *memory
, int maskb
)
1363 int oldval
= RBAT (addr
);
1366 case B_BCLR
: /* bclr.b */
1367 WBAT (addr
, oldval
& ~imm
);
1369 case B_BSET
: /* bset.b */
1370 WBAT (addr
, oldval
| imm
);
1372 case B_BST
: /* bst.b */
1374 WBAT (addr
, oldval
| imm
);
1376 WBAT (addr
, oldval
& ~imm
);
1378 case B_BLD
: /* bld.b */
1379 SET_SR_T ((oldval
& imm
) != 0);
1381 case B_BAND
: /* band.b */
1382 SET_SR_T (T
&& ((oldval
& imm
) != 0));
1384 case B_BOR
: /* bor.b */
1385 SET_SR_T (T
|| ((oldval
& imm
) != 0));
1387 case B_BXOR
: /* bxor.b */
1388 SET_SR_T (T
^ ((oldval
& imm
) != 0));
1390 case B_BLDNOT
: /* bldnot.b */
1391 SET_SR_T ((oldval
& imm
) == 0);
1393 case B_BANDNOT
: /* bandnot.b */
1394 SET_SR_T (T
&& ((oldval
& imm
) == 0));
1396 case B_BORNOT
: /* bornot.b */
1397 SET_SR_T (T
|| ((oldval
& imm
) == 0));
1403 fsca_s (int in
, double (*f
) (double))
1405 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1406 double result
= (*f
) (rad
);
1407 double error
, upper
, lower
, frac
;
1410 /* Search the value with the maximum error that is still within the
1411 architectural spec. */
1412 error
= ldexp (1., -21);
1413 /* compensate for calculation inaccuracy by reducing error. */
1414 error
= error
- ldexp (1., -50);
1415 upper
= result
+ error
;
1416 frac
= frexp (upper
, &exp
);
1417 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1418 lower
= result
- error
;
1419 frac
= frexp (lower
, &exp
);
1420 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1421 return abs (upper
- result
) >= abs (lower
- result
) ? upper
: lower
;
1427 double result
= 1. / sqrt (in
);
1429 double frac
, upper
, lower
, error
, eps
;
1432 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1433 /* Search the value with the maximum error that is still within the
1434 architectural spec. */
1435 frac
= frexp (result
, &exp
);
1436 frac
= ldexp (frac
, 24);
1437 error
= 4.0; /* 1 << 24-1-21 */
1438 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1439 eps
= ldexp (1., -29);
1440 upper
= floor (frac
+ error
- eps
);
1441 if (upper
> 16777216.)
1442 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1443 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1444 if (lower
> 8388608.)
1445 lower
= ceil (frac
- error
+ eps
);
1446 upper
= ldexp (upper
, exp
- 24);
1447 lower
= ldexp (lower
, exp
- 24);
1448 return upper
- result
>= result
- lower
? upper
: lower
;
1452 /* GET_LOOP_BOUNDS {EXTENDED}
1453 These two functions compute the actual starting and ending point
1454 of the repeat loop, based on the RS and RE registers (repeat start,
1455 repeat stop). The extended version is called for LDRC, and the
1456 regular version is called for SETRC. The difference is that for
1457 LDRC, the loop start and end instructions are literally the ones
1458 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1460 static struct loop_bounds
1461 get_loop_bounds_ext (int rs
, int re
, unsigned char *memory
,
1462 unsigned char *mem_end
, int maskw
, int endianw
)
1464 struct loop_bounds loop
;
1466 /* FIXME: should I verify RS < RE? */
1467 loop
.start
= PT2H (RS
); /* FIXME not using the params? */
1468 loop
.end
= PT2H (RE
& ~1); /* Ignore bit 0 of RE. */
1469 SKIP_INSN (loop
.end
);
1470 if (loop
.end
>= mem_end
)
1471 loop
.end
= PT2H (0);
1475 static struct loop_bounds
1476 get_loop_bounds (int rs
, int re
, unsigned char *memory
, unsigned char *mem_end
,
1477 int maskw
, int endianw
)
1479 struct loop_bounds loop
;
1485 loop
.start
= PT2H (RE
- 4);
1486 SKIP_INSN (loop
.start
);
1487 loop
.end
= loop
.start
;
1489 SKIP_INSN (loop
.end
);
1491 SKIP_INSN (loop
.end
);
1492 SKIP_INSN (loop
.end
);
1496 loop
.start
= PT2H (RS
);
1497 loop
.end
= PT2H (RE
- 4);
1498 SKIP_INSN (loop
.end
);
1499 SKIP_INSN (loop
.end
);
1500 SKIP_INSN (loop
.end
);
1501 SKIP_INSN (loop
.end
);
1503 if (loop
.end
>= mem_end
)
1504 loop
.end
= PT2H (0);
1507 loop
.end
= PT2H (0);
1512 static void ppi_insn ();
1516 /* Provide calloc / free versions that use an anonymous mmap. This can
1517 significantly cut the start-up time when a large simulator memory is
1518 required, because pages are only zeroed on demand. */
1519 #ifdef MAP_ANONYMOUS
1521 mcalloc (size_t nmemb
, size_t size
)
1527 return mmap (0, size
, PROT_READ
| PROT_WRITE
, MAP_PRIVATE
| MAP_ANONYMOUS
,
1531 #define mfree(start,length) munmap ((start), (length))
1533 #define mcalloc calloc
1534 #define mfree(start,length) free(start)
1537 /* Set the memory size to the power of two provided. */
1540 sim_size (int power
)
1542 sim_memory_size
= power
;
1544 if (saved_state
.asregs
.memory
)
1546 mfree (saved_state
.asregs
.memory
, saved_state
.asregs
.msize
);
1549 saved_state
.asregs
.msize
= 1 << power
;
1551 saved_state
.asregs
.memory
=
1552 (unsigned char *) mcalloc (1, saved_state
.asregs
.msize
);
1554 if (!saved_state
.asregs
.memory
)
1557 "Not enough VM for simulation of %d bytes of RAM\n",
1558 saved_state
.asregs
.msize
);
1560 saved_state
.asregs
.msize
= 1;
1561 saved_state
.asregs
.memory
= (unsigned char *) mcalloc (1, 1);
1566 init_dsp (struct bfd
*abfd
)
1568 int was_dsp
= target_dsp
;
1569 unsigned long mach
= bfd_get_mach (abfd
);
1571 if (mach
== bfd_mach_sh_dsp
||
1572 mach
== bfd_mach_sh4al_dsp
||
1573 mach
== bfd_mach_sh3_dsp
)
1575 int ram_area_size
, xram_start
, yram_start
;
1579 if (mach
== bfd_mach_sh_dsp
)
1581 /* SH7410 (orig. sh-sdp):
1582 4KB each for X & Y memory;
1583 On-chip X RAM 0x0800f000-0x0800ffff
1584 On-chip Y RAM 0x0801f000-0x0801ffff */
1585 xram_start
= 0x0800f000;
1586 ram_area_size
= 0x1000;
1588 if (mach
== bfd_mach_sh3_dsp
|| mach
== bfd_mach_sh4al_dsp
)
1591 8KB each for X & Y memory;
1592 On-chip X RAM 0x1000e000-0x1000ffff
1593 On-chip Y RAM 0x1001e000-0x1001ffff */
1594 xram_start
= 0x1000e000;
1595 ram_area_size
= 0x2000;
1597 yram_start
= xram_start
+ 0x10000;
1598 new_select
= ~(ram_area_size
- 1);
1599 if (saved_state
.asregs
.xyram_select
!= new_select
)
1601 saved_state
.asregs
.xyram_select
= new_select
;
1602 free (saved_state
.asregs
.xmem
);
1603 free (saved_state
.asregs
.ymem
);
1604 saved_state
.asregs
.xmem
=
1605 (unsigned char *) calloc (1, ram_area_size
);
1606 saved_state
.asregs
.ymem
=
1607 (unsigned char *) calloc (1, ram_area_size
);
1609 /* Disable use of X / Y mmeory if not allocated. */
1610 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1612 saved_state
.asregs
.xyram_select
= 0;
1613 if (saved_state
.asregs
.xmem
)
1614 free (saved_state
.asregs
.xmem
);
1615 if (saved_state
.asregs
.ymem
)
1616 free (saved_state
.asregs
.ymem
);
1619 saved_state
.asregs
.xram_start
= xram_start
;
1620 saved_state
.asregs
.yram_start
= yram_start
;
1621 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1622 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1627 if (saved_state
.asregs
.xyram_select
)
1629 saved_state
.asregs
.xyram_select
= 0;
1630 free (saved_state
.asregs
.xmem
);
1631 free (saved_state
.asregs
.ymem
);
1635 if (! saved_state
.asregs
.xyram_select
)
1637 saved_state
.asregs
.xram_start
= 1;
1638 saved_state
.asregs
.yram_start
= 1;
1641 if (saved_state
.asregs
.regstack
== NULL
)
1642 saved_state
.asregs
.regstack
=
1643 calloc (512, sizeof *saved_state
.asregs
.regstack
);
1645 if (target_dsp
!= was_dsp
)
1649 for (i
= ARRAY_SIZE (sh_dsp_table
) - 1; i
>= 0; i
--)
1651 tmp
= sh_jump_table
[0xf000 + i
];
1652 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1653 sh_dsp_table
[i
] = tmp
;
1659 init_pointers (void)
1661 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1663 sim_size (sim_memory_size
);
1666 if (saved_state
.asregs
.profile
&& !profile_file
)
1668 profile_file
= fopen ("gmon.out", "wb");
1669 /* Seek to where to put the call arc data */
1670 nsamples
= (1 << sim_profile_size
);
1672 fseek (profile_file
, nsamples
* 2 + 12, 0);
1676 fprintf (stderr
, "Can't open gmon.out\n");
1680 saved_state
.asregs
.profile_hist
=
1681 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1694 p
= saved_state
.asregs
.profile_hist
;
1696 maxpc
= (1 << sim_profile_size
);
1698 fseek (profile_file
, 0L, 0);
1699 swapout (minpc
<< PROFILE_SHIFT
);
1700 swapout (maxpc
<< PROFILE_SHIFT
);
1701 swapout (nsamples
* 2 + 12);
1702 for (i
= 0; i
< nsamples
; i
++)
1703 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1708 gotcall (int from
, int to
)
1715 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1718 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1720 register unsigned char *insn_ptr
;
1721 unsigned char *mem_end
;
1722 struct loop_bounds loop
;
1723 register int cycles
= 0;
1724 register int stalls
= 0;
1725 register int memstalls
= 0;
1726 register int insts
= 0;
1727 register int prevlock
;
1731 register int thislock
;
1733 register unsigned int doprofile
;
1734 register int pollcount
= 0;
1735 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1736 endianb is used less often. */
1737 register int endianw
= global_endianw
;
1739 int tick_start
= get_now ();
1740 void (*prev_fpe
) ();
1742 register unsigned short *jump_table
= sh_jump_table
;
1744 register int *R
= &(saved_state
.asregs
.regs
[0]);
1750 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1751 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1752 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1753 register unsigned char *memory
;
1754 register unsigned int sbit
= ((unsigned int) 1 << 31);
1756 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1759 saved_state
.asregs
.exception
= 0;
1761 memory
= saved_state
.asregs
.memory
;
1762 mem_end
= memory
+ saved_state
.asregs
.msize
;
1765 loop
= get_loop_bounds_ext (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1767 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1769 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1770 CHECK_INSN_PTR (insn_ptr
);
1773 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1775 /*T = GET_SR () & SR_MASK_T;*/
1776 prevlock
= saved_state
.asregs
.prevlock
;
1777 thislock
= saved_state
.asregs
.thislock
;
1778 doprofile
= saved_state
.asregs
.profile
;
1780 /* If profiling not enabled, disable it by asking for
1781 profiles infrequently. */
1786 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1788 if (saved_state
.asregs
.exception
)
1789 /* This can happen if we've already been single-stepping and
1790 encountered a loop end. */
1791 saved_state
.asregs
.insn_end
= insn_ptr
;
1794 saved_state
.asregs
.exception
= SIGTRAP
;
1795 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1799 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1801 register unsigned int iword
= RIAT (insn_ptr
);
1802 register unsigned int ult
;
1803 register unsigned char *nip
= insn_ptr
+ 2;
1816 if (--pollcount
< 0)
1818 host_callback
*callback
= STATE_CALLBACK (sd
);
1820 pollcount
= POLL_QUIT_INTERVAL
;
1821 if ((*callback
->poll_quit
) != NULL
1822 && (*callback
->poll_quit
) (callback
))
1829 prevlock
= thislock
;
1833 if (cycles
>= doprofile
)
1836 saved_state
.asregs
.cycles
+= doprofile
;
1837 cycles
-= doprofile
;
1838 if (saved_state
.asregs
.profile_hist
)
1840 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1843 int i
= saved_state
.asregs
.profile_hist
[n
];
1845 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1852 if (saved_state
.asregs
.insn_end
== loop
.end
)
1854 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1856 insn_ptr
= loop
.start
;
1859 saved_state
.asregs
.insn_end
= mem_end
;
1860 loop
.end
= PT2H (0);
1865 if (saved_state
.asregs
.exception
== SIGILL
1866 || saved_state
.asregs
.exception
== SIGBUS
)
1870 /* Check for SIGBUS due to insn fetch. */
1871 else if (! saved_state
.asregs
.exception
)
1872 saved_state
.asregs
.exception
= SIGBUS
;
1874 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1875 saved_state
.asregs
.cycles
+= cycles
;
1876 saved_state
.asregs
.stalls
+= stalls
;
1877 saved_state
.asregs
.memstalls
+= memstalls
;
1878 saved_state
.asregs
.insts
+= insts
;
1879 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1881 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1884 saved_state
.asregs
.prevlock
= prevlock
;
1885 saved_state
.asregs
.thislock
= thislock
;
1892 signal (SIGFPE
, prev_fpe
);
1896 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1902 for (i
= 0; i
< size
; i
++)
1904 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1910 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1916 for (i
= 0; i
< size
; i
++)
1918 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1923 static int gdb_bank_number
;
1933 sh_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1938 val
= swap (* (int *) memory
);
1941 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
1942 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
1943 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
1944 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
1945 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
1946 case SIM_SH_R15_REGNUM
:
1947 saved_state
.asregs
.regs
[rn
] = val
;
1949 case SIM_SH_PC_REGNUM
:
1950 saved_state
.asregs
.pc
= val
;
1952 case SIM_SH_PR_REGNUM
:
1955 case SIM_SH_GBR_REGNUM
:
1958 case SIM_SH_VBR_REGNUM
:
1961 case SIM_SH_MACH_REGNUM
:
1964 case SIM_SH_MACL_REGNUM
:
1967 case SIM_SH_SR_REGNUM
:
1970 case SIM_SH_FPUL_REGNUM
:
1973 case SIM_SH_FPSCR_REGNUM
:
1976 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
1977 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
1978 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
1979 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
1980 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
1981 case SIM_SH_FR15_REGNUM
:
1982 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
1984 case SIM_SH_DSR_REGNUM
:
1987 case SIM_SH_A0G_REGNUM
:
1990 case SIM_SH_A0_REGNUM
:
1993 case SIM_SH_A1G_REGNUM
:
1996 case SIM_SH_A1_REGNUM
:
1999 case SIM_SH_M0_REGNUM
:
2002 case SIM_SH_M1_REGNUM
:
2005 case SIM_SH_X0_REGNUM
:
2008 case SIM_SH_X1_REGNUM
:
2011 case SIM_SH_Y0_REGNUM
:
2014 case SIM_SH_Y1_REGNUM
:
2017 case SIM_SH_MOD_REGNUM
:
2020 case SIM_SH_RS_REGNUM
:
2023 case SIM_SH_RE_REGNUM
:
2026 case SIM_SH_SSR_REGNUM
:
2029 case SIM_SH_SPC_REGNUM
:
2032 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2033 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2034 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2035 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2036 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2037 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2038 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2040 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2041 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
] = val
;
2045 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2047 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2049 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2050 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2051 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2052 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2053 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2055 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2056 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8] = val
;
2060 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2062 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2064 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2065 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2066 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2067 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2068 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2070 case SIM_SH_TBR_REGNUM
:
2073 case SIM_SH_IBNR_REGNUM
:
2076 case SIM_SH_IBCR_REGNUM
:
2079 case SIM_SH_BANK_REGNUM
:
2080 /* This is a pseudo-register maintained just for gdb.
2081 It tells us what register bank gdb would like to read/write. */
2082 gdb_bank_number
= val
;
2084 case SIM_SH_BANK_MACL_REGNUM
:
2085 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
] = val
;
2087 case SIM_SH_BANK_GBR_REGNUM
:
2088 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
] = val
;
2090 case SIM_SH_BANK_PR_REGNUM
:
2091 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
] = val
;
2093 case SIM_SH_BANK_IVN_REGNUM
:
2094 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
] = val
;
2096 case SIM_SH_BANK_MACH_REGNUM
:
2097 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
] = val
;
2106 sh_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
2113 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2114 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2115 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2116 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2117 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2118 case SIM_SH_R15_REGNUM
:
2119 val
= saved_state
.asregs
.regs
[rn
];
2121 case SIM_SH_PC_REGNUM
:
2122 val
= saved_state
.asregs
.pc
;
2124 case SIM_SH_PR_REGNUM
:
2127 case SIM_SH_GBR_REGNUM
:
2130 case SIM_SH_VBR_REGNUM
:
2133 case SIM_SH_MACH_REGNUM
:
2136 case SIM_SH_MACL_REGNUM
:
2139 case SIM_SH_SR_REGNUM
:
2142 case SIM_SH_FPUL_REGNUM
:
2145 case SIM_SH_FPSCR_REGNUM
:
2148 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2149 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2150 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2151 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2152 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2153 case SIM_SH_FR15_REGNUM
:
2154 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2156 case SIM_SH_DSR_REGNUM
:
2159 case SIM_SH_A0G_REGNUM
:
2162 case SIM_SH_A0_REGNUM
:
2165 case SIM_SH_A1G_REGNUM
:
2168 case SIM_SH_A1_REGNUM
:
2171 case SIM_SH_M0_REGNUM
:
2174 case SIM_SH_M1_REGNUM
:
2177 case SIM_SH_X0_REGNUM
:
2180 case SIM_SH_X1_REGNUM
:
2183 case SIM_SH_Y0_REGNUM
:
2186 case SIM_SH_Y1_REGNUM
:
2189 case SIM_SH_MOD_REGNUM
:
2192 case SIM_SH_RS_REGNUM
:
2195 case SIM_SH_RE_REGNUM
:
2198 case SIM_SH_SSR_REGNUM
:
2201 case SIM_SH_SPC_REGNUM
:
2204 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2205 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2206 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2207 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2208 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2209 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2210 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2212 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2213 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
];
2216 val
= (SR_MD
&& SR_RB
2217 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2218 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2220 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2221 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2222 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2223 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2224 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2226 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2227 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8];
2230 val
= (! SR_MD
|| ! SR_RB
2231 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2232 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2234 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2235 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2236 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2237 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2238 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2240 case SIM_SH_TBR_REGNUM
:
2243 case SIM_SH_IBNR_REGNUM
:
2246 case SIM_SH_IBCR_REGNUM
:
2249 case SIM_SH_BANK_REGNUM
:
2250 /* This is a pseudo-register maintained just for gdb.
2251 It tells us what register bank gdb would like to read/write. */
2252 val
= gdb_bank_number
;
2254 case SIM_SH_BANK_MACL_REGNUM
:
2255 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
];
2257 case SIM_SH_BANK_GBR_REGNUM
:
2258 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
];
2260 case SIM_SH_BANK_PR_REGNUM
:
2261 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
];
2263 case SIM_SH_BANK_IVN_REGNUM
:
2264 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
];
2266 case SIM_SH_BANK_MACH_REGNUM
:
2267 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
];
2272 * (int *) memory
= swap (val
);
2277 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
2279 /* The SH simulator uses SIGQUIT to indicate that the program has
2280 exited, so we must check for it here and translate it to exit. */
2281 if (saved_state
.asregs
.exception
== SIGQUIT
)
2283 *reason
= sim_exited
;
2284 *sigrc
= saved_state
.asregs
.regs
[5];
2288 *reason
= sim_stopped
;
2289 *sigrc
= saved_state
.asregs
.exception
;
2294 sim_info (SIM_DESC sd
, int verbose
)
2297 (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2298 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2300 sim_io_printf (sd
, "\n\n# instructions executed %10d\n",
2301 saved_state
.asregs
.insts
);
2302 sim_io_printf (sd
, "# cycles %10d\n",
2303 saved_state
.asregs
.cycles
);
2304 sim_io_printf (sd
, "# pipeline stalls %10d\n",
2305 saved_state
.asregs
.stalls
);
2306 sim_io_printf (sd
, "# misaligned load/store %10d\n",
2307 saved_state
.asregs
.memstalls
);
2308 sim_io_printf (sd
, "# real time taken %10.4f\n", timetaken
);
2309 sim_io_printf (sd
, "# virtual time taken %10.4f\n", virttime
);
2310 sim_io_printf (sd
, "# profiling size %10d\n", sim_profile_size
);
2311 sim_io_printf (sd
, "# profiling frequency %10d\n",
2312 saved_state
.asregs
.profile
);
2313 sim_io_printf (sd
, "# profile maxpc %10x\n",
2314 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2318 sim_io_printf (sd
, "# cycles/second %10d\n",
2319 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2320 sim_io_printf (sd
, "# simulation ratio %10.4f\n",
2321 virttime
/ timetaken
);
2326 sh_pc_get (sim_cpu
*cpu
)
2328 return saved_state
.asregs
.pc
;
2332 sh_pc_set (sim_cpu
*cpu
, sim_cia pc
)
2334 saved_state
.asregs
.pc
= pc
;
2338 free_state (SIM_DESC sd
)
2340 if (STATE_MODULES (sd
) != NULL
)
2341 sim_module_uninstall (sd
);
2342 sim_cpu_free_all (sd
);
2343 sim_state_free (sd
);
2347 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
2348 struct bfd
*abfd
, char * const *argv
)
2360 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
2361 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
2363 /* The cpu data is kept in a separately allocated chunk of memory. */
2364 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
2370 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
2376 /* The parser will print an error message for us, so we silently return. */
2377 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
2383 /* Check for/establish the a reference program image. */
2384 if (sim_analyze_program (sd
,
2385 (STATE_PROG_ARGV (sd
) != NULL
2386 ? *STATE_PROG_ARGV (sd
)
2387 : NULL
), abfd
) != SIM_RC_OK
)
2393 /* Configure/verify the target byte order and other runtime
2394 configuration options. */
2395 if (sim_config (sd
) != SIM_RC_OK
)
2397 sim_module_uninstall (sd
);
2401 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
2403 /* Uninstall the modules to avoid memory leaks,
2404 file descriptor leaks, etc. */
2405 sim_module_uninstall (sd
);
2409 /* CPU specific initialization. */
2410 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
2412 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
2414 CPU_REG_FETCH (cpu
) = sh_reg_fetch
;
2415 CPU_REG_STORE (cpu
) = sh_reg_store
;
2416 CPU_PC_FETCH (cpu
) = sh_pc_get
;
2417 CPU_PC_STORE (cpu
) = sh_pc_set
;
2420 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2423 parse_and_set_memory_size (sd
, *p
);
2429 for (i
= 4; (i
-= 2) >= 0; )
2430 mem_word
.s
[i
>> 1] = i
;
2431 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2433 for (i
= 4; --i
>= 0; )
2435 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2441 parse_and_set_memory_size (SIM_DESC sd
, const char *str
)
2445 n
= strtol (str
, NULL
, 10);
2446 if (n
> 0 && n
<= 31)
2447 sim_memory_size
= n
;
2449 sim_io_printf (sd
, "Bad memory size %d; must be 1 to 31, inclusive\n", n
);
2453 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
2454 char * const *argv
, char * const *env
)
2456 /* Clear the registers. */
2457 memset (&saved_state
, 0,
2458 (char*) &saved_state
.asregs
.end_of_registers
- (char*) &saved_state
);
2461 if (prog_bfd
!= NULL
)
2462 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2464 /* Set the bfd machine type. */
2465 if (prog_bfd
!= NULL
)
2466 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2468 if (prog_bfd
!= NULL
)
2469 init_dsp (prog_bfd
);
2475 sim_do_command (SIM_DESC sd
, const char *cmd
)
2477 const char *sms_cmd
= "set-memory-size";
2480 if (cmd
== NULL
|| *cmd
== '\0')
2485 cmdsize
= strlen (sms_cmd
);
2486 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0
2487 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2489 parse_and_set_memory_size (sd
, cmd
+ cmdsize
+ 1);
2491 else if (strcmp (cmd
, "help") == 0)
2493 sim_io_printf (sd
, "List of SH simulator commands:\n\n");
2494 sim_io_printf (sd
, "set-memory-size <n> -- Set the number of address bits to use\n");
2495 sim_io_printf (sd
, "\n");
2499 sim_io_printf (sd
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);