1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
33 # define MAP_FAILED -1
35 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
36 # define MAP_ANONYMOUS MAP_ANON
42 #ifdef HAVE_SYS_STAT_H
53 #include "gdb/callback.h"
54 #include "gdb/remote-sim.h"
55 #include "gdb/sim-sh.h"
59 #include "sim-options.h"
61 #include "targ-vals.h"
66 #include <float.h> /* Needed for _isnan() */
71 #define SIGBUS SIGSEGV
75 #define SIGQUIT SIGTERM
82 /* TODO: Stop using these names. */
86 extern unsigned short sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
88 #define O_RECOMPILE 85
90 #define DISASSEMBLER_TABLE
92 /* Define the rate at which the simulator should poll the host
94 #define POLL_QUIT_INTERVAL 0x60000
96 /* TODO: Move into sim_cpu. */
97 saved_state_type saved_state
;
99 struct loop_bounds
{ unsigned char *start
, *end
; };
101 /* These variables are at file scope so that functions other than
102 sim_resume can use the fetch/store macros */
104 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
105 static int global_endianw
, endianb
;
106 static int target_dsp
;
107 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE)
109 static int maskw
= 0;
110 static int maskl
= 0;
112 /* Short hand definitions of the registers */
114 #define SBIT(x) ((x)&sbit)
115 #define R0 saved_state.asregs.regs[0]
116 #define Rn saved_state.asregs.regs[n]
117 #define Rm saved_state.asregs.regs[m]
118 #define UR0 (unsigned int) (saved_state.asregs.regs[0])
119 #define UR (unsigned int) R
120 #define UR (unsigned int) R
121 #define SR0 saved_state.asregs.regs[0]
122 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
123 #define GBR saved_state.asregs.cregs.named.gbr
124 #define VBR saved_state.asregs.cregs.named.vbr
125 #define DBR saved_state.asregs.cregs.named.dbr
126 #define TBR saved_state.asregs.cregs.named.tbr
127 #define IBCR saved_state.asregs.cregs.named.ibcr
128 #define IBNR saved_state.asregs.cregs.named.ibnr
129 #define BANKN (saved_state.asregs.cregs.named.ibnr & 0x1ff)
130 #define ME ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
131 #define SSR saved_state.asregs.cregs.named.ssr
132 #define SPC saved_state.asregs.cregs.named.spc
133 #define SGR saved_state.asregs.cregs.named.sgr
134 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
135 #define MACH saved_state.asregs.sregs.named.mach
136 #define MACL saved_state.asregs.sregs.named.macl
137 #define PR saved_state.asregs.sregs.named.pr
138 #define FPUL saved_state.asregs.sregs.named.fpul
144 /* Alternate bank of registers r0-r7 */
146 /* Note: code controling SR handles flips between BANK0 and BANK1 */
147 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
148 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
153 #define SR_MASK_BO (1 << 14)
154 #define SR_MASK_CS (1 << 13)
155 #define SR_MASK_DMY (1 << 11)
156 #define SR_MASK_DMX (1 << 10)
157 #define SR_MASK_M (1 << 9)
158 #define SR_MASK_Q (1 << 8)
159 #define SR_MASK_I (0xf << 4)
160 #define SR_MASK_S (1 << 1)
161 #define SR_MASK_T (1 << 0)
163 #define SR_MASK_BL (1 << 28)
164 #define SR_MASK_RB (1 << 29)
165 #define SR_MASK_MD (1 << 30)
166 #define SR_MASK_RC 0x0fff0000
167 #define SR_RC_INCREMENT -0x00010000
169 #define BO ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
170 #define CS ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
171 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
172 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
173 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
174 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
175 #define LDST ((saved_state.asregs.cregs.named.ldst) != 0)
177 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
178 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
179 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
180 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
181 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
182 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
184 /* Note: don't use this for privileged bits */
185 #define SET_SR_BIT(EXP, BIT) \
188 saved_state.asregs.cregs.named.sr |= (BIT); \
190 saved_state.asregs.cregs.named.sr &= ~(BIT); \
193 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
194 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
195 #define SET_BANKN(EXP) \
197 IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
199 #define SET_ME(EXP) \
201 IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
203 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
204 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
205 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
206 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
207 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
209 /* stc currently relies on being able to read SR without modifications. */
210 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
212 #define SET_SR(x) set_sr (x)
215 (saved_state.asregs.cregs.named.sr \
216 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
218 /* Manipulate FPSCR */
220 #define FPSCR_MASK_FR (1 << 21)
221 #define FPSCR_MASK_SZ (1 << 20)
222 #define FPSCR_MASK_PR (1 << 19)
224 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
225 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
226 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
231 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
232 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
233 /* swap the floating point register banks */
234 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
235 /* Ignore bit change if simulating sh-dsp. */
238 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
239 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
240 saved_state
.asregs
.fregs
[1] = tmpf
;
244 /* sts relies on being able to read fpscr directly. */
245 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
246 #define SET_FPSCR(x) \
251 #define DSR (saved_state.asregs.sregs.named.fpscr)
253 #define RAISE_EXCEPTION(x) \
254 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
256 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
257 if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
259 /* This function exists mainly for the purpose of setting a breakpoint to
260 catch simulated bus errors when running the simulator under GDB. */
263 raise_exception (int x
)
269 raise_buserror (void)
271 raise_exception (SIGBUS
);
274 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
275 forbidden_addr_bits, data, retval) \
277 if (addr & forbidden_addr_bits) \
282 else if ((addr & saved_state.asregs.xyram_select) \
283 == saved_state.asregs.xram_start) \
284 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
285 else if ((addr & saved_state.asregs.xyram_select) \
286 == saved_state.asregs.yram_start) \
287 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
288 else if ((unsigned) addr >> 24 == 0xf0 \
289 && bits_written == 32 && (data & 1) == 0) \
290 /* This invalidates (if not associative) or might invalidate \
291 (if associative) an instruction cache line. This is used for \
292 trampolines. Since we don't simulate the cache, this is a no-op \
293 as far as the simulator is concerned. */ \
297 if (bits_written == 8 && addr > 0x5000000) \
298 IOMEM (addr, 1, data); \
299 /* We can't do anything useful with the other stuff, so fail. */ \
305 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
306 being implemented by ../common/sim_resume.c and the below should
307 make a call to sim_engine_halt */
309 #define BUSERROR(addr, mask) ((addr) & (mask))
311 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
316 addr_func (addr, data); \
322 #define READ_BUSERROR(addr, mask, addr_func) \
326 return addr_func (addr); \
330 /* Define this to enable register lifetime checking.
331 The compiler generates "add #0,rn" insns to mark registers as invalid,
332 the simulator uses this info to call fail if it finds a ref to an invalid
333 register before a def
340 #define CREF(x) if (!valid[x]) fail ();
341 #define CDEF(x) valid[x] = 1;
342 #define UNDEF(x) valid[x] = 0;
349 static void parse_and_set_memory_size (SIM_DESC sd
, const char *str
);
350 static int IOMEM (int addr
, int write
, int value
);
351 static struct loop_bounds
get_loop_bounds (int, int, unsigned char *,
352 unsigned char *, int, int);
353 static void process_wlat_addr (int, int);
354 static void process_wwat_addr (int, int);
355 static void process_wbat_addr (int, int);
356 static int process_rlat_addr (int);
357 static int process_rwat_addr (int);
358 static int process_rbat_addr (int);
360 /* Floating point registers */
362 #define DR(n) (get_dr (n))
367 if (host_little_endian
)
374 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
375 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
379 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
382 #define SET_DR(n, EXP) set_dr ((n), (EXP))
384 set_dr (int n
, double exp
)
387 if (host_little_endian
)
395 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
396 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
399 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
402 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
403 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
405 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
406 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
408 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
409 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
410 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
412 #define RS saved_state.asregs.cregs.named.rs
413 #define RE saved_state.asregs.cregs.named.re
414 #define MOD (saved_state.asregs.cregs.named.mod)
417 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
418 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
420 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
421 #define DSP_GRD(n) DSP_R ((n) + 8)
422 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
427 #define Y0 DSP_R (10)
428 #define Y1 DSP_R (11)
429 #define M0 DSP_R (12)
430 #define A1G DSP_R (13)
431 #define M1 DSP_R (14)
432 #define A0G DSP_R (15)
433 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
434 #define MOD_ME DSP_GRD (17)
435 #define MOD_DELTA DSP_GRD (18)
437 #define FP_OP(n, OP, m) \
441 if (((n) & 1) || ((m) & 1)) \
442 RAISE_EXCEPTION (SIGILL); \
444 SET_DR (n, (DR (n) OP DR (m))); \
447 SET_FR (n, (FR (n) OP FR (m))); \
450 #define FP_UNARY(n, OP) \
455 RAISE_EXCEPTION (SIGILL); \
457 SET_DR (n, (OP (DR (n)))); \
460 SET_FR (n, (OP (FR (n)))); \
463 #define FP_CMP(n, OP, m) \
467 if (((n) & 1) || ((m) & 1)) \
468 RAISE_EXCEPTION (SIGILL); \
470 SET_SR_T (DR (n) OP DR (m)); \
473 SET_SR_T (FR (n) OP FR (m)); \
479 /* do we need to swap banks */
480 int old_gpr
= SR_MD
&& SR_RB
;
481 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
482 if (old_gpr
!= new_gpr
)
485 for (i
= 0; i
< 8; i
++)
487 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
488 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
489 saved_state
.asregs
.regs
[i
] = tmp
;
492 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
497 wlat_fast (unsigned char *memory
, int x
, int value
, int maskl
)
500 unsigned int *p
= (unsigned int *) (memory
+ x
);
501 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
506 wwat_fast (unsigned char *memory
, int x
, int value
, int maskw
, int endianw
)
509 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
510 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
515 wbat_fast (unsigned char *memory
, int x
, int value
, int maskb
)
517 unsigned char *p
= memory
+ (x
^ endianb
);
518 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
526 rlat_fast (unsigned char *memory
, int x
, int maskl
)
528 unsigned int *p
= (unsigned int *) (memory
+ x
);
529 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
535 rwat_fast (unsigned char *memory
, int x
, int maskw
, int endianw
)
537 unsigned short *p
= (unsigned short *) (memory
+ (x
^ endianw
));
538 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
544 riat_fast (unsigned char *insn_ptr
, int endianw
)
546 unsigned short *p
= (unsigned short *) ((uintptr_t) insn_ptr
^ endianw
);
552 rbat_fast (unsigned char *memory
, int x
, int maskb
)
554 unsigned char *p
= memory
+ (x
^ endianb
);
555 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
560 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
561 #define RLAT(x) (rlat_fast (memory, x, maskl))
562 #define RBAT(x) (rbat_fast (memory, x, maskb))
563 #define RIAT(p) (riat_fast ((p), endianw))
564 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
565 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
566 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
568 #define RUWAT(x) (RWAT (x) & 0xffff)
569 #define RSWAT(x) ((short) (RWAT (x)))
570 #define RSLAT(x) ((long) (RLAT (x)))
571 #define RSBAT(x) (SEXT (RBAT (x)))
573 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
575 do_rdat (unsigned char *memory
, int x
, int n
, int maskl
)
581 f0
= rlat_fast (memory
, x
+ 0, maskl
);
582 f1
= rlat_fast (memory
, x
+ 4, maskl
);
583 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
584 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
588 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
590 do_wdat (unsigned char *memory
, int x
, int n
, int maskl
)
596 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
597 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
598 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
599 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
604 process_wlat_addr (int addr
, int value
)
608 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
613 process_wwat_addr (int addr
, int value
)
617 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
622 process_wbat_addr (int addr
, int value
)
626 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
631 process_rlat_addr (int addr
)
635 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
640 process_rwat_addr (int addr
)
644 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
649 process_rbat_addr (int addr
)
653 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
657 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
658 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
659 #define SEXTW(y) ((int) ((short) y))
661 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
663 #define SEXT32(x) ((int) (x))
665 #define SIGN32(x) (SEXT32 (x) >> 31)
667 /* convert pointer from target to host value. */
668 #define PT2H(x) ((x) + memory)
669 /* convert pointer from host to target value. */
670 #define PH2T(x) ((x) - memory)
672 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
674 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
676 static int in_delay_slot
= 0;
677 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
679 #define CHECK_INSN_PTR(p) \
681 if (saved_state.asregs.exception || PH2T (p) & maskw) \
682 saved_state.asregs.insn_end = 0; \
683 else if (p < loop.end) \
684 saved_state.asregs.insn_end = loop.end; \
686 saved_state.asregs.insn_end = mem_end; \
699 do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
701 #define L(x) thislock = x;
702 #define TL(x) if ((x) == prevlock) stalls++;
703 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++;
707 #if defined(__GO32__)
708 int sim_memory_size
= 19;
710 int sim_memory_size
= 30;
713 static int sim_profile_size
= 17;
719 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
720 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
721 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
722 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
723 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
724 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
726 #define SCI_RDRF 0x40 /* Recieve data register full */
727 #define SCI_TDRE 0x80 /* Transmit data register empty */
730 IOMEM (int addr
, int write
, int value
)
759 return time ((long *) 0);
768 static FILE *profile_file
;
770 static INLINE
unsigned
774 n
= (n
<< 24 | (n
& 0xff00) << 8
775 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
779 static INLINE
unsigned short
780 swap16 (unsigned short n
)
783 n
= n
<< 8 | (n
& 0xff00) >> 8;
792 union { char b
[4]; int n
; } u
;
794 fwrite (u
.b
, 4, 1, profile_file
);
801 union { char b
[4]; int n
; } u
;
803 fwrite (u
.b
, 2, 1, profile_file
);
806 /* Turn a pointer in a register into a pointer into real memory. */
811 return (char *) (x
+ saved_state
.asregs
.memory
);
814 /* STR points to a zero-terminated string in target byte order. Return
815 the number of bytes that need to be converted to host byte order in order
816 to use this string as a zero-terminated string on the host.
817 (Not counting the rounding up needed to operate on entire words.) */
821 unsigned char *memory
= saved_state
.asregs
.memory
;
823 int endian
= endianb
;
828 for (end
= str
; memory
[end
^ endian
]; end
++) ;
829 return end
- str
+ 1;
833 strnswap (int str
, int len
)
837 if (! endianb
|| ! len
)
839 start
= (int *) ptr (str
& ~3);
840 end
= (int *) ptr (str
+ len
);
844 *start
= (old
<< 24 | (old
& 0xff00) << 8
845 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
851 /* Simulate a monitor trap, put the result into r0 and errno into r1
852 return offset by which to adjust pc. */
855 trap (SIM_DESC sd
, int i
, int *regs
, unsigned char *insn_ptr
,
856 unsigned char *memory
, int maskl
, int maskw
, int endianw
)
858 host_callback
*callback
= STATE_CALLBACK (sd
);
859 char **prog_argv
= STATE_PROG_ARGV (sd
);
864 printf ("%c", regs
[0]);
867 raise_exception (SIGQUIT
);
869 case 3: /* FIXME: for backwards compat, should be removed */
872 unsigned int countp
= * (unsigned int *) (insn_ptr
+ 4);
874 WLAT (countp
, RLAT (countp
) + 1);
886 #if !defined(__GO32__) && !defined(_WIN32)
887 case TARGET_SYS_fork
:
890 /* This would work only if endianness matched between host and target.
891 Besides, it's quite dangerous. */
893 case TARGET_SYS_execve
:
894 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]),
895 (char **) ptr (regs
[7]));
897 case TARGET_SYS_execv
:
898 regs
[0] = execve (ptr (regs
[5]), (char **) ptr (regs
[6]), 0);
901 case TARGET_SYS_pipe
:
903 regs
[0] = (BUSERROR (regs
[5], maskl
)
905 : pipe ((int *) ptr (regs
[5])));
909 case TARGET_SYS_wait
:
910 regs
[0] = wait ((int *) ptr (regs
[5]));
912 #endif /* !defined(__GO32__) && !defined(_WIN32) */
914 case TARGET_SYS_read
:
915 strnswap (regs
[6], regs
[7]);
917 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
918 strnswap (regs
[6], regs
[7]);
920 case TARGET_SYS_write
:
921 strnswap (regs
[6], regs
[7]);
923 regs
[0] = (int) callback
->write_stdout (callback
,
924 ptr (regs
[6]), regs
[7]);
926 regs
[0] = (int) callback
->write (callback
, regs
[5],
927 ptr (regs
[6]), regs
[7]);
928 strnswap (regs
[6], regs
[7]);
930 case TARGET_SYS_lseek
:
931 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
933 case TARGET_SYS_close
:
934 regs
[0] = callback
->close (callback
,regs
[5]);
936 case TARGET_SYS_open
:
938 int len
= strswaplen (regs
[5]);
939 strnswap (regs
[5], len
);
940 regs
[0] = callback
->open (callback
, ptr (regs
[5]), regs
[6]);
941 strnswap (regs
[5], len
);
944 case TARGET_SYS_exit
:
945 /* EXIT - caller can look in r5 to work out the reason */
946 raise_exception (SIGQUIT
);
950 case TARGET_SYS_stat
: /* added at hmsi */
951 /* stat system call */
953 struct stat host_stat
;
955 int len
= strswaplen (regs
[5]);
957 strnswap (regs
[5], len
);
958 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
959 strnswap (regs
[5], len
);
963 WWAT (buf
, host_stat
.st_dev
);
965 WWAT (buf
, host_stat
.st_ino
);
967 WLAT (buf
, host_stat
.st_mode
);
969 WWAT (buf
, host_stat
.st_nlink
);
971 WWAT (buf
, host_stat
.st_uid
);
973 WWAT (buf
, host_stat
.st_gid
);
975 WWAT (buf
, host_stat
.st_rdev
);
977 WLAT (buf
, host_stat
.st_size
);
979 WLAT (buf
, host_stat
.st_atime
);
983 WLAT (buf
, host_stat
.st_mtime
);
987 WLAT (buf
, host_stat
.st_ctime
);
999 case TARGET_SYS_chown
:
1001 int len
= strswaplen (regs
[5]);
1003 strnswap (regs
[5], len
);
1004 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1005 strnswap (regs
[5], len
);
1009 case TARGET_SYS_chmod
:
1011 int len
= strswaplen (regs
[5]);
1013 strnswap (regs
[5], len
);
1014 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1015 strnswap (regs
[5], len
);
1018 case TARGET_SYS_utime
:
1020 /* Cast the second argument to void *, to avoid type mismatch
1021 if a prototype is present. */
1022 int len
= strswaplen (regs
[5]);
1024 strnswap (regs
[5], len
);
1025 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1026 strnswap (regs
[5], len
);
1029 case TARGET_SYS_argc
:
1030 regs
[0] = countargv (prog_argv
);
1032 case TARGET_SYS_argnlen
:
1033 if (regs
[5] < countargv (prog_argv
))
1034 regs
[0] = strlen (prog_argv
[regs
[5]]);
1038 case TARGET_SYS_argn
:
1039 if (regs
[5] < countargv (prog_argv
))
1041 /* Include the termination byte. */
1042 int i
= strlen (prog_argv
[regs
[5]]) + 1;
1043 regs
[0] = sim_write (0, regs
[6], (void *) prog_argv
[regs
[5]], i
);
1048 case TARGET_SYS_time
:
1049 regs
[0] = get_now ();
1051 case TARGET_SYS_ftruncate
:
1052 regs
[0] = callback
->ftruncate (callback
, regs
[5], regs
[6]);
1054 case TARGET_SYS_truncate
:
1056 int len
= strswaplen (regs
[5]);
1057 strnswap (regs
[5], len
);
1058 regs
[0] = callback
->truncate (callback
, ptr (regs
[5]), regs
[6]);
1059 strnswap (regs
[5], len
);
1066 regs
[1] = callback
->get_errno (callback
);
1071 case 13: /* Set IBNR */
1072 IBNR
= regs
[0] & 0xffff;
1074 case 14: /* Set IBCR */
1075 IBCR
= regs
[0] & 0xffff;
1079 raise_exception (SIGTRAP
);
1088 div1 (int *R
, int iRn2
, int iRn1
/*, int T*/)
1091 unsigned char old_q
, tmp1
;
1094 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1096 R
[iRn1
] |= (unsigned long) T
;
1106 tmp1
= (R
[iRn1
] > tmp0
);
1113 SET_SR_Q ((unsigned char) (tmp1
== 0));
1120 tmp1
= (R
[iRn1
] < tmp0
);
1124 SET_SR_Q ((unsigned char) (tmp1
== 0));
1139 tmp1
= (R
[iRn1
] < tmp0
);
1146 SET_SR_Q ((unsigned char) (tmp1
== 0));
1153 tmp1
= (R
[iRn1
] > tmp0
);
1157 SET_SR_Q ((unsigned char) (tmp1
== 0));
1173 dmul_s (uint32_t rm
, uint32_t rn
)
1175 int64_t res
= (int64_t)(int32_t)rm
* (int64_t)(int32_t)rn
;
1176 MACH
= (uint32_t)((uint64_t)res
>> 32);
1177 MACL
= (uint32_t)res
;
1181 dmul_u (uint32_t rm
, uint32_t rn
)
1183 uint64_t res
= (uint64_t)(uint32_t)rm
* (uint64_t)(uint32_t)rn
;
1184 MACH
= (uint32_t)(res
>> 32);
1185 MACL
= (uint32_t)res
;
1189 macw (int *regs
, unsigned char *memory
, int n
, int m
, int endianw
)
1192 long prod
, macl
, sum
;
1194 tempm
=RSWAT (regs
[m
]); regs
[m
]+=2;
1195 tempn
=RSWAT (regs
[n
]); regs
[n
]+=2;
1198 prod
= (long) (short) tempm
* (long) (short) tempn
;
1202 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1204 /* MACH's lsb is a sticky overflow bit. */
1206 /* Store the smallest negative number in MACL if prod is
1207 negative, and the largest positive number otherwise. */
1208 sum
= 0x7fffffff + (prod
< 0);
1214 /* Add to MACH the sign extended product, and carry from low sum. */
1215 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1216 /* Sign extend at 10:th bit in MACH. */
1217 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1223 macl (int *regs
, unsigned char *memory
, int n
, int m
)
1230 tempm
= RSLAT (regs
[m
]);
1233 tempn
= RSLAT (regs
[n
]);
1239 mac64
= ((long long) macl
& 0xffffffff) |
1240 ((long long) mach
& 0xffffffff) << 32;
1242 ans
= (long long) tempm
* (long long) tempn
; /* Multiply 32bit * 32bit */
1244 mac64
+= ans
; /* Accumulate 64bit + 64 bit */
1246 macl
= (long) (mac64
& 0xffffffff);
1247 mach
= (long) ((mac64
>> 32) & 0xffffffff);
1249 if (S
) /* Store only 48 bits of the result */
1251 if (mach
< 0) /* Result is negative */
1253 mach
= mach
& 0x0000ffff; /* Mask higher 16 bits */
1254 mach
|= 0xffff8000; /* Sign extend higher 16 bits */
1257 mach
= mach
& 0x00007fff; /* Postive Result */
1288 /* Do extended displacement move instructions. */
1290 do_long_move_insn (int op
, int disp12
, int m
, int n
, int *thatlock
)
1293 int thislock
= *thatlock
;
1294 int endianw
= global_endianw
;
1295 int *R
= &(saved_state
.asregs
.regs
[0]);
1296 unsigned char *memory
= saved_state
.asregs
.memory
;
1297 int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1298 unsigned char *insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1301 case MOVB_RM
: /* signed */
1302 WBAT (disp12
* 1 + R
[n
], R
[m
]);
1305 WWAT (disp12
* 2 + R
[n
], R
[m
]);
1308 WLAT (disp12
* 4 + R
[n
], R
[m
]);
1310 case FMOV_RM
: /* floating point */
1314 WDAT (R
[n
] + 8 * disp12
, m
);
1317 WLAT (R
[n
] + 4 * disp12
, FI (m
));
1320 R
[n
] = RSBAT (disp12
* 1 + R
[m
]);
1324 R
[n
] = RSWAT (disp12
* 2 + R
[m
]);
1328 R
[n
] = RLAT (disp12
* 4 + R
[m
]);
1334 RDAT (R
[m
] + 8 * disp12
, n
);
1337 SET_FI (n
, RLAT (R
[m
] + 4 * disp12
));
1339 case MOVU_BMR
: /* unsigned */
1340 R
[n
] = RBAT (disp12
* 1 + R
[m
]);
1344 R
[n
] = RWAT (disp12
* 2 + R
[m
]);
1348 RAISE_EXCEPTION (SIGINT
);
1351 saved_state
.asregs
.memstalls
+= memstalls
;
1352 *thatlock
= thislock
;
1355 /* Do binary logical bit-manipulation insns. */
1357 do_blog_insn (int imm
, int addr
, int binop
,
1358 unsigned char *memory
, int maskb
)
1360 int oldval
= RBAT (addr
);
1363 case B_BCLR
: /* bclr.b */
1364 WBAT (addr
, oldval
& ~imm
);
1366 case B_BSET
: /* bset.b */
1367 WBAT (addr
, oldval
| imm
);
1369 case B_BST
: /* bst.b */
1371 WBAT (addr
, oldval
| imm
);
1373 WBAT (addr
, oldval
& ~imm
);
1375 case B_BLD
: /* bld.b */
1376 SET_SR_T ((oldval
& imm
) != 0);
1378 case B_BAND
: /* band.b */
1379 SET_SR_T (T
&& ((oldval
& imm
) != 0));
1381 case B_BOR
: /* bor.b */
1382 SET_SR_T (T
|| ((oldval
& imm
) != 0));
1384 case B_BXOR
: /* bxor.b */
1385 SET_SR_T (T
^ ((oldval
& imm
) != 0));
1387 case B_BLDNOT
: /* bldnot.b */
1388 SET_SR_T ((oldval
& imm
) == 0);
1390 case B_BANDNOT
: /* bandnot.b */
1391 SET_SR_T (T
&& ((oldval
& imm
) == 0));
1393 case B_BORNOT
: /* bornot.b */
1394 SET_SR_T (T
|| ((oldval
& imm
) == 0));
1400 fsca_s (int in
, double (*f
) (double))
1402 double rad
= ldexp ((in
& 0xffff), -15) * 3.141592653589793238462643383;
1403 double result
= (*f
) (rad
);
1404 double error
, upper
, lower
, frac
;
1407 /* Search the value with the maximum error that is still within the
1408 architectural spec. */
1409 error
= ldexp (1., -21);
1410 /* compensate for calculation inaccuracy by reducing error. */
1411 error
= error
- ldexp (1., -50);
1412 upper
= result
+ error
;
1413 frac
= frexp (upper
, &exp
);
1414 upper
= ldexp (floor (ldexp (frac
, 24)), exp
- 24);
1415 lower
= result
- error
;
1416 frac
= frexp (lower
, &exp
);
1417 lower
= ldexp (ceil (ldexp (frac
, 24)), exp
- 24);
1418 return abs (upper
- result
) >= abs (lower
- result
) ? upper
: lower
;
1424 double result
= 1. / sqrt (in
);
1426 double frac
, upper
, lower
, error
, eps
;
1429 result
= result
- (result
* result
* in
- 1) * 0.5 * result
;
1430 /* Search the value with the maximum error that is still within the
1431 architectural spec. */
1432 frac
= frexp (result
, &exp
);
1433 frac
= ldexp (frac
, 24);
1434 error
= 4.0; /* 1 << 24-1-21 */
1435 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */
1436 eps
= ldexp (1., -29);
1437 upper
= floor (frac
+ error
- eps
);
1438 if (upper
> 16777216.)
1439 upper
= floor ((frac
+ error
- eps
) * 0.5) * 2.;
1440 lower
= ceil ((frac
- error
+ eps
) * 2) * .5;
1441 if (lower
> 8388608.)
1442 lower
= ceil (frac
- error
+ eps
);
1443 upper
= ldexp (upper
, exp
- 24);
1444 lower
= ldexp (lower
, exp
- 24);
1445 return upper
- result
>= result
- lower
? upper
: lower
;
1449 /* GET_LOOP_BOUNDS {EXTENDED}
1450 These two functions compute the actual starting and ending point
1451 of the repeat loop, based on the RS and RE registers (repeat start,
1452 repeat stop). The extended version is called for LDRC, and the
1453 regular version is called for SETRC. The difference is that for
1454 LDRC, the loop start and end instructions are literally the ones
1455 pointed to by RS and RE -- for SETRC, they're not (see docs). */
1457 static struct loop_bounds
1458 get_loop_bounds_ext (int rs
, int re
, unsigned char *memory
,
1459 unsigned char *mem_end
, int maskw
, int endianw
)
1461 struct loop_bounds loop
;
1463 /* FIXME: should I verify RS < RE? */
1464 loop
.start
= PT2H (RS
); /* FIXME not using the params? */
1465 loop
.end
= PT2H (RE
& ~1); /* Ignore bit 0 of RE. */
1466 SKIP_INSN (loop
.end
);
1467 if (loop
.end
>= mem_end
)
1468 loop
.end
= PT2H (0);
1472 static struct loop_bounds
1473 get_loop_bounds (int rs
, int re
, unsigned char *memory
, unsigned char *mem_end
,
1474 int maskw
, int endianw
)
1476 struct loop_bounds loop
;
1482 loop
.start
= PT2H (RE
- 4);
1483 SKIP_INSN (loop
.start
);
1484 loop
.end
= loop
.start
;
1486 SKIP_INSN (loop
.end
);
1488 SKIP_INSN (loop
.end
);
1489 SKIP_INSN (loop
.end
);
1493 loop
.start
= PT2H (RS
);
1494 loop
.end
= PT2H (RE
- 4);
1495 SKIP_INSN (loop
.end
);
1496 SKIP_INSN (loop
.end
);
1497 SKIP_INSN (loop
.end
);
1498 SKIP_INSN (loop
.end
);
1500 if (loop
.end
>= mem_end
)
1501 loop
.end
= PT2H (0);
1504 loop
.end
= PT2H (0);
1509 static void ppi_insn ();
1513 /* Provide calloc / free versions that use an anonymous mmap. This can
1514 significantly cut the start-up time when a large simulator memory is
1515 required, because pages are only zeroed on demand. */
1516 #ifdef MAP_ANONYMOUS
1518 mcalloc (size_t nmemb
, size_t size
)
1524 return mmap (0, size
, PROT_READ
| PROT_WRITE
, MAP_PRIVATE
| MAP_ANONYMOUS
,
1528 #define mfree(start,length) munmap ((start), (length))
1530 #define mcalloc calloc
1531 #define mfree(start,length) free(start)
1534 /* Set the memory size to the power of two provided. */
1537 sim_size (int power
)
1539 sim_memory_size
= power
;
1541 if (saved_state
.asregs
.memory
)
1543 mfree (saved_state
.asregs
.memory
, saved_state
.asregs
.msize
);
1546 saved_state
.asregs
.msize
= 1 << power
;
1548 saved_state
.asregs
.memory
=
1549 (unsigned char *) mcalloc (1, saved_state
.asregs
.msize
);
1551 if (!saved_state
.asregs
.memory
)
1554 "Not enough VM for simulation of %d bytes of RAM\n",
1555 saved_state
.asregs
.msize
);
1557 saved_state
.asregs
.msize
= 1;
1558 saved_state
.asregs
.memory
= (unsigned char *) mcalloc (1, 1);
1563 init_dsp (struct bfd
*abfd
)
1565 int was_dsp
= target_dsp
;
1566 unsigned long mach
= bfd_get_mach (abfd
);
1568 if (mach
== bfd_mach_sh_dsp
||
1569 mach
== bfd_mach_sh4al_dsp
||
1570 mach
== bfd_mach_sh3_dsp
)
1572 int ram_area_size
, xram_start
, yram_start
;
1576 if (mach
== bfd_mach_sh_dsp
)
1578 /* SH7410 (orig. sh-sdp):
1579 4KB each for X & Y memory;
1580 On-chip X RAM 0x0800f000-0x0800ffff
1581 On-chip Y RAM 0x0801f000-0x0801ffff */
1582 xram_start
= 0x0800f000;
1583 ram_area_size
= 0x1000;
1585 if (mach
== bfd_mach_sh3_dsp
|| mach
== bfd_mach_sh4al_dsp
)
1588 8KB each for X & Y memory;
1589 On-chip X RAM 0x1000e000-0x1000ffff
1590 On-chip Y RAM 0x1001e000-0x1001ffff */
1591 xram_start
= 0x1000e000;
1592 ram_area_size
= 0x2000;
1594 yram_start
= xram_start
+ 0x10000;
1595 new_select
= ~(ram_area_size
- 1);
1596 if (saved_state
.asregs
.xyram_select
!= new_select
)
1598 saved_state
.asregs
.xyram_select
= new_select
;
1599 free (saved_state
.asregs
.xmem
);
1600 free (saved_state
.asregs
.ymem
);
1601 saved_state
.asregs
.xmem
=
1602 (unsigned char *) calloc (1, ram_area_size
);
1603 saved_state
.asregs
.ymem
=
1604 (unsigned char *) calloc (1, ram_area_size
);
1606 /* Disable use of X / Y mmeory if not allocated. */
1607 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1609 saved_state
.asregs
.xyram_select
= 0;
1610 if (saved_state
.asregs
.xmem
)
1611 free (saved_state
.asregs
.xmem
);
1612 if (saved_state
.asregs
.ymem
)
1613 free (saved_state
.asregs
.ymem
);
1616 saved_state
.asregs
.xram_start
= xram_start
;
1617 saved_state
.asregs
.yram_start
= yram_start
;
1618 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1619 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1624 if (saved_state
.asregs
.xyram_select
)
1626 saved_state
.asregs
.xyram_select
= 0;
1627 free (saved_state
.asregs
.xmem
);
1628 free (saved_state
.asregs
.ymem
);
1632 if (! saved_state
.asregs
.xyram_select
)
1634 saved_state
.asregs
.xram_start
= 1;
1635 saved_state
.asregs
.yram_start
= 1;
1638 if (saved_state
.asregs
.regstack
== NULL
)
1639 saved_state
.asregs
.regstack
=
1640 calloc (512, sizeof *saved_state
.asregs
.regstack
);
1642 if (target_dsp
!= was_dsp
)
1646 for (i
= ARRAY_SIZE (sh_dsp_table
) - 1; i
>= 0; i
--)
1648 tmp
= sh_jump_table
[0xf000 + i
];
1649 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1650 sh_dsp_table
[i
] = tmp
;
1656 init_pointers (void)
1658 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1660 sim_size (sim_memory_size
);
1663 if (saved_state
.asregs
.profile
&& !profile_file
)
1665 profile_file
= fopen ("gmon.out", "wb");
1666 /* Seek to where to put the call arc data */
1667 nsamples
= (1 << sim_profile_size
);
1669 fseek (profile_file
, nsamples
* 2 + 12, 0);
1673 fprintf (stderr
, "Can't open gmon.out\n");
1677 saved_state
.asregs
.profile_hist
=
1678 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1691 p
= saved_state
.asregs
.profile_hist
;
1693 maxpc
= (1 << sim_profile_size
);
1695 fseek (profile_file
, 0L, 0);
1696 swapout (minpc
<< PROFILE_SHIFT
);
1697 swapout (maxpc
<< PROFILE_SHIFT
);
1698 swapout (nsamples
* 2 + 12);
1699 for (i
= 0; i
< nsamples
; i
++)
1700 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1705 gotcall (int from
, int to
)
1712 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1715 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
1717 register unsigned char *insn_ptr
;
1718 unsigned char *mem_end
;
1719 struct loop_bounds loop
;
1720 register int cycles
= 0;
1721 register int stalls
= 0;
1722 register int memstalls
= 0;
1723 register int insts
= 0;
1724 register int prevlock
;
1728 register int thislock
;
1730 register unsigned int doprofile
;
1731 register int pollcount
= 0;
1732 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1733 endianb is used less often. */
1734 register int endianw
= global_endianw
;
1736 int tick_start
= get_now ();
1737 void (*prev_fpe
) ();
1739 register unsigned short *jump_table
= sh_jump_table
;
1741 register int *R
= &(saved_state
.asregs
.regs
[0]);
1747 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1748 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1749 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1750 register unsigned char *memory
;
1751 register unsigned int sbit
= ((unsigned int) 1 << 31);
1753 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1756 saved_state
.asregs
.exception
= 0;
1758 memory
= saved_state
.asregs
.memory
;
1759 mem_end
= memory
+ saved_state
.asregs
.msize
;
1762 loop
= get_loop_bounds_ext (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1764 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1766 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1767 CHECK_INSN_PTR (insn_ptr
);
1770 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1772 /*T = GET_SR () & SR_MASK_T;*/
1773 prevlock
= saved_state
.asregs
.prevlock
;
1774 thislock
= saved_state
.asregs
.thislock
;
1775 doprofile
= saved_state
.asregs
.profile
;
1777 /* If profiling not enabled, disable it by asking for
1778 profiles infrequently. */
1783 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1785 if (saved_state
.asregs
.exception
)
1786 /* This can happen if we've already been single-stepping and
1787 encountered a loop end. */
1788 saved_state
.asregs
.insn_end
= insn_ptr
;
1791 saved_state
.asregs
.exception
= SIGTRAP
;
1792 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1796 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1798 register unsigned int iword
= RIAT (insn_ptr
);
1799 register unsigned int ult
;
1800 register unsigned char *nip
= insn_ptr
+ 2;
1813 if (--pollcount
< 0)
1815 host_callback
*callback
= STATE_CALLBACK (sd
);
1817 pollcount
= POLL_QUIT_INTERVAL
;
1818 if ((*callback
->poll_quit
) != NULL
1819 && (*callback
->poll_quit
) (callback
))
1826 prevlock
= thislock
;
1830 if (cycles
>= doprofile
)
1833 saved_state
.asregs
.cycles
+= doprofile
;
1834 cycles
-= doprofile
;
1835 if (saved_state
.asregs
.profile_hist
)
1837 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1840 int i
= saved_state
.asregs
.profile_hist
[n
];
1842 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1849 if (saved_state
.asregs
.insn_end
== loop
.end
)
1851 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1853 insn_ptr
= loop
.start
;
1856 saved_state
.asregs
.insn_end
= mem_end
;
1857 loop
.end
= PT2H (0);
1862 if (saved_state
.asregs
.exception
== SIGILL
1863 || saved_state
.asregs
.exception
== SIGBUS
)
1867 /* Check for SIGBUS due to insn fetch. */
1868 else if (! saved_state
.asregs
.exception
)
1869 saved_state
.asregs
.exception
= SIGBUS
;
1871 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1872 saved_state
.asregs
.cycles
+= cycles
;
1873 saved_state
.asregs
.stalls
+= stalls
;
1874 saved_state
.asregs
.memstalls
+= memstalls
;
1875 saved_state
.asregs
.insts
+= insts
;
1876 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1878 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1881 saved_state
.asregs
.prevlock
= prevlock
;
1882 saved_state
.asregs
.thislock
= thislock
;
1889 signal (SIGFPE
, prev_fpe
);
1893 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1899 for (i
= 0; i
< size
; i
++)
1901 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1907 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1913 for (i
= 0; i
< size
; i
++)
1915 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1920 static int gdb_bank_number
;
1930 sh_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1935 val
= swap (* (int *) memory
);
1938 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
1939 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
1940 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
1941 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
1942 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
1943 case SIM_SH_R15_REGNUM
:
1944 saved_state
.asregs
.regs
[rn
] = val
;
1946 case SIM_SH_PC_REGNUM
:
1947 saved_state
.asregs
.pc
= val
;
1949 case SIM_SH_PR_REGNUM
:
1952 case SIM_SH_GBR_REGNUM
:
1955 case SIM_SH_VBR_REGNUM
:
1958 case SIM_SH_MACH_REGNUM
:
1961 case SIM_SH_MACL_REGNUM
:
1964 case SIM_SH_SR_REGNUM
:
1967 case SIM_SH_FPUL_REGNUM
:
1970 case SIM_SH_FPSCR_REGNUM
:
1973 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
1974 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
1975 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
1976 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
1977 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
1978 case SIM_SH_FR15_REGNUM
:
1979 SET_FI (rn
- SIM_SH_FR0_REGNUM
, val
);
1981 case SIM_SH_DSR_REGNUM
:
1984 case SIM_SH_A0G_REGNUM
:
1987 case SIM_SH_A0_REGNUM
:
1990 case SIM_SH_A1G_REGNUM
:
1993 case SIM_SH_A1_REGNUM
:
1996 case SIM_SH_M0_REGNUM
:
1999 case SIM_SH_M1_REGNUM
:
2002 case SIM_SH_X0_REGNUM
:
2005 case SIM_SH_X1_REGNUM
:
2008 case SIM_SH_Y0_REGNUM
:
2011 case SIM_SH_Y1_REGNUM
:
2014 case SIM_SH_MOD_REGNUM
:
2017 case SIM_SH_RS_REGNUM
:
2020 case SIM_SH_RE_REGNUM
:
2023 case SIM_SH_SSR_REGNUM
:
2026 case SIM_SH_SPC_REGNUM
:
2029 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2030 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2031 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2032 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2033 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2034 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2035 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2037 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2038 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
] = val
;
2042 Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
) = val
;
2044 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
] = val
;
2046 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2047 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2048 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2049 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2050 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2052 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2053 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8] = val
;
2057 saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
] = val
;
2059 Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
) = val
;
2061 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2062 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2063 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2064 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2065 SET_Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
, val
);
2067 case SIM_SH_TBR_REGNUM
:
2070 case SIM_SH_IBNR_REGNUM
:
2073 case SIM_SH_IBCR_REGNUM
:
2076 case SIM_SH_BANK_REGNUM
:
2077 /* This is a pseudo-register maintained just for gdb.
2078 It tells us what register bank gdb would like to read/write. */
2079 gdb_bank_number
= val
;
2081 case SIM_SH_BANK_MACL_REGNUM
:
2082 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
] = val
;
2084 case SIM_SH_BANK_GBR_REGNUM
:
2085 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
] = val
;
2087 case SIM_SH_BANK_PR_REGNUM
:
2088 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
] = val
;
2090 case SIM_SH_BANK_IVN_REGNUM
:
2091 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
] = val
;
2093 case SIM_SH_BANK_MACH_REGNUM
:
2094 saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
] = val
;
2103 sh_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
2110 case SIM_SH_R0_REGNUM
: case SIM_SH_R1_REGNUM
: case SIM_SH_R2_REGNUM
:
2111 case SIM_SH_R3_REGNUM
: case SIM_SH_R4_REGNUM
: case SIM_SH_R5_REGNUM
:
2112 case SIM_SH_R6_REGNUM
: case SIM_SH_R7_REGNUM
: case SIM_SH_R8_REGNUM
:
2113 case SIM_SH_R9_REGNUM
: case SIM_SH_R10_REGNUM
: case SIM_SH_R11_REGNUM
:
2114 case SIM_SH_R12_REGNUM
: case SIM_SH_R13_REGNUM
: case SIM_SH_R14_REGNUM
:
2115 case SIM_SH_R15_REGNUM
:
2116 val
= saved_state
.asregs
.regs
[rn
];
2118 case SIM_SH_PC_REGNUM
:
2119 val
= saved_state
.asregs
.pc
;
2121 case SIM_SH_PR_REGNUM
:
2124 case SIM_SH_GBR_REGNUM
:
2127 case SIM_SH_VBR_REGNUM
:
2130 case SIM_SH_MACH_REGNUM
:
2133 case SIM_SH_MACL_REGNUM
:
2136 case SIM_SH_SR_REGNUM
:
2139 case SIM_SH_FPUL_REGNUM
:
2142 case SIM_SH_FPSCR_REGNUM
:
2145 case SIM_SH_FR0_REGNUM
: case SIM_SH_FR1_REGNUM
: case SIM_SH_FR2_REGNUM
:
2146 case SIM_SH_FR3_REGNUM
: case SIM_SH_FR4_REGNUM
: case SIM_SH_FR5_REGNUM
:
2147 case SIM_SH_FR6_REGNUM
: case SIM_SH_FR7_REGNUM
: case SIM_SH_FR8_REGNUM
:
2148 case SIM_SH_FR9_REGNUM
: case SIM_SH_FR10_REGNUM
: case SIM_SH_FR11_REGNUM
:
2149 case SIM_SH_FR12_REGNUM
: case SIM_SH_FR13_REGNUM
: case SIM_SH_FR14_REGNUM
:
2150 case SIM_SH_FR15_REGNUM
:
2151 val
= FI (rn
- SIM_SH_FR0_REGNUM
);
2153 case SIM_SH_DSR_REGNUM
:
2156 case SIM_SH_A0G_REGNUM
:
2159 case SIM_SH_A0_REGNUM
:
2162 case SIM_SH_A1G_REGNUM
:
2165 case SIM_SH_A1_REGNUM
:
2168 case SIM_SH_M0_REGNUM
:
2171 case SIM_SH_M1_REGNUM
:
2174 case SIM_SH_X0_REGNUM
:
2177 case SIM_SH_X1_REGNUM
:
2180 case SIM_SH_Y0_REGNUM
:
2183 case SIM_SH_Y1_REGNUM
:
2186 case SIM_SH_MOD_REGNUM
:
2189 case SIM_SH_RS_REGNUM
:
2192 case SIM_SH_RE_REGNUM
:
2195 case SIM_SH_SSR_REGNUM
:
2198 case SIM_SH_SPC_REGNUM
:
2201 /* The rn_bank idiosyncracies are not due to hardware differences, but to
2202 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
2203 case SIM_SH_R0_BANK0_REGNUM
: case SIM_SH_R1_BANK0_REGNUM
:
2204 case SIM_SH_R2_BANK0_REGNUM
: case SIM_SH_R3_BANK0_REGNUM
:
2205 case SIM_SH_R4_BANK0_REGNUM
: case SIM_SH_R5_BANK0_REGNUM
:
2206 case SIM_SH_R6_BANK0_REGNUM
: case SIM_SH_R7_BANK0_REGNUM
:
2207 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2209 rn
-= SIM_SH_R0_BANK0_REGNUM
;
2210 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
];
2213 val
= (SR_MD
&& SR_RB
2214 ? Rn_BANK (rn
- SIM_SH_R0_BANK0_REGNUM
)
2215 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK0_REGNUM
]);
2217 case SIM_SH_R0_BANK1_REGNUM
: case SIM_SH_R1_BANK1_REGNUM
:
2218 case SIM_SH_R2_BANK1_REGNUM
: case SIM_SH_R3_BANK1_REGNUM
:
2219 case SIM_SH_R4_BANK1_REGNUM
: case SIM_SH_R5_BANK1_REGNUM
:
2220 case SIM_SH_R6_BANK1_REGNUM
: case SIM_SH_R7_BANK1_REGNUM
:
2221 if (saved_state
.asregs
.bfd_mach
== bfd_mach_sh2a
)
2223 rn
-= SIM_SH_R0_BANK1_REGNUM
;
2224 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[rn
+ 8];
2227 val
= (! SR_MD
|| ! SR_RB
2228 ? Rn_BANK (rn
- SIM_SH_R0_BANK1_REGNUM
)
2229 : saved_state
.asregs
.regs
[rn
- SIM_SH_R0_BANK1_REGNUM
]);
2231 case SIM_SH_R0_BANK_REGNUM
: case SIM_SH_R1_BANK_REGNUM
:
2232 case SIM_SH_R2_BANK_REGNUM
: case SIM_SH_R3_BANK_REGNUM
:
2233 case SIM_SH_R4_BANK_REGNUM
: case SIM_SH_R5_BANK_REGNUM
:
2234 case SIM_SH_R6_BANK_REGNUM
: case SIM_SH_R7_BANK_REGNUM
:
2235 val
= Rn_BANK (rn
- SIM_SH_R0_BANK_REGNUM
);
2237 case SIM_SH_TBR_REGNUM
:
2240 case SIM_SH_IBNR_REGNUM
:
2243 case SIM_SH_IBCR_REGNUM
:
2246 case SIM_SH_BANK_REGNUM
:
2247 /* This is a pseudo-register maintained just for gdb.
2248 It tells us what register bank gdb would like to read/write. */
2249 val
= gdb_bank_number
;
2251 case SIM_SH_BANK_MACL_REGNUM
:
2252 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACL
];
2254 case SIM_SH_BANK_GBR_REGNUM
:
2255 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_GBR
];
2257 case SIM_SH_BANK_PR_REGNUM
:
2258 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_PR
];
2260 case SIM_SH_BANK_IVN_REGNUM
:
2261 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_IVN
];
2263 case SIM_SH_BANK_MACH_REGNUM
:
2264 val
= saved_state
.asregs
.regstack
[gdb_bank_number
].regs
[REGBANK_MACH
];
2269 * (int *) memory
= swap (val
);
2274 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
2276 /* The SH simulator uses SIGQUIT to indicate that the program has
2277 exited, so we must check for it here and translate it to exit. */
2278 if (saved_state
.asregs
.exception
== SIGQUIT
)
2280 *reason
= sim_exited
;
2281 *sigrc
= saved_state
.asregs
.regs
[5];
2285 *reason
= sim_stopped
;
2286 *sigrc
= saved_state
.asregs
.exception
;
2291 sim_info (SIM_DESC sd
, int verbose
)
2294 (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
2295 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
2297 sim_io_printf (sd
, "\n\n# instructions executed %10d\n",
2298 saved_state
.asregs
.insts
);
2299 sim_io_printf (sd
, "# cycles %10d\n",
2300 saved_state
.asregs
.cycles
);
2301 sim_io_printf (sd
, "# pipeline stalls %10d\n",
2302 saved_state
.asregs
.stalls
);
2303 sim_io_printf (sd
, "# misaligned load/store %10d\n",
2304 saved_state
.asregs
.memstalls
);
2305 sim_io_printf (sd
, "# real time taken %10.4f\n", timetaken
);
2306 sim_io_printf (sd
, "# virtual time taken %10.4f\n", virttime
);
2307 sim_io_printf (sd
, "# profiling size %10d\n", sim_profile_size
);
2308 sim_io_printf (sd
, "# profiling frequency %10d\n",
2309 saved_state
.asregs
.profile
);
2310 sim_io_printf (sd
, "# profile maxpc %10x\n",
2311 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2315 sim_io_printf (sd
, "# cycles/second %10d\n",
2316 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2317 sim_io_printf (sd
, "# simulation ratio %10.4f\n",
2318 virttime
/ timetaken
);
2323 sh_pc_get (sim_cpu
*cpu
)
2325 return saved_state
.asregs
.pc
;
2329 sh_pc_set (sim_cpu
*cpu
, sim_cia pc
)
2331 saved_state
.asregs
.pc
= pc
;
2335 free_state (SIM_DESC sd
)
2337 if (STATE_MODULES (sd
) != NULL
)
2338 sim_module_uninstall (sd
);
2339 sim_cpu_free_all (sd
);
2340 sim_state_free (sd
);
2344 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
2345 struct bfd
*abfd
, char * const *argv
)
2357 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
2358 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
2360 /* The cpu data is kept in a separately allocated chunk of memory. */
2361 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
2367 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
2373 /* The parser will print an error message for us, so we silently return. */
2374 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
2380 /* Check for/establish the a reference program image. */
2381 if (sim_analyze_program (sd
,
2382 (STATE_PROG_ARGV (sd
) != NULL
2383 ? *STATE_PROG_ARGV (sd
)
2384 : NULL
), abfd
) != SIM_RC_OK
)
2390 /* Configure/verify the target byte order and other runtime
2391 configuration options. */
2392 if (sim_config (sd
) != SIM_RC_OK
)
2394 sim_module_uninstall (sd
);
2398 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
2400 /* Uninstall the modules to avoid memory leaks,
2401 file descriptor leaks, etc. */
2402 sim_module_uninstall (sd
);
2406 /* CPU specific initialization. */
2407 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
2409 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
2411 CPU_REG_FETCH (cpu
) = sh_reg_fetch
;
2412 CPU_REG_STORE (cpu
) = sh_reg_store
;
2413 CPU_PC_FETCH (cpu
) = sh_pc_get
;
2414 CPU_PC_STORE (cpu
) = sh_pc_set
;
2417 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2420 parse_and_set_memory_size (sd
, *p
);
2426 for (i
= 4; (i
-= 2) >= 0; )
2427 mem_word
.s
[i
>> 1] = i
;
2428 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2430 for (i
= 4; --i
>= 0; )
2432 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2438 parse_and_set_memory_size (SIM_DESC sd
, const char *str
)
2442 n
= strtol (str
, NULL
, 10);
2443 if (n
> 0 && n
<= 31)
2444 sim_memory_size
= n
;
2446 sim_io_printf (sd
, "Bad memory size %d; must be 1 to 31, inclusive\n", n
);
2450 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
2451 char * const *argv
, char * const *env
)
2453 /* Clear the registers. */
2454 memset (&saved_state
, 0,
2455 (char*) &saved_state
.asregs
.end_of_registers
- (char*) &saved_state
);
2458 if (prog_bfd
!= NULL
)
2459 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2461 /* Set the bfd machine type. */
2462 if (prog_bfd
!= NULL
)
2463 saved_state
.asregs
.bfd_mach
= bfd_get_mach (prog_bfd
);
2465 if (prog_bfd
!= NULL
)
2466 init_dsp (prog_bfd
);
2472 sim_do_command (SIM_DESC sd
, const char *cmd
)
2474 const char *sms_cmd
= "set-memory-size";
2477 if (cmd
== NULL
|| *cmd
== '\0')
2482 cmdsize
= strlen (sms_cmd
);
2483 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0
2484 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2486 parse_and_set_memory_size (sd
, cmd
+ cmdsize
+ 1);
2488 else if (strcmp (cmd
, "help") == 0)
2490 sim_io_printf (sd
, "List of SH simulator commands:\n\n");
2491 sim_io_printf (sd
, "set-memory-size <n> -- Set the number of address bits to use\n");
2492 sim_io_printf (sd
, "\n");
2496 sim_io_printf (sd
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);