1 # Hitachi H8 testcase 'sub.b'
3 # as(h8300): --defsym sim_cpu=0
4 # as(h8300h): --defsym sim_cpu=1
5 # as(h8300s): --defsym sim_cpu=2
6 # as(h8sx): --defsym sim_cpu=3
7 # ld(h8300h): -m h8300helf
8 # ld(h8300s): -m h8300self
9 # ld(h8sx): -m h8300sxelf
11 .include "testutils.inc"
13 # Instructions tested:
14 # sub.b #xx:8, rd ; <illegal>
15 # sub.b #xx:8, @erd ; 7 d rd ???? a ???? xxxxxxxx
16 # sub.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
17 # sub.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
18 # sub.b rs, rd ; 1 8 rs rd
19 # sub.b reg8, @erd ; 7 d rd ???? 1 8 rs ????
20 # sub.b reg8, @erd+ ; 0 1 7 9 8 rd 3 rs
21 # sub.b reg8, @erd- ; 0 1 7 9 a rd 3 rs
25 # sub.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
26 # sub.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
27 # sub.b reg8, @+erd ; 0 1 7 9 9 rd 3 rs
28 # sub.b reg8, @-erd ; 0 1 7 9 b rd 3 rs
38 .if (0) ; Guess what? Sub.b immediate reg8 is illegal!
40 set_grs_a5a5 ; Fill all general regs with a fixed pattern
44 sub.b #5, r0l ; Immediate 8-bit operand
46 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
47 test_h_gr16 0xa5a0 r0 ; sub result: a5 - 5
48 .if (sim_cpu) ; non-zero means h8300h, s, or sx
49 test_h_gr32 0xa5a5a5a0 er0 ; sub result: a5 - 5
51 test_gr_a5a5 1 ; Make sure other general regs not disturbed
62 set_grs_a5a5 ; Fill all general regs with a fixed pattern
67 sub.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
71 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
76 test_h_gr32 byte_dest, er0 ; er0 still contains address
77 test_gr_a5a5 1 ; Make sure other general regs not disturbed
85 ;; Now check the result of the sub to memory.
94 set_grs_a5a5 ; Fill all general regs with a fixed pattern
99 sub.b #5:8, @er0+ ; Immediate 8-bit src, reg post-incr dest
104 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
109 test_h_gr32 post_byte, er0 ; er0 still contains address plus one
110 test_gr_a5a5 1 ; Make sure other general regs not disturbed
118 ;; Now check the result of the sub to memory.
120 mov.b @byte_dest, r0l
126 sub_b_imm8_rdpostdec:
127 set_grs_a5a5 ; Fill all general regs with a fixed pattern
132 sub.b #5:8, @er0- ; Immediate 8-bit src, reg post-decr dest
137 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
142 test_h_gr32 pre_byte, er0 ; er0 still contains address minus one
143 test_gr_a5a5 1 ; Make sure other general regs not disturbed
151 ;; Now check the result of the sub to memory.
153 mov.b @byte_dest, r0l
162 set_grs_a5a5 ; Fill all general regs with a fixed pattern
167 sub.b r0h, r0l ; Register operand
169 ;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
170 test_h_gr16 0x05a0 r0 ; sub result: a5 - 5
171 .if (sim_cpu) ; non-zero means h8300h, s, or sx
172 test_h_gr32 0xa5a505a0 er0 ; sub result: a5 - 5
174 test_gr_a5a5 1 ; Make sure other general regs not disturbed
182 .if (sim_cpu == h8sx)
184 set_grs_a5a5 ; Fill all general regs with a fixed pattern
187 ;; sub.b rs8,@eRd ; Subx to register indirect
190 sub.b r1l, @er0 ; reg8 src, reg indirect dest
194 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
199 test_h_gr32 byte_dest er0 ; er0 still contains address
200 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
202 test_gr_a5a5 2 ; Make sure other general regs not disturbed
209 ;; Now check the result of the sub to memory.
211 mov.b @byte_dest, r0l
217 sub_b_reg8_rdpostinc:
218 set_grs_a5a5 ; Fill all general regs with a fixed pattern
221 ;; sub.b rs8,@eRd+ ; Subx to register indirect
224 sub.b r1l, @er0+ ; reg8 src, reg indirect dest
228 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
233 test_h_gr32 post_byte er0 ; er0 still contains address plus one
234 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
236 test_gr_a5a5 2 ; Make sure other general regs not disturbed
243 ;; Now check the result of the sub to memory.
245 mov.b @byte_dest, r0l
250 ;; special case same register
251 mov.l #byte_dest, er0
258 mov.b @byte_dest, r0l
263 mov.b r2l, @byte_dest
265 sub_b_reg8_rdpostdec:
266 set_grs_a5a5 ; Fill all general regs with a fixed pattern
269 ;; sub.b rs8,@eRd- ; Subx to register indirect
272 sub.b r1l, @er0- ; reg8 src, reg indirect dest
276 test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
281 test_h_gr32 pre_byte er0 ; er0 still contains address minus one
282 test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
284 test_gr_a5a5 2 ; Make sure other general regs not disturbed
291 ;; Now check the result of the sub to memory.
293 mov.b @byte_dest, r0l
298 ;; special case same register
299 mov.l #byte_dest, er0
305 mov.b @byte_dest, r0l