sim/testsuite/or1k/spr-defs.h

   1 /* Special Purpose Registers definitions
   2
   3    Copyright (C) 2017-2023 Free Software Foundation, Inc.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  17
  18 #ifndef SPR_DEFS_H
  19 #define SPR_DEFS_H
  20
  21 #define MAX_GRPS 32
  22 #define MAX_SPRS_PER_GRP_BITS 11
  23
  24 /* Base addresses for the groups */
  25 #define SPRGROUP_SYS   (0<< MAX_SPRS_PER_GRP_BITS)
  26 #define SPRGROUP_DMMU  (1<< MAX_SPRS_PER_GRP_BITS)
  27 #define SPRGROUP_IMMU  (2<< MAX_SPRS_PER_GRP_BITS)
  28 #define SPRGROUP_DC    (3<< MAX_SPRS_PER_GRP_BITS)
  29 #define SPRGROUP_IC    (4<< MAX_SPRS_PER_GRP_BITS)
  30 #define SPRGROUP_MAC   (5<< MAX_SPRS_PER_GRP_BITS)
  31 #define SPRGROUP_D     (6<< MAX_SPRS_PER_GRP_BITS)
  32 #define SPRGROUP_PC    (7<< MAX_SPRS_PER_GRP_BITS)
  33 #define SPRGROUP_PM    (8<< MAX_SPRS_PER_GRP_BITS)
  34 #define SPRGROUP_PIC   (9<< MAX_SPRS_PER_GRP_BITS)
  35 #define SPRGROUP_TT    (10<< MAX_SPRS_PER_GRP_BITS)
  36 #define SPRGROUP_FP    (11<< MAX_SPRS_PER_GRP_BITS)
  37
  38 /* System control and status group */
  39 #define SPR_VR          (SPRGROUP_SYS + 0)
  40 #define SPR_UPR         (SPRGROUP_SYS + 1)
  41 #define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
  42 #define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
  43 #define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
  44 #define SPR_DCCFGR      (SPRGROUP_SYS + 5)
  45 #define SPR_ICCFGR      (SPRGROUP_SYS + 6)
  46 #define SPR_DCFGR       (SPRGROUP_SYS + 7)
  47 #define SPR_PCCFGR      (SPRGROUP_SYS + 8)
  48 #define SPR_NPC         (SPRGROUP_SYS + 16)
  49 #define SPR_SR          (SPRGROUP_SYS + 17)
  50 #define SPR_PPC         (SPRGROUP_SYS + 18)
  51 #define SPR_FPCSR       (SPRGROUP_SYS + 20)
  52 #define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)
  53 #define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)
  54 #define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
  55 #define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
  56 #define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
  57 #define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
  58 #define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
  59
  60 /* Data MMU group */
  61 #define SPR_DMMUCR  (SPRGROUP_DMMU + 0)
  62 #define SPR_DMMUPR  (SPRGROUP_DMMU + 1)
  63 #define SPR_DTLBEIR     (SPRGROUP_DMMU + 2)
  64 #define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
  65 #define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
  66 #define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
  67 #define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
  68
  69 /* Instruction MMU group */
  70 #define SPR_IMMUCR  (SPRGROUP_IMMU + 0)
  71 #define SPR_ITLBEIR     (SPRGROUP_IMMU + 2)
  72 #define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
  73 #define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
  74 #define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
  75 #define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
  76
  77 /* Data cache group */
  78 #define SPR_DCCR    (SPRGROUP_DC + 0)
  79 #define SPR_DCBPR   (SPRGROUP_DC + 1)
  80 #define SPR_DCBFR   (SPRGROUP_DC + 2)
  81 #define SPR_DCBIR   (SPRGROUP_DC + 3)
  82 #define SPR_DCBWR   (SPRGROUP_DC + 4)
  83 #define SPR_DCBLR   (SPRGROUP_DC + 5)
  84 #define SPR_DCR_BASE(WAY)   (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
  85 #define SPR_DCR_LAST(WAY)   (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
  86
  87 /* Instruction cache group */
  88 #define SPR_ICCR    (SPRGROUP_IC + 0)
  89 #define SPR_ICBPR   (SPRGROUP_IC + 1)
  90 #define SPR_ICBIR   (SPRGROUP_IC + 2)
  91 #define SPR_ICBLR   (SPRGROUP_IC + 3)
  92 #define SPR_ICR_BASE(WAY)   (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
  93 #define SPR_ICR_LAST(WAY)   (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
  94
  95 /* MAC group */
  96 #define SPR_MACLO   (SPRGROUP_MAC + 1)
  97 #define SPR_MACHI   (SPRGROUP_MAC + 2)
  98
  99 /* Bit definitions for the Supervision Register.  */
 100 #define SPR_SR_SM          0x00000001 /* Supervisor Mode */
 101 #define SPR_SR_TEE         0x00000002 /* Tick timer Exception Enable */
 102 #define SPR_SR_IEE         0x00000004 /* Interrupt Exception Enable */
 103 #define SPR_SR_DCE         0x00000008 /* Data Cache Enable */
 104 #define SPR_SR_ICE         0x00000010 /* Instruction Cache Enable */
 105 #define SPR_SR_DME         0x00000020 /* Data MMU Enable */
 106 #define SPR_SR_IME         0x00000040 /* Instruction MMU Enable */
 107 #define SPR_SR_LEE         0x00000080 /* Little Endian Enable */
 108 #define SPR_SR_CE          0x00000100 /* CID Enable */
 109 #define SPR_SR_F           0x00000200 /* Condition Flag */
 110 #define SPR_SR_CY          0x00000400 /* Carry flag */
 111 #define SPR_SR_OV          0x00000800 /* Overflow flag */
 112 #define SPR_SR_OVE         0x00001000 /* Overflow flag Exception */
 113 #define SPR_SR_DSX         0x00002000 /* Delay Slot Exception */
 114 #define SPR_SR_EPH         0x00004000 /* Exception Prefix High */
 115 #define SPR_SR_FO          0x00008000 /* Fixed one */
 116 #define SPR_SR_SUMRA       0x00010000 /* Supervisor SPR read access */
 117 #define SPR_SR_RES         0x0ffe0000 /* Reserved */
 118 #define SPR_SR_CID         0xf0000000 /* Context ID */
 119
 120 #endif /* SPR_DEFS_H */