sim/testsuite/sim/arm/iwmmxt/wsad.cgs

   1 # Intel(r) Wireless MMX(tm) technology testcase for WSAD
   2 # mach: xscale
   3 # as: -mcpu=xscale+iwmmxt
   4
   5         .include "testutils.inc"
   6
   7         start
   8
   9         .global wsad
  10 wsad:
  11         # Enable access to CoProcessors 0 & 1 before
  12         # we attempt these instructions.
  13
  14         mvi_h_gr   r1, 3
  15         mcr        p15, 0, r1, cr15, cr1, 0
  16
  17         # Test Byte wide absolute accumulation
  18
  19         mvi_h_gr   r0, 0x12345678
  20         mvi_h_gr   r1, 0x9abcdef0
  21         mvi_h_gr   r2, 0x11111111
  22         mvi_h_gr   r3, 0x22222222
  23         mvi_h_gr   r4, 0x22222222
  24         mvi_h_gr   r5, 0x22222222
  25
  26         tmcrr      wr0, r0, r1
  27         tmcrr      wr1, r2, r3
  28         tmcrr      wr2, r4, r5
  29
  30         wsadb      wr2, wr0, wr1
  31
  32         tmrrc      r0, r1, wr0
  33         tmrrc      r2, r3, wr1
  34         tmrrc      r4, r5, wr2
  35
  36         test_h_gr  r0, 0x12345678
  37         test_h_gr  r1, 0x9abcdef0
  38         test_h_gr  r2, 0x11111111
  39         test_h_gr  r3, 0x22222222
  40         test_h_gr  r4, 0x2222258e
  41         test_h_gr  r5, 0x00000000
  42
  43         # Test Byte wide absolute accumulation with zeroing
  44
  45         mvi_h_gr   r0, 0x12345678
  46         mvi_h_gr   r1, 0x9abcdef0
  47         mvi_h_gr   r2, 0x11111111
  48         mvi_h_gr   r3, 0x22222222
  49         mvi_h_gr   r4, 0x22222222
  50         mvi_h_gr   r5, 0x22222222
  51
  52         tmcrr      wr0, r0, r1
  53         tmcrr      wr1, r2, r3
  54         tmcrr      wr2, r4, r5
  55
  56         wsadbz     wr2, wr0, wr1
  57
  58         tmrrc      r0, r1, wr0
  59         tmrrc      r2, r3, wr1
  60         tmrrc      r4, r5, wr2
  61
  62         test_h_gr  r0, 0x12345678
  63         test_h_gr  r1, 0x9abcdef0
  64         test_h_gr  r2, 0x11111111
  65         test_h_gr  r3, 0x22222222
  66         test_h_gr  r4, 0x0000036c
  67         test_h_gr  r5, 0x00000000
  68
  69         # Test Halfword wide absolute accumulation
  70
  71         mvi_h_gr   r0, 0x12345678
  72         mvi_h_gr   r1, 0x9abcdef0
  73         mvi_h_gr   r2, 0x11111111
  74         mvi_h_gr   r3, 0x22222222
  75         mvi_h_gr   r4, 0x22222222
  76         mvi_h_gr   r5, 0x22222222
  77
  78         tmcrr      wr0, r0, r1
  79         tmcrr      wr1, r2, r3
  80         tmcrr      wr2, r4, r5
  81
  82         wsadh      wr2, wr0, wr1
  83
  84         tmrrc      r0, r1, wr0
  85         tmrrc      r2, r3, wr1
  86         tmrrc      r4, r5, wr2
  87
  88         test_h_gr  r0, 0x12345678
  89         test_h_gr  r1, 0x9abcdef0
  90         test_h_gr  r2, 0x11111111
  91         test_h_gr  r3, 0x22222222
  92         test_h_gr  r4, 0x22239e14
  93         test_h_gr  r5, 0x00000000
  94
  95         # Test Halfword wide absolute accumulation with zeroing
  96
  97         mvi_h_gr   r0, 0x12345678
  98         mvi_h_gr   r1, 0x9abcdef0
  99         mvi_h_gr   r2, 0x11111111
 100         mvi_h_gr   r3, 0x22222222
 101         mvi_h_gr   r4, 0x22222222
 102         mvi_h_gr   r5, 0x22222222
 103
 104         tmcrr      wr0, r0, r1
 105         tmcrr      wr1, r2, r3
 106         tmcrr      wr2, r4, r5
 107
 108         wsadhz     wr2, wr0, wr1
 109
 110         tmrrc      r0, r1, wr0
 111         tmrrc      r2, r3, wr1
 112         tmrrc      r4, r5, wr2
 113
 114         test_h_gr  r0, 0x12345678
 115         test_h_gr  r1, 0x9abcdef0
 116         test_h_gr  r2, 0x11111111
 117         test_h_gr  r3, 0x22222222
 118         test_h_gr  r4, 0x00017bf2
 119         test_h_gr  r5, 0x00000000
 120
 121         pass