sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s

   1 //Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8 // Spec Reference: dsp32shiftimm ashift: ashift saturated
   9
  10
  11 imm32 r0, 0x81230001;
  12 imm32 r1, 0x19345678;
  13 imm32 r2, 0x23c56789;
  14 imm32 r3, 0x3ed6789a;
  15 imm32 r4, 0x85d789ab;
  16 imm32 r5, 0x967f9abc;
  17 imm32 r6, 0xa789bbcd;
  18 imm32 r7, 0xb891acde;
  19 R0 = R0 << 0 (S);
  20 R1 = R1 << 3 (S);
  21 R2 = R2 << 7 (S);
  22 R3 = R3 << 8 (S);
  23 R4 = R4 << 15 (S);
  24 R5 = R5 << 24 (S);
  25 R6 = R6 << 31 (S);
  26 R7 = R7 << 20 (S);
  27 CHECKREG r0, 0x81230001;
  28 CHECKREG r1, 0x7FFFFFFF;
  29 CHECKREG r2, 0x7FFFFFFF;
  30 CHECKREG r3, 0x7FFFFFFF;
  31 CHECKREG r4, 0x80000000;
  32 CHECKREG r5, 0x80000000;
  33 CHECKREG r6, 0x80000000;
  34 CHECKREG r7, 0x80000000;
  35
  36 imm32 r0, 0xa1230001;
  37 imm32 r1, 0x1e345678;
  38 imm32 r2, 0x23f56789;
  39 imm32 r3, 0x34db789a;
  40 imm32 r4, 0x85a7a9ab;
  41 imm32 r5, 0x967c9abc;
  42 imm32 r6, 0xa78dabcd;
  43 imm32 r7, 0xb8914cde;
  44 R6 = R0 >>> 1;
  45 R7 = R1 >>> 3;
  46 R0 = R2 >>> 7;
  47 R1 = R3 >>> 8;
  48 R2 = R4 >>> 15;
  49 R3 = R5 >>> 24;
  50 R4 = R6 >>> 31;
  51 R5 = R7 >>> 20;
  52 CHECKREG r0, 0x0047EACF;
  53 CHECKREG r1, 0x0034DB78;
  54 CHECKREG r2, 0xFFFF0B4F;
  55 CHECKREG r3, 0xFFFFFF96;
  56 CHECKREG r4, 0xFFFFFFFF;
  57 CHECKREG r5, 0x0000003C;
  58 CHECKREG r6, 0xD0918000;
  59 CHECKREG r7, 0x03C68ACF;
  60
  61
  62
  63 pass