sim/testsuite/sim/fr30/mulu.cgs

   1 # fr30 testcase for mulu $Rj,$Ri
   2 # mach(): fr30
   3
   4         .include "testutils.inc"
   5
   6         START
   7
   8         .text
   9         .global mulu
  10 mulu:
  11         ; Test mulu $Rj,$Ri
  12         ; Positive operands
  13         mvi_h_gr        3,r7            ; multiply small numbers
  14         mvi_h_gr        2,r8
  15         set_cc          0x0f            ; Set mask opposite of expected
  16         mulu            r7,r8
  17         test_cc         0 0 0 1
  18         test_h_dr       0,mdh
  19         test_h_dr       6,mdl
  20
  21         mvi_h_gr        1,r7            ; multiply by 1
  22         mvi_h_gr        2,r8
  23         set_cc          0x0e            ; Set mask opposite of expected
  24         mulu            r7,r8
  25         test_cc         0 0 0 0
  26         test_h_dr       0,mdh
  27         test_h_dr       2,mdl
  28
  29         mvi_h_gr        2,r7            ; multiply by 1
  30         mvi_h_gr        1,r8
  31         set_cc          0x0f            ; Set mask opposite of expected
  32         mulu            r7,r8
  33         test_cc         0 0 0 1
  34         test_h_dr       0,mdh
  35         test_h_dr       2,mdl
  36
  37         mvi_h_gr        0,r7            ; multiply by 0
  38         mvi_h_gr        2,r8
  39         set_cc          0x0b            ; Set mask opposite of expected
  40         mulu            r7,r8
  41         test_cc         0 1 0 1
  42         test_h_dr       0,mdh
  43         test_h_dr       0,mdl
  44
  45         mvi_h_gr        2,r7            ; multiply by 0
  46         mvi_h_gr        0,r8
  47         set_cc          0x0a            ; Set mask opposite of expected
  48         mulu            r7,r8
  49         test_cc         0 1 0 0
  50         test_h_dr       0,mdh
  51         test_h_dr       0,mdl
  52
  53         mvi_h_gr        0x3fffffff,r7   ; 31 bit result
  54         mvi_h_gr        2,r8
  55         set_cc          0x0f            ; Set mask opposite of expected
  56         mulu            r7,r8
  57         test_cc         0 0 0 1
  58         test_h_dr       0,mdh
  59         test_h_dr       0x7ffffffe,mdl
  60
  61         mvi_h_gr        0x40000000,r7   ; 32 bit result
  62         mvi_h_gr        2,r8
  63         set_cc          0x0e            ; Set mask opposite of expected
  64         mulu            r7,r8
  65         test_cc         0 0 0 0
  66         test_h_dr       0,mdh
  67         test_h_dr       0x80000000,mdl
  68
  69         mvi_h_gr        0x80000000,r7   ; 33 bit result
  70         mvi_h_gr        2,r8
  71         set_cc          0x09            ; Set mask opposite of expected
  72         mulu            r7,r8
  73         test_cc         0 1 1 1
  74         test_h_dr       1,mdh
  75         test_h_dr       0x00000000,mdl
  76
  77         mvi_h_gr        0x7fffffff,r7   ; max positive result
  78         mvi_h_gr        0x7fffffff,r8
  79         set_cc          0x0d            ; Set mask opposite of expected
  80         mulu            r7,r8
  81         test_cc         0 0 1 1
  82         test_h_dr       0x3fffffff,mdh
  83         test_h_dr       0x00000001,mdl
  84
  85         mvi_h_gr        0x80000000,r7   ; max positive result
  86         mvi_h_gr        0x80000000,r8
  87         set_cc          0x09            ; Set mask opposite of expected
  88         mulu            r7,r8
  89         test_cc         0 1 1 1
  90         test_h_dr       0x40000000,mdh
  91         test_h_dr       0x00000000,mdl
  92
  93         mvi_h_gr        0xffffffff,r7   ; max positive result
  94         mvi_h_gr        0xffffffff,r8
  95         set_cc          0x05            ; Set mask opposite of expected
  96         mulu            r7,r8
  97         test_cc         1 0 1 1
  98         test_h_dr       0xfffffffe,mdh
  99         test_h_dr       0x00000001,mdl
 100
 101         pass