sim/testsuite/sim/frv/fr500/cmqaddhus.cgs

   1 # frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
   2 # mach: frv fr500
   3
   4         .include "../testutils.inc"
   5
   6         start
   7
   8         .global cmqaddhus
   9 cmqaddhus:
  10         set_spr_immed   0x1b1b,cccr
  11
  12         set_fr_iimmed   0x0000,0x0000,fr10
  13         set_fr_iimmed   0xdead,0x0000,fr11
  14         set_fr_iimmed   0x0000,0x0000,fr12
  15         set_fr_iimmed   0x0000,0xbeef,fr13
  16         cmqaddhus       fr10,fr12,fr14,cc0,1
  17         test_fr_limmed  0x0000,0x0000,fr14
  18         test_fr_limmed  0xdead,0xbeef,fr15
  19         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  20         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  21         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  22         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  23
  24         set_fr_iimmed   0x0000,0xdead,fr10
  25         set_fr_iimmed   0x1234,0x5678,fr11
  26         set_fr_iimmed   0xbeef,0x0000,fr12
  27         set_fr_iimmed   0x1111,0x1111,fr13
  28         cmqaddhus       fr10,fr12,fr14,cc0,1
  29         test_fr_limmed  0xbeef,0xdead,fr14
  30         test_fr_limmed  0x2345,0x6789,fr15
  31         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  32         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  33         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  34         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  35
  36         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  37         set_fr_iimmed   0xfffe,0xfffe,fr11
  38         set_fr_iimmed   0x0002,0x0001,fr12
  39         set_fr_iimmed   0x0001,0x0002,fr13
  40         cmqaddhus       fr10,fr12,fr14,cc4,1
  41         test_fr_limmed  0x8000,0x7fff,fr14
  42         test_fr_limmed  0xffff,0xffff,fr15
  43         test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
  44         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
  45         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  46         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  47
  48         set_spr_immed   0,msr0
  49         set_spr_immed   0,msr1
  50         set_fr_iimmed   0x0002,0x0001,fr10
  51         set_fr_iimmed   0x0001,0x0001,fr11
  52         set_fr_iimmed   0xfffe,0xfffe,fr12
  53         set_fr_iimmed   0x8000,0x8000,fr13
  54         cmqaddhus.p     fr10,fr10,fr14,cc4,1
  55         cmqaddhus       fr12,fr12,fr16,cc4,1
  56         test_fr_limmed  0x0004,0x0002,fr14
  57         test_fr_limmed  0x0002,0x0002,fr15
  58         test_fr_limmed  0xffff,0xffff,fr16
  59         test_fr_limmed  0xffff,0xffff,fr17
  60         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  61         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  62         test_spr_bits   0x3c,2,0xf,msr1         ; msr1.sie is set
  63         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
  64         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
  65         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
  66
  67         set_spr_immed   0,msr0
  68         set_spr_immed   0,msr1
  69         set_fr_iimmed   0x0000,0x0000,fr10
  70         set_fr_iimmed   0xdead,0x0000,fr11
  71         set_fr_iimmed   0x0000,0x0000,fr12
  72         set_fr_iimmed   0x0000,0xbeef,fr13
  73         cmqaddhus       fr10,fr12,fr14,cc1,0
  74         test_fr_limmed  0x0000,0x0000,fr14
  75         test_fr_limmed  0xdead,0xbeef,fr15
  76         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  77         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  78         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  79         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  80
  81         set_fr_iimmed   0x0000,0xdead,fr10
  82         set_fr_iimmed   0x1234,0x5678,fr11
  83         set_fr_iimmed   0xbeef,0x0000,fr12
  84         set_fr_iimmed   0x1111,0x1111,fr13
  85         cmqaddhus       fr10,fr12,fr14,cc1,0
  86         test_fr_limmed  0xbeef,0xdead,fr14
  87         test_fr_limmed  0x2345,0x6789,fr15
  88         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
  89         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
  90         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
  91         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
  92
  93         set_fr_iimmed   0x7ffe,0x7ffe,fr10
  94         set_fr_iimmed   0xfffe,0xfffe,fr11
  95         set_fr_iimmed   0x0002,0x0001,fr12
  96         set_fr_iimmed   0x0001,0x0002,fr13
  97         cmqaddhus       fr10,fr12,fr14,cc5,0
  98         test_fr_limmed  0x8000,0x7fff,fr14
  99         test_fr_limmed  0xffff,0xffff,fr15
 100         test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
 101         test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
 102         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 103         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 104
 105         set_spr_immed   0,msr0
 106         set_spr_immed   0,msr1
 107         set_fr_iimmed   0x0002,0x0001,fr10
 108         set_fr_iimmed   0x0001,0x0001,fr11
 109         set_fr_iimmed   0xfffe,0xfffe,fr12
 110         set_fr_iimmed   0x8000,0x8000,fr13
 111         cmqaddhus.p     fr10,fr10,fr14,cc5,0
 112         cmqaddhus       fr12,fr12,fr16,cc5,0
 113         test_fr_limmed  0x0004,0x0002,fr14
 114         test_fr_limmed  0x0002,0x0002,fr15
 115         test_fr_limmed  0xffff,0xffff,fr16
 116         test_fr_limmed  0xffff,0xffff,fr17
 117         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 118         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 119         test_spr_bits   0x3c,2,0xf,msr1         ; msr1.sie is set
 120         test_spr_bits   2,1,1,msr1              ; msr1.ovf set
 121         test_spr_bits   1,0,1,msr0              ; msr0.aovf set
 122         test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
 123
 124         set_fr_iimmed   0x1111,0x1111,fr14
 125         set_fr_iimmed   0x2222,0x2222,fr15
 126         set_spr_immed   0,msr0
 127         set_spr_immed   0,msr1
 128         set_fr_iimmed   0x0000,0x0000,fr10
 129         set_fr_iimmed   0xdead,0x0000,fr11
 130         set_fr_iimmed   0x0000,0x0000,fr12
 131         set_fr_iimmed   0x0000,0xbeef,fr13
 132         cmqaddhus       fr10,fr12,fr14,cc0,0
 133         test_fr_limmed  0x1111,0x1111,fr14
 134         test_fr_limmed  0x2222,0x2222,fr15
 135         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 136         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 137         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 138         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 139
 140         set_fr_iimmed   0x0000,0xdead,fr10
 141         set_fr_iimmed   0x1234,0x5678,fr11
 142         set_fr_iimmed   0xbeef,0x0000,fr12
 143         set_fr_iimmed   0x1111,0x1111,fr13
 144         cmqaddhus       fr10,fr12,fr14,cc0,0
 145         test_fr_limmed  0x1111,0x1111,fr14
 146         test_fr_limmed  0x2222,0x2222,fr15
 147         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 148         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 149         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 150         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 151
 152         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 153         set_fr_iimmed   0xfffe,0xfffe,fr11
 154         set_fr_iimmed   0x0002,0x0001,fr12
 155         set_fr_iimmed   0x0001,0x0002,fr13
 156         cmqaddhus       fr10,fr12,fr14,cc4,0
 157         test_fr_limmed  0x1111,0x1111,fr14
 158         test_fr_limmed  0x2222,0x2222,fr15
 159         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 160         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 161         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 162         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 163
 164         set_fr_iimmed   0x3333,0x3333,fr16
 165         set_fr_iimmed   0x4444,0x4444,fr17
 166         set_spr_immed   0,msr0
 167         set_spr_immed   0,msr1
 168         set_fr_iimmed   0x0002,0x0001,fr10
 169         set_fr_iimmed   0x0001,0x0001,fr11
 170         set_fr_iimmed   0xfffe,0xfffe,fr12
 171         set_fr_iimmed   0x8000,0x8000,fr13
 172         cmqaddhus.p     fr10,fr10,fr14,cc4,0
 173         cmqaddhus       fr12,fr12,fr16,cc4,0
 174         test_fr_limmed  0x1111,0x1111,fr14
 175         test_fr_limmed  0x2222,0x2222,fr15
 176         test_fr_limmed  0x3333,0x3333,fr16
 177         test_fr_limmed  0x4444,0x4444,fr17
 178         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 179         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 180         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 181         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 182
 183         set_fr_iimmed   0x1111,0x1111,fr14
 184         set_fr_iimmed   0x2222,0x2222,fr15
 185         set_spr_immed   0,msr0
 186         set_spr_immed   0,msr1
 187         set_fr_iimmed   0x0000,0x0000,fr10
 188         set_fr_iimmed   0xdead,0x0000,fr11
 189         set_fr_iimmed   0x0000,0x0000,fr12
 190         set_fr_iimmed   0x0000,0xbeef,fr13
 191         cmqaddhus       fr10,fr12,fr14,cc1,1
 192         test_fr_limmed  0x1111,0x1111,fr14
 193         test_fr_limmed  0x2222,0x2222,fr15
 194         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 195         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 196         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 197         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 198
 199         set_fr_iimmed   0x0000,0xdead,fr10
 200         set_fr_iimmed   0x1234,0x5678,fr11
 201         set_fr_iimmed   0xbeef,0x0000,fr12
 202         set_fr_iimmed   0x1111,0x1111,fr13
 203         cmqaddhus       fr10,fr12,fr14,cc1,1
 204         test_fr_limmed  0x1111,0x1111,fr14
 205         test_fr_limmed  0x2222,0x2222,fr15
 206         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 207         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 208         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 209         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 210
 211         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 212         set_fr_iimmed   0xfffe,0xfffe,fr11
 213         set_fr_iimmed   0x0002,0x0001,fr12
 214         set_fr_iimmed   0x0001,0x0002,fr13
 215         cmqaddhus       fr10,fr12,fr14,cc5,1
 216         test_fr_limmed  0x1111,0x1111,fr14
 217         test_fr_limmed  0x2222,0x2222,fr15
 218         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 219         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 220         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 221         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 222
 223         set_fr_iimmed   0x3333,0x3333,fr16
 224         set_fr_iimmed   0x4444,0x4444,fr17
 225         set_spr_immed   0,msr0
 226         set_spr_immed   0,msr1
 227         set_fr_iimmed   0x0002,0x0001,fr10
 228         set_fr_iimmed   0x0001,0x0001,fr11
 229         set_fr_iimmed   0xfffe,0xfffe,fr12
 230         set_fr_iimmed   0x8000,0x8000,fr13
 231         cmqaddhus.p     fr10,fr10,fr14,cc5,1
 232         cmqaddhus       fr12,fr12,fr16,cc5,1
 233         test_fr_limmed  0x1111,0x1111,fr14
 234         test_fr_limmed  0x2222,0x2222,fr15
 235         test_fr_limmed  0x3333,0x3333,fr16
 236         test_fr_limmed  0x4444,0x4444,fr17
 237         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 238         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 239         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 240         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 241
 242         set_fr_iimmed   0x1111,0x1111,fr14
 243         set_fr_iimmed   0x2222,0x2222,fr15
 244         set_spr_immed   0,msr0
 245         set_spr_immed   0,msr1
 246         set_fr_iimmed   0x0000,0x0000,fr10
 247         set_fr_iimmed   0xdead,0x0000,fr11
 248         set_fr_iimmed   0x0000,0x0000,fr12
 249         set_fr_iimmed   0x0000,0xbeef,fr13
 250         cmqaddhus       fr10,fr12,fr14,cc2,1
 251         test_fr_limmed  0x1111,0x1111,fr14
 252         test_fr_limmed  0x2222,0x2222,fr15
 253         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 254         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 255         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 256         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 257
 258         set_fr_iimmed   0x0000,0xdead,fr10
 259         set_fr_iimmed   0x1234,0x5678,fr11
 260         set_fr_iimmed   0xbeef,0x0000,fr12
 261         set_fr_iimmed   0x1111,0x1111,fr13
 262         cmqaddhus       fr10,fr12,fr14,cc2,0
 263         test_fr_limmed  0x1111,0x1111,fr14
 264         test_fr_limmed  0x2222,0x2222,fr15
 265         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 266         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 267         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 268         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 269
 270         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 271         set_fr_iimmed   0xfffe,0xfffe,fr11
 272         set_fr_iimmed   0x0002,0x0001,fr12
 273         set_fr_iimmed   0x0001,0x0002,fr13
 274         cmqaddhus       fr10,fr12,fr14,cc6,1
 275         test_fr_limmed  0x1111,0x1111,fr14
 276         test_fr_limmed  0x2222,0x2222,fr15
 277         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 278         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 279         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 280         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 281
 282         set_fr_iimmed   0x3333,0x3333,fr16
 283         set_fr_iimmed   0x4444,0x4444,fr17
 284         set_spr_immed   0,msr0
 285         set_spr_immed   0,msr1
 286         set_fr_iimmed   0x0002,0x0001,fr10
 287         set_fr_iimmed   0x0001,0x0001,fr11
 288         set_fr_iimmed   0xfffe,0xfffe,fr12
 289         set_fr_iimmed   0x8000,0x8000,fr13
 290         cmqaddhus.p     fr10,fr10,fr14,cc6,0
 291         cmqaddhus       fr12,fr12,fr16,cc6,1
 292         test_fr_limmed  0x1111,0x1111,fr14
 293         test_fr_limmed  0x2222,0x2222,fr15
 294         test_fr_limmed  0x3333,0x3333,fr16
 295         test_fr_limmed  0x4444,0x4444,fr17
 296         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 297         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 298         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 299         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 300
 301         set_fr_iimmed   0x1111,0x1111,fr14
 302         set_fr_iimmed   0x2222,0x2222,fr15
 303         set_spr_immed   0,msr0
 304         set_spr_immed   0,msr1
 305         set_fr_iimmed   0x0000,0x0000,fr10
 306         set_fr_iimmed   0xdead,0x0000,fr11
 307         set_fr_iimmed   0x0000,0x0000,fr12
 308         set_fr_iimmed   0x0000,0xbeef,fr13
 309         cmqaddhus       fr10,fr12,fr14,cc3,1
 310         test_fr_limmed  0x1111,0x1111,fr14
 311         test_fr_limmed  0x2222,0x2222,fr15
 312         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 313         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 314         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 315         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 316
 317         set_fr_iimmed   0x0000,0xdead,fr10
 318         set_fr_iimmed   0x1234,0x5678,fr11
 319         set_fr_iimmed   0xbeef,0x0000,fr12
 320         set_fr_iimmed   0x1111,0x1111,fr13
 321         cmqaddhus       fr10,fr12,fr14,cc3,0
 322         test_fr_limmed  0x1111,0x1111,fr14
 323         test_fr_limmed  0x2222,0x2222,fr15
 324         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 325         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 326         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 327         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 328
 329         set_fr_iimmed   0x7ffe,0x7ffe,fr10
 330         set_fr_iimmed   0xfffe,0xfffe,fr11
 331         set_fr_iimmed   0x0002,0x0001,fr12
 332         set_fr_iimmed   0x0001,0x0002,fr13
 333         cmqaddhus       fr10,fr12,fr14,cc7,1
 334         test_fr_limmed  0x1111,0x1111,fr14
 335         test_fr_limmed  0x2222,0x2222,fr15
 336         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 337         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 338         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 339         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 340
 341         set_fr_iimmed   0x3333,0x3333,fr16
 342         set_fr_iimmed   0x4444,0x4444,fr17
 343         set_spr_immed   0,msr0
 344         set_spr_immed   0,msr1
 345         set_fr_iimmed   0x0002,0x0001,fr10
 346         set_fr_iimmed   0x0001,0x0001,fr11
 347         set_fr_iimmed   0xfffe,0xfffe,fr12
 348         set_fr_iimmed   0x8000,0x8000,fr13
 349         cmqaddhus.p     fr10,fr10,fr14,cc7,0
 350         cmqaddhus       fr12,fr12,fr16,cc7,1
 351         test_fr_limmed  0x1111,0x1111,fr14
 352         test_fr_limmed  0x2222,0x2222,fr15
 353         test_fr_limmed  0x3333,0x3333,fr16
 354         test_fr_limmed  0x4444,0x4444,fr17
 355         test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
 356         test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
 357         test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
 358         test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
 359
 360         pass