sim/testsuite/sim/h8300/brabc.s

   1 # Hitachi H8 testcase 'bra/bc'
   2 # mach(): h8sx
   3 # as(h8300):    --defsym sim_cpu=0
   4 # as(h8300h):   --defsym sim_cpu=1
   5 # as(h8300s):   --defsym sim_cpu=2
   6 # as(h8sx):     --defsym sim_cpu=3
   7 # ld(h8300h):   -m h8300helf
   8 # ld(h8300s):   -m h8300self
   9 # ld(h8sx):     -m h8300sxelf
  10
  11         .include "testutils.inc"
  12
  13         .data
  14 byte_src:       .byte   0xa5
  15
  16         start
  17
  18 .if (sim_cpu == h8sx)
  19 brabc_ind_disp8:
  20         set_grs_a5a5
  21         mov     #byte_src, er1
  22         set_ccr_zero
  23         ;; bra/bc xx:3, @erd, disp8
  24         bra/bc  #1, @er1, .Lpass1:8
  25 ;;;     .word   0x7c10
  26 ;;;     .word   0x4110
  27         fail
  28 .Lpass1:
  29         bra/bc  #2, @er1, .Lfail1:8
  30 ;;;     .word   0x7c10
  31 ;;;     .word   0x4202
  32         bra     .Lpass2
  33 .Lfail1:
  34         fail
  35 .Lpass2:
  36         test_cc_clear
  37         test_h_gr32 0xa5a5a5a5 er0
  38         test_h_gr32 byte_src   er1
  39         test_h_gr32 0xa5a5a5a5 er2
  40         test_h_gr32 0xa5a5a5a5 er3
  41         test_h_gr32 0xa5a5a5a5 er4
  42         test_h_gr32 0xa5a5a5a5 er5
  43         test_h_gr32 0xa5a5a5a5 er6
  44         test_h_gr32 0xa5a5a5a5 er7
  45
  46 brabc_abs8_disp16:
  47         set_grs_a5a5
  48         mov.b   #0xa5, @0x20:32
  49         set_ccr_zero
  50         ;; bra/bc xx:3, @aa:8, disp16
  51         bra/bc  #1, @0x20:8, .Lpass3:16
  52         fail
  53 .Lpass3:
  54         bra/bc  #2, @0x20:8, Lfail:16
  55
  56         test_cc_clear
  57         test_grs_a5a5
  58
  59 brabc_abs16_disp16:
  60         set_grs_a5a5
  61         set_ccr_zero
  62         ;; bra/bc xx:3, @aa:16, disp16
  63         bra/bc  #1, @byte_src:16, .Lpass5:16
  64         fail
  65 .Lpass5:
  66         bra/bc  #2, @byte_src:16, Lfail:16
  67
  68         test_cc_clear
  69         test_grs_a5a5
  70
  71 brabs_ind_disp8:
  72         set_grs_a5a5
  73         mov     #byte_src, er1
  74         set_ccr_zero
  75         ;; bra/bs xx:3, @erd, disp8
  76         bra/bs  #2, @er1, .Lpass7:8
  77 ;;;     .word   0x7c10
  78 ;;;     .word   0x4a10
  79         fail
  80 .Lpass7:
  81         bra/bs  #1, @er1, .Lfail3:8
  82 ;;;     .word   0x7c10
  83 ;;;     .word   0x4902
  84         bra     .Lpass8
  85 .Lfail3:
  86         fail
  87 .Lpass8:
  88         test_cc_clear
  89         test_h_gr32 0xa5a5a5a5 er0
  90         test_h_gr32 byte_src   er1
  91         test_h_gr32 0xa5a5a5a5 er2
  92         test_h_gr32 0xa5a5a5a5 er3
  93         test_h_gr32 0xa5a5a5a5 er4
  94         test_h_gr32 0xa5a5a5a5 er5
  95         test_h_gr32 0xa5a5a5a5 er6
  96         test_h_gr32 0xa5a5a5a5 er7
  97
  98 brabs_abs32_disp16:
  99         set_grs_a5a5
 100         set_ccr_zero
 101         ;; bra/bs xx:3, @aa:32, disp16
 102         bra/bs  #2, @byte_src:32, .Lpass9:16
 103         fail
 104 .Lpass9:
 105         bra/bs  #1, @byte_src:32, Lfail:16
 106
 107         test_cc_clear
 108         test_grs_a5a5
 109
 110 .endif
 111
 112         pass
 113
 114         exit 0
 115
 116 Lfail:  fail