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git.ipfire.org Git - thirdparty/binutils-gdb.git/blob - sim/v850/interp.c
2 #include "sim-options.h"
4 #include "sim-assert.h"
21 static const char * get_insn_name (sim_cpu
*, int);
23 /* For compatibility. */
26 /* V850 interrupt model. */
41 const char *interrupt_names
[] =
55 do_interrupt (SIM_DESC sd
, void *data
)
57 const char **interrupt_name
= (const char**)data
;
58 enum interrupt_type inttype
;
59 inttype
= (interrupt_name
- STATE_WATCHPOINTS (sd
)->interrupt_names
);
61 /* For a hardware reset, drop everything and jump to the start
63 if (inttype
== int_reset
)
68 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
71 /* Deliver an NMI when allowed */
72 if (inttype
== int_nmi
)
76 /* We're already working on an NMI, so this one must wait
77 around until the previous one is done. The processor
78 ignores subsequent NMIs, so we don't need to count them.
79 Just keep re-scheduling a single NMI until it manages to
81 if (STATE_CPU (sd
, 0)->pending_nmi
!= NULL
)
82 sim_events_deschedule (sd
, STATE_CPU (sd
, 0)->pending_nmi
);
83 STATE_CPU (sd
, 0)->pending_nmi
=
84 sim_events_schedule (sd
, 1, do_interrupt
, data
);
89 /* NMI can be delivered. Do not deschedule pending_nmi as
90 that, if still in the event queue, is a second NMI that
91 needs to be delivered later. */
94 /* Set the FECC part of the ECR. */
101 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
105 /* deliver maskable interrupt when allowed */
106 if (inttype
> int_nmi
&& inttype
< num_int_types
)
108 if ((PSW
& PSW_NP
) || (PSW
& PSW_ID
))
110 /* Can't deliver this interrupt, reschedule it for later */
111 sim_events_schedule (sd
, 1, do_interrupt
, data
);
119 /* Disable further interrupts. */
121 /* Indicate that we're doing interrupt not exception processing. */
123 /* Clear the EICC part of the ECR, will set below. */
152 /* Should never be possible. */
153 sim_engine_abort (sd
, NULL
, NULL_CIA
,
154 "do_interrupt - internal error - bad switch");
158 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
161 /* some other interrupt? */
162 sim_engine_abort (sd
, NULL
, NULL_CIA
,
163 "do_interrupt - internal error - interrupt %d unknown",
167 /* Return name of an insn, used by insn profiling. */
170 get_insn_name (sim_cpu
*cpu
, int i
)
172 return itable
[i
].name
;
175 /* These default values correspond to expected usage for the chip. */
180 v850_pc_get (sim_cpu
*cpu
)
186 v850_pc_set (sim_cpu
*cpu
, sim_cia pc
)
191 static int v850_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
192 static int v850_reg_store (SIM_CPU
*, int, unsigned char *, int);
195 sim_open (SIM_OPEN_KIND kind
,
201 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
204 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
206 /* The cpu data is kept in a separately allocated chunk of memory. */
207 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
210 /* for compatibility */
213 /* FIXME: should be better way of setting up interrupts */
214 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
215 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
216 STATE_WATCHPOINTS (sd
)->interrupt_handler
= do_interrupt
;
217 STATE_WATCHPOINTS (sd
)->interrupt_names
= interrupt_names
;
219 /* Initialize the mechanism for doing insn profiling. */
220 CPU_INSN_NAME (STATE_CPU (sd
, 0)) = get_insn_name
;
221 CPU_MAX_INSNS (STATE_CPU (sd
, 0)) = nr_itable_entries
;
223 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
226 /* Allocate core managed memory */
228 /* "Mirror" the ROM addresses below 1MB. */
229 sim_do_commandf (sd
, "memory region 0,0x100000,0x%lx", V850_ROM_SIZE
);
230 /* Chunk of ram adjacent to rom */
231 sim_do_commandf (sd
, "memory region 0x100000,0x%lx", V850_LOW_END
-0x100000);
232 /* peripheral I/O region - mirror 1K across 4k (0x1000) */
233 sim_do_command (sd
, "memory region 0xfff000,0x1000,1024");
234 /* similarly if in the internal RAM region */
235 sim_do_command (sd
, "memory region 0xffe000,0x1000,1024");
237 /* getopt will print the error message so we just have to exit if this fails.
238 FIXME: Hmmm... in the case of gdb we need getopt to call
240 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
242 /* Uninstall the modules to avoid memory leaks,
243 file descriptor leaks, etc. */
244 sim_module_uninstall (sd
);
248 /* check for/establish the a reference program image */
249 if (sim_analyze_program (sd
,
250 (STATE_PROG_ARGV (sd
) != NULL
251 ? *STATE_PROG_ARGV (sd
)
255 sim_module_uninstall (sd
);
259 /* establish any remaining configuration options */
260 if (sim_config (sd
) != SIM_RC_OK
)
262 sim_module_uninstall (sd
);
266 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
268 /* Uninstall the modules to avoid memory leaks,
269 file descriptor leaks, etc. */
270 sim_module_uninstall (sd
);
275 /* determine the machine type */
276 if (STATE_ARCHITECTURE (sd
) != NULL
277 && (STATE_ARCHITECTURE (sd
)->arch
== bfd_arch_v850
278 || STATE_ARCHITECTURE (sd
)->arch
== bfd_arch_v850_rh850
))
279 mach
= STATE_ARCHITECTURE (sd
)->mach
;
281 mach
= bfd_mach_v850
; /* default */
283 /* set machine specific configuration */
288 case bfd_mach_v850e1
:
289 case bfd_mach_v850e2
:
290 case bfd_mach_v850e2v3
:
291 case bfd_mach_v850e3v5
:
292 STATE_CPU (sd
, 0)->psw_mask
= (PSW_NP
| PSW_EP
| PSW_ID
| PSW_SAT
293 | PSW_CY
| PSW_OV
| PSW_S
| PSW_Z
);
297 /* CPU specific initialization. */
298 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
300 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
302 CPU_REG_FETCH (cpu
) = v850_reg_fetch
;
303 CPU_REG_STORE (cpu
) = v850_reg_store
;
304 CPU_PC_FETCH (cpu
) = v850_pc_get
;
305 CPU_PC_STORE (cpu
) = v850_pc_set
;
312 sim_create_inferior (SIM_DESC sd
,
313 struct bfd
* prog_bfd
,
317 memset (&State
, 0, sizeof (State
));
318 if (prog_bfd
!= NULL
)
319 PC
= bfd_get_start_address (prog_bfd
);
324 v850_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
326 *(unsigned32
*)memory
= H2T_4 (State
.regs
[rn
]);
331 v850_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
333 State
.regs
[rn
] = T2H_4 (*(unsigned32
*) memory
);