1 /* This must come before any other includes. */
5 #include "sim-signal.h"
21 #include "libiberty.h"
24 #if !defined(__GO32__) && !defined(_WIN32)
26 #include <sys/times.h>
30 #include "target-newlib-syscall.h"
32 /* This is an array of the bit positions of registers r20 .. r31 in
33 that order in a prepare/dispose instruction. */
34 int type1_regs
[12] = { 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 0, 21 };
35 /* This is an array of the bit positions of registers r16 .. r31 in
36 that order in a push/pop instruction. */
37 int type2_regs
[16] = { 3, 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
38 /* This is an array of the bit positions of registers r1 .. r15 in
39 that order in a push/pop instruction. */
40 int type3_regs
[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
43 #ifndef SIZE_INSTRUCTION
44 #define SIZE_INSTRUCTION 18
48 #define SIZE_VALUES 11
52 uint32_t trace_values
[3];
55 const char * trace_name
;
60 trace_input (char *name
, enum op_types type
, int size
)
62 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
67 trace_module
= TRACE_ALU_IDX
;
80 trace_values
[0] = State
.regs
[OP
[0]];
87 trace_values
[0] = State
.regs
[OP
[1]];
88 trace_values
[1] = State
.regs
[OP
[0]];
94 trace_values
[0] = SEXT5 (OP
[0]);
95 trace_values
[1] = OP
[1];
100 trace_values
[0] = SEXT5 (OP
[0]);
101 trace_num_values
= 1;
105 trace_values
[0] = State
.pc
;
106 trace_values
[1] = SEXT9 (OP
[0]);
107 trace_values
[2] = PSW
;
108 trace_num_values
= 3;
112 trace_values
[0] = OP
[1] * size
;
113 trace_values
[1] = State
.regs
[30];
114 trace_num_values
= 2;
118 trace_values
[0] = State
.regs
[OP
[0]];
119 trace_values
[1] = OP
[1] * size
;
120 trace_values
[2] = State
.regs
[30];
121 trace_num_values
= 3;
125 trace_values
[0] = EXTEND16 (OP
[2]);
126 trace_values
[1] = State
.regs
[OP
[0]];
127 trace_num_values
= 2;
131 trace_values
[0] = State
.regs
[OP
[1]];
132 trace_values
[1] = EXTEND16 (OP
[2]);
133 trace_values
[2] = State
.regs
[OP
[0]];
134 trace_num_values
= 3;
138 trace_values
[0] = SEXT22 (OP
[0]);
139 trace_values
[1] = State
.pc
;
140 trace_num_values
= 2;
144 trace_values
[0] = EXTEND16 (OP
[0]) << size
;
145 trace_values
[1] = State
.regs
[OP
[1]];
146 trace_num_values
= 2;
149 case OP_IMM16_REG_REG
:
150 trace_values
[0] = EXTEND16 (OP
[2]) << size
;
151 trace_values
[1] = State
.regs
[OP
[1]];
152 trace_num_values
= 2;
155 case OP_UIMM_REG_REG
:
156 trace_values
[0] = (OP
[0] & 0xffff) << size
;
157 trace_values
[1] = State
.regs
[OP
[1]];
158 trace_num_values
= 2;
161 case OP_UIMM16_REG_REG
:
162 trace_values
[0] = (OP
[2]) << size
;
163 trace_values
[1] = State
.regs
[OP
[1]];
164 trace_num_values
= 2;
168 trace_num_values
= 0;
172 trace_values
[0] = PSW
;
173 trace_num_values
= 1;
177 trace_num_values
= 0;
181 trace_values
[0] = State
.regs
[OP
[0]];
182 trace_num_values
= 1;
186 trace_values
[0] = State
.sregs
[OP
[1]];
187 trace_num_values
= 1;
193 trace_result (int has_result
, uint32_t result
)
201 /* write out the values saved during the trace_input call */
204 for (i
= 0; i
< trace_num_values
; i
++)
206 sprintf (chp
, "%*s0x%.8lx", SIZE_VALUES
- 10, "",
207 (long) trace_values
[i
]);
208 chp
= strchr (chp
, '\0');
212 sprintf (chp
, "%*s", SIZE_VALUES
, "");
213 chp
= strchr (chp
, '\0');
217 /* append any result to the end of the buffer */
219 sprintf (chp
, " :: 0x%.8lx", (unsigned long) result
);
221 trace_generic (simulator
, STATE_CPU (simulator
, 0), trace_module
, "%s", buf
);
225 trace_output (enum op_types result
)
227 if (!TRACE_ALU_P (STATE_CPU (simulator
, 0)))
249 trace_result (1, State
.regs
[OP
[0]]);
253 case OP_REG_REG_MOVE
:
255 case OP_IMM_REG_MOVE
:
258 trace_result (1, State
.regs
[OP
[1]]);
262 case OP_UIMM_REG_REG
:
263 case OP_IMM16_REG_REG
:
264 case OP_UIMM16_REG_REG
:
265 trace_result (1, State
.regs
[OP
[1]]);
270 trace_result (1, State
.regs
[OP
[1]]);
276 trace_result (1, State
.sregs
[OP
[1]]);
283 /* Returns 1 if the specific condition is met, returns 0 otherwise. */
285 condition_met (unsigned code
)
287 unsigned int psw
= PSW
;
291 case 0x0: return ((psw
& PSW_OV
) != 0);
292 case 0x1: return ((psw
& PSW_CY
) != 0);
293 case 0x2: return ((psw
& PSW_Z
) != 0);
294 case 0x3: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) != 0);
295 case 0x4: return ((psw
& PSW_S
) != 0);
296 /*case 0x5: return 1;*/
297 case 0x6: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) != 0);
298 case 0x7: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) != 0);
299 case 0x8: return ((psw
& PSW_OV
) == 0);
300 case 0x9: return ((psw
& PSW_CY
) == 0);
301 case 0xa: return ((psw
& PSW_Z
) == 0);
302 case 0xb: return ((((psw
& PSW_CY
) != 0) | ((psw
& PSW_Z
) != 0)) == 0);
303 case 0xc: return ((psw
& PSW_S
) == 0);
304 case 0xd: return ((psw
& PSW_SAT
) != 0);
305 case 0xe: return ((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) == 0);
306 case 0xf: return (((((psw
& PSW_S
) != 0) ^ ((psw
& PSW_OV
) != 0)) || ((psw
& PSW_Z
) != 0)) == 0);
313 Add32 (unsigned long a1
, unsigned long a2
, int * carry
)
315 unsigned long result
= (a1
+ a2
);
317 * carry
= (result
< a1
);
323 Multiply64 (int sign
, unsigned long op0
)
334 op1
= State
.regs
[ OP
[1] ];
338 /* Compute sign of result and adjust operands if necessary. */
340 sign
= (op0
^ op1
) & 0x80000000;
342 if (op0
& 0x80000000)
345 if (op1
& 0x80000000)
349 /* We can split the 32x32 into four 16x16 operations. This ensures
350 that we do not lose precision on 32bit only hosts: */
351 lo
= ( (op0
& 0xFFFF) * (op1
& 0xFFFF));
352 mid1
= ( (op0
& 0xFFFF) * ((op1
>> 16) & 0xFFFF));
353 mid2
= (((op0
>> 16) & 0xFFFF) * (op1
& 0xFFFF));
354 hi
= (((op0
>> 16) & 0xFFFF) * ((op1
>> 16) & 0xFFFF));
356 /* We now need to add all of these results together, taking care
357 to propogate the carries from the additions: */
358 RdLo
= Add32 (lo
, (mid1
<< 16), & carry
);
360 RdLo
= Add32 (RdLo
, (mid2
<< 16), & carry
);
361 RdHi
+= (carry
+ ((mid1
>> 16) & 0xFFFF) + ((mid2
>> 16) & 0xFFFF) + hi
);
365 /* Negate result if necessary. */
369 if (RdLo
== 0xFFFFFFFF)
378 /* Don't store into register 0. */
380 State
.regs
[ OP
[1] ] = RdLo
;
382 State
.regs
[ OP
[2] >> 11 ] = RdHi
;
388 /* Read a null terminated string from memory, return in a buffer. */
391 fetch_str (SIM_DESC sd
, address_word addr
)
396 while (sim_core_read_1 (STATE_CPU (sd
, 0),
397 PC
, read_map
, addr
+ nr
) != 0)
400 buf
= NZALLOC (char, nr
+ 1);
401 sim_read (simulator
, addr
, buf
, nr
);
406 /* Read a null terminated argument vector from memory, return in a
410 fetch_argv (SIM_DESC sd
, address_word addr
)
414 char **buf
= xmalloc (max_nr
* sizeof (char*));
418 uint32_t a
= sim_core_read_4 (STATE_CPU (sd
, 0),
419 PC
, read_map
, addr
+ nr
* 4);
421 buf
[nr
] = fetch_str (sd
, a
);
423 if (nr
== max_nr
- 1)
426 buf
= xrealloc (buf
, max_nr
* sizeof (char*));
438 trace_input ("sst.b", OP_STORE16
, 1);
440 store_mem (State
.regs
[30] + (OP
[3] & 0x7f), 1, State
.regs
[ OP
[1] ]);
442 trace_output (OP_STORE16
);
451 trace_input ("sst.h", OP_STORE16
, 2);
453 store_mem (State
.regs
[30] + ((OP
[3] & 0x7f) << 1), 2, State
.regs
[ OP
[1] ]);
455 trace_output (OP_STORE16
);
464 trace_input ("sst.w", OP_STORE16
, 4);
466 store_mem (State
.regs
[30] + ((OP
[3] & 0x7e) << 1), 4, State
.regs
[ OP
[1] ]);
468 trace_output (OP_STORE16
);
479 trace_input ("ld.b", OP_LOAD32
, 1);
481 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
483 State
.regs
[ OP
[1] ] = EXTEND8 (load_mem (adr
, 1));
485 trace_output (OP_LOAD32
);
496 trace_input ("ld.h", OP_LOAD32
, 2);
498 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
501 State
.regs
[ OP
[1] ] = EXTEND16 (load_mem (adr
, 2));
503 trace_output (OP_LOAD32
);
514 trace_input ("ld.w", OP_LOAD32
, 4);
516 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
519 State
.regs
[ OP
[1] ] = load_mem (adr
, 4);
521 trace_output (OP_LOAD32
);
530 trace_input ("st.b", OP_STORE32
, 1);
532 store_mem (State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]), 1, State
.regs
[ OP
[1] ]);
534 trace_output (OP_STORE32
);
545 trace_input ("st.h", OP_STORE32
, 2);
547 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2]);
550 store_mem (adr
, 2, State
.regs
[ OP
[1] ]);
552 trace_output (OP_STORE32
);
563 trace_input ("st.w", OP_STORE32
, 4);
565 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
568 store_mem (adr
, 4, State
.regs
[ OP
[1] ]);
570 trace_output (OP_STORE32
);
579 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
581 trace_input ("add", OP_REG_REG
, 0);
583 /* Compute the result. */
585 op0
= State
.regs
[ OP
[0] ];
586 op1
= State
.regs
[ OP
[1] ];
590 /* Compute the condition codes. */
592 s
= (result
& 0x80000000);
593 cy
= (result
< op0
|| result
< op1
);
594 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
595 && (op0
& 0x80000000) != (result
& 0x80000000));
597 /* Store the result and condition codes. */
598 State
.regs
[OP
[1]] = result
;
599 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
600 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
601 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
602 trace_output (OP_REG_REG
);
607 /* add sign_extend(imm5), reg */
611 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
614 trace_input ("add", OP_IMM_REG
, 0);
616 /* Compute the result. */
617 temp
= SEXT5 (OP
[0]);
619 op1
= State
.regs
[OP
[1]];
622 /* Compute the condition codes. */
624 s
= (result
& 0x80000000);
625 cy
= (result
< op0
|| result
< op1
);
626 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
627 && (op0
& 0x80000000) != (result
& 0x80000000));
629 /* Store the result and condition codes. */
630 State
.regs
[OP
[1]] = result
;
631 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
632 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
633 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
634 trace_output (OP_IMM_REG
);
639 /* addi sign_extend(imm16), reg, reg */
643 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
645 trace_input ("addi", OP_IMM16_REG_REG
, 0);
647 /* Compute the result. */
649 op0
= EXTEND16 (OP
[2]);
650 op1
= State
.regs
[ OP
[0] ];
653 /* Compute the condition codes. */
655 s
= (result
& 0x80000000);
656 cy
= (result
< op0
|| result
< op1
);
657 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
658 && (op0
& 0x80000000) != (result
& 0x80000000));
660 /* Store the result and condition codes. */
661 State
.regs
[OP
[1]] = result
;
662 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
663 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
664 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
665 trace_output (OP_IMM16_REG_REG
);
674 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
676 trace_input ("sub", OP_REG_REG
, 0);
677 /* Compute the result. */
678 op0
= State
.regs
[ OP
[0] ];
679 op1
= State
.regs
[ OP
[1] ];
682 /* Compute the condition codes. */
684 s
= (result
& 0x80000000);
686 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
687 && (op1
& 0x80000000) != (result
& 0x80000000));
689 /* Store the result and condition codes. */
690 State
.regs
[OP
[1]] = result
;
691 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
692 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
693 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
694 trace_output (OP_REG_REG
);
699 /* subr reg1, reg2 */
703 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
705 trace_input ("subr", OP_REG_REG
, 0);
706 /* Compute the result. */
707 op0
= State
.regs
[ OP
[0] ];
708 op1
= State
.regs
[ OP
[1] ];
711 /* Compute the condition codes. */
713 s
= (result
& 0x80000000);
715 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
716 && (op0
& 0x80000000) != (result
& 0x80000000));
718 /* Store the result and condition codes. */
719 State
.regs
[OP
[1]] = result
;
720 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
721 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
722 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
723 trace_output (OP_REG_REG
);
732 trace_input ("mulh", OP_REG_REG
, 0);
734 State
.regs
[ OP
[1] ] = (EXTEND16 (State
.regs
[ OP
[1] ]) * EXTEND16 (State
.regs
[ OP
[0] ]));
736 trace_output (OP_REG_REG
);
741 /* mulh sign_extend(imm5), reg2 */
745 trace_input ("mulh", OP_IMM_REG
, 0);
747 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[1] ]) * SEXT5 (OP
[0]);
749 trace_output (OP_IMM_REG
);
754 /* mulhi imm16, reg1, reg2 */
758 trace_input ("mulhi", OP_IMM16_REG_REG
, 0);
760 State
.regs
[ OP
[1] ] = EXTEND16 (State
.regs
[ OP
[0] ]) * EXTEND16 (OP
[2]);
762 trace_output (OP_IMM16_REG_REG
);
771 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
773 trace_input ("cmp", OP_REG_REG_CMP
, 0);
774 /* Compute the result. */
775 op0
= State
.regs
[ OP
[0] ];
776 op1
= State
.regs
[ OP
[1] ];
779 /* Compute the condition codes. */
781 s
= (result
& 0x80000000);
783 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
784 && (op1
& 0x80000000) != (result
& 0x80000000));
786 /* Set condition codes. */
787 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
788 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
789 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
790 trace_output (OP_REG_REG_CMP
);
795 /* cmp sign_extend(imm5), reg */
799 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
;
802 /* Compute the result. */
803 trace_input ("cmp", OP_IMM_REG_CMP
, 0);
804 temp
= SEXT5 (OP
[0]);
806 op1
= State
.regs
[OP
[1]];
809 /* Compute the condition codes. */
811 s
= (result
& 0x80000000);
813 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
814 && (op1
& 0x80000000) != (result
& 0x80000000));
816 /* Set condition codes. */
817 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
818 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
819 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0));
820 trace_output (OP_IMM_REG_CMP
);
829 trace_input ("setf", OP_EX1
, 0);
831 State
.regs
[ OP
[1] ] = condition_met (OP
[0]);
833 trace_output (OP_EX1
);
842 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
844 trace_input ("satadd", OP_REG_REG
, 0);
845 /* Compute the result. */
846 op0
= State
.regs
[ OP
[0] ];
847 op1
= State
.regs
[ OP
[1] ];
850 /* Compute the condition codes. */
852 s
= (result
& 0x80000000);
853 cy
= (result
< op0
|| result
< op1
);
854 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
855 && (op0
& 0x80000000) != (result
& 0x80000000));
858 /* Handle saturated results. */
861 /* An overflow that results in a negative result implies that we
862 became too positive. */
868 /* Any other overflow must have thus been too negative. */
874 /* Store the result and condition codes. */
875 State
.regs
[OP
[1]] = result
;
876 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
877 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
878 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
879 | (sat
? PSW_SAT
: 0));
881 trace_output (OP_REG_REG
);
886 /* satadd sign_extend(imm5), reg */
890 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
894 trace_input ("satadd", OP_IMM_REG
, 0);
896 /* Compute the result. */
897 temp
= SEXT5 (OP
[0]);
899 op1
= State
.regs
[OP
[1]];
902 /* Compute the condition codes. */
904 s
= (result
& 0x80000000);
905 cy
= (result
< op0
|| result
< op1
);
906 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
907 && (op0
& 0x80000000) != (result
& 0x80000000));
910 /* Handle saturated results. */
913 /* An overflow that results in a negative result implies that we
914 became too positive. */
920 /* Any other overflow must have thus been too negative. */
926 /* Store the result and condition codes. */
927 State
.regs
[OP
[1]] = result
;
928 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
929 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
930 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
931 | (sat
? PSW_SAT
: 0));
932 trace_output (OP_IMM_REG
);
937 /* satsub reg1, reg2 */
941 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
943 trace_input ("satsub", OP_REG_REG
, 0);
945 /* Compute the result. */
946 op0
= State
.regs
[ OP
[0] ];
947 op1
= State
.regs
[ OP
[1] ];
950 /* Compute the condition codes. */
952 s
= (result
& 0x80000000);
954 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
955 && (op1
& 0x80000000) != (result
& 0x80000000));
958 /* Handle saturated results. */
961 /* An overflow that results in a negative result implies that we
962 became too positive. */
968 /* Any other overflow must have thus been too negative. */
974 /* Store the result and condition codes. */
975 State
.regs
[OP
[1]] = result
;
976 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
977 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
978 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
979 | (sat
? PSW_SAT
: 0));
981 trace_output (OP_REG_REG
);
985 /* satsubi sign_extend(imm16), reg */
989 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
992 trace_input ("satsubi", OP_IMM_REG
, 0);
994 /* Compute the result. */
995 temp
= EXTEND16 (OP
[2]);
997 op1
= State
.regs
[ OP
[0] ];
1000 /* Compute the condition codes. */
1002 s
= (result
& 0x80000000);
1004 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
1005 && (op1
& 0x80000000) != (result
& 0x80000000));
1008 /* Handle saturated results. */
1011 /* An overflow that results in a negative result implies that we
1012 became too positive. */
1013 result
= 0x7fffffff;
1018 /* Any other overflow must have thus been too negative. */
1019 result
= 0x80000000;
1024 /* Store the result and condition codes. */
1025 State
.regs
[OP
[1]] = result
;
1026 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1027 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1028 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1029 | (sat
? PSW_SAT
: 0));
1031 trace_output (OP_IMM_REG
);
1036 /* satsubr reg,reg */
1040 unsigned int op0
, op1
, result
, z
, s
, cy
, ov
, sat
;
1042 trace_input ("satsubr", OP_REG_REG
, 0);
1044 /* Compute the result. */
1045 op0
= State
.regs
[ OP
[0] ];
1046 op1
= State
.regs
[ OP
[1] ];
1049 /* Compute the condition codes. */
1051 s
= (result
& 0x80000000);
1053 ov
= ((op0
& 0x80000000) != (op1
& 0x80000000)
1054 && (op0
& 0x80000000) != (result
& 0x80000000));
1057 /* Handle saturated results. */
1060 /* An overflow that results in a negative result implies that we
1061 became too positive. */
1062 result
= 0x7fffffff;
1067 /* Any other overflow must have thus been too negative. */
1068 result
= 0x80000000;
1073 /* Store the result and condition codes. */
1074 State
.regs
[OP
[1]] = result
;
1075 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
1076 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1077 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
1078 | (sat
? PSW_SAT
: 0));
1080 trace_output (OP_REG_REG
);
1089 unsigned int op0
, op1
, result
, z
, s
;
1091 trace_input ("tst", OP_REG_REG_CMP
, 0);
1093 /* Compute the result. */
1094 op0
= State
.regs
[ OP
[0] ];
1095 op1
= State
.regs
[ OP
[1] ];
1098 /* Compute the condition codes. */
1100 s
= (result
& 0x80000000);
1102 /* Store the condition codes. */
1103 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1104 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1105 trace_output (OP_REG_REG_CMP
);
1110 /* mov sign_extend(imm5), reg */
1114 int value
= SEXT5 (OP
[0]);
1116 trace_input ("mov", OP_IMM_REG_MOVE
, 0);
1118 State
.regs
[ OP
[1] ] = value
;
1120 trace_output (OP_IMM_REG_MOVE
);
1125 /* movhi imm16, reg, reg */
1129 trace_input ("movhi", OP_UIMM16_REG_REG
, 16);
1131 State
.regs
[ OP
[1] ] = State
.regs
[ OP
[0] ] + (OP
[2] << 16);
1133 trace_output (OP_UIMM16_REG_REG
);
1138 /* sar zero_extend(imm5),reg1 */
1142 unsigned int op0
, op1
, result
, z
, s
, cy
;
1144 trace_input ("sar", OP_IMM_REG
, 0);
1146 op1
= State
.regs
[ OP
[1] ];
1147 result
= (signed)op1
>> op0
;
1149 /* Compute the condition codes. */
1151 s
= (result
& 0x80000000);
1152 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1154 /* Store the result and condition codes. */
1155 State
.regs
[ OP
[1] ] = result
;
1156 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1157 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1158 | (cy
? PSW_CY
: 0));
1159 trace_output (OP_IMM_REG
);
1164 /* sar reg1, reg2 */
1168 unsigned int op0
, op1
, result
, z
, s
, cy
;
1170 trace_input ("sar", OP_REG_REG
, 0);
1172 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1173 op1
= State
.regs
[ OP
[1] ];
1174 result
= (signed)op1
>> op0
;
1176 /* Compute the condition codes. */
1178 s
= (result
& 0x80000000);
1179 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1181 /* Store the result and condition codes. */
1182 State
.regs
[OP
[1]] = result
;
1183 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1184 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1185 | (cy
? PSW_CY
: 0));
1186 trace_output (OP_REG_REG
);
1191 /* shl zero_extend(imm5),reg1 */
1195 unsigned int op0
, op1
, result
, z
, s
, cy
;
1197 trace_input ("shl", OP_IMM_REG
, 0);
1199 op1
= State
.regs
[ OP
[1] ];
1200 result
= op1
<< op0
;
1202 /* Compute the condition codes. */
1204 s
= (result
& 0x80000000);
1205 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1207 /* Store the result and condition codes. */
1208 State
.regs
[OP
[1]] = result
;
1209 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1210 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1211 | (cy
? PSW_CY
: 0));
1212 trace_output (OP_IMM_REG
);
1217 /* shl reg1, reg2 */
1221 unsigned int op0
, op1
, result
, z
, s
, cy
;
1223 trace_input ("shl", OP_REG_REG
, 0);
1224 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1225 op1
= State
.regs
[ OP
[1] ];
1226 result
= op1
<< op0
;
1228 /* Compute the condition codes. */
1230 s
= (result
& 0x80000000);
1231 cy
= op0
? (op1
& (1 << (32 - op0
))) : 0;
1233 /* Store the result and condition codes. */
1234 State
.regs
[OP
[1]] = result
;
1235 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1236 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1237 | (cy
? PSW_CY
: 0));
1238 trace_output (OP_REG_REG
);
1243 /* shr zero_extend(imm5),reg1 */
1247 unsigned int op0
, op1
, result
, z
, s
, cy
;
1249 trace_input ("shr", OP_IMM_REG
, 0);
1251 op1
= State
.regs
[ OP
[1] ];
1252 result
= op1
>> op0
;
1254 /* Compute the condition codes. */
1256 s
= (result
& 0x80000000);
1257 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1259 /* Store the result and condition codes. */
1260 State
.regs
[OP
[1]] = result
;
1261 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1262 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1263 | (cy
? PSW_CY
: 0));
1264 trace_output (OP_IMM_REG
);
1269 /* shr reg1, reg2 */
1273 unsigned int op0
, op1
, result
, z
, s
, cy
;
1275 trace_input ("shr", OP_REG_REG
, 0);
1276 op0
= State
.regs
[ OP
[0] ] & 0x1f;
1277 op1
= State
.regs
[ OP
[1] ];
1278 result
= op1
>> op0
;
1280 /* Compute the condition codes. */
1282 s
= (result
& 0x80000000);
1283 cy
= op0
? (op1
& (1 << (op0
- 1))) : 0;
1285 /* Store the result and condition codes. */
1286 State
.regs
[OP
[1]] = result
;
1287 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
1288 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
1289 | (cy
? PSW_CY
: 0));
1290 trace_output (OP_REG_REG
);
1299 unsigned int op0
, op1
, result
, z
, s
;
1301 trace_input ("or", OP_REG_REG
, 0);
1303 /* Compute the result. */
1304 op0
= State
.regs
[ OP
[0] ];
1305 op1
= State
.regs
[ OP
[1] ];
1308 /* Compute the condition codes. */
1310 s
= (result
& 0x80000000);
1312 /* Store the result and condition codes. */
1313 State
.regs
[OP
[1]] = result
;
1314 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1315 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1316 trace_output (OP_REG_REG
);
1321 /* ori zero_extend(imm16), reg, reg */
1325 unsigned int op0
, op1
, result
, z
, s
;
1327 trace_input ("ori", OP_UIMM16_REG_REG
, 0);
1329 op1
= State
.regs
[ OP
[0] ];
1332 /* Compute the condition codes. */
1334 s
= (result
& 0x80000000);
1336 /* Store the result and condition codes. */
1337 State
.regs
[OP
[1]] = result
;
1338 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1339 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1340 trace_output (OP_UIMM16_REG_REG
);
1349 unsigned int op0
, op1
, result
, z
, s
;
1351 trace_input ("and", OP_REG_REG
, 0);
1353 /* Compute the result. */
1354 op0
= State
.regs
[ OP
[0] ];
1355 op1
= State
.regs
[ OP
[1] ];
1358 /* Compute the condition codes. */
1360 s
= (result
& 0x80000000);
1362 /* Store the result and condition codes. */
1363 State
.regs
[OP
[1]] = result
;
1364 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1365 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1366 trace_output (OP_REG_REG
);
1371 /* andi zero_extend(imm16), reg, reg */
1375 unsigned int result
, z
;
1377 trace_input ("andi", OP_UIMM16_REG_REG
, 0);
1379 result
= OP
[2] & State
.regs
[ OP
[0] ];
1381 /* Compute the condition codes. */
1384 /* Store the result and condition codes. */
1385 State
.regs
[ OP
[1] ] = result
;
1387 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1388 PSW
|= (z
? PSW_Z
: 0);
1390 trace_output (OP_UIMM16_REG_REG
);
1399 unsigned int op0
, op1
, result
, z
, s
;
1401 trace_input ("xor", OP_REG_REG
, 0);
1403 /* Compute the result. */
1404 op0
= State
.regs
[ OP
[0] ];
1405 op1
= State
.regs
[ OP
[1] ];
1408 /* Compute the condition codes. */
1410 s
= (result
& 0x80000000);
1412 /* Store the result and condition codes. */
1413 State
.regs
[OP
[1]] = result
;
1414 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1415 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1416 trace_output (OP_REG_REG
);
1421 /* xori zero_extend(imm16), reg, reg */
1425 unsigned int op0
, op1
, result
, z
, s
;
1427 trace_input ("xori", OP_UIMM16_REG_REG
, 0);
1429 op1
= State
.regs
[ OP
[0] ];
1432 /* Compute the condition codes. */
1434 s
= (result
& 0x80000000);
1436 /* Store the result and condition codes. */
1437 State
.regs
[OP
[1]] = result
;
1438 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1439 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1440 trace_output (OP_UIMM16_REG_REG
);
1445 /* not reg1, reg2 */
1449 unsigned int op0
, result
, z
, s
;
1451 trace_input ("not", OP_REG_REG_MOVE
, 0);
1452 /* Compute the result. */
1453 op0
= State
.regs
[ OP
[0] ];
1456 /* Compute the condition codes. */
1458 s
= (result
& 0x80000000);
1460 /* Store the result and condition codes. */
1461 State
.regs
[OP
[1]] = result
;
1462 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
1463 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0));
1464 trace_output (OP_REG_REG_MOVE
);
1473 unsigned int op0
, op1
, op2
;
1476 trace_input ("set1", OP_BIT
, 0);
1477 op0
= State
.regs
[ OP
[0] ];
1479 temp
= EXTEND16 (OP
[2]);
1481 temp
= load_mem (op0
+ op2
, 1);
1483 if ((temp
& (1 << op1
)) == 0)
1486 store_mem (op0
+ op2
, 1, temp
);
1487 trace_output (OP_BIT
);
1496 unsigned int op0
, op1
, op2
;
1499 trace_input ("not1", OP_BIT
, 0);
1500 op0
= State
.regs
[ OP
[0] ];
1502 temp
= EXTEND16 (OP
[2]);
1504 temp
= load_mem (op0
+ op2
, 1);
1506 if ((temp
& (1 << op1
)) == 0)
1509 store_mem (op0
+ op2
, 1, temp
);
1510 trace_output (OP_BIT
);
1519 unsigned int op0
, op1
, op2
;
1522 trace_input ("clr1", OP_BIT
, 0);
1523 op0
= State
.regs
[ OP
[0] ];
1525 temp
= EXTEND16 (OP
[2]);
1527 temp
= load_mem (op0
+ op2
, 1);
1529 if ((temp
& (1 << op1
)) == 0)
1531 temp
&= ~(1 << op1
);
1532 store_mem (op0
+ op2
, 1, temp
);
1533 trace_output (OP_BIT
);
1542 unsigned int op0
, op1
, op2
;
1545 trace_input ("tst1", OP_BIT
, 0);
1546 op0
= State
.regs
[ OP
[0] ];
1548 temp
= EXTEND16 (OP
[2]);
1550 temp
= load_mem (op0
+ op2
, 1);
1552 if ((temp
& (1 << op1
)) == 0)
1554 trace_output (OP_BIT
);
1563 trace_input ("di", OP_NONE
, 0);
1565 trace_output (OP_NONE
);
1574 trace_input ("ei", OP_NONE
, 0);
1576 trace_output (OP_NONE
);
1585 trace_input ("halt", OP_NONE
, 0);
1586 /* FIXME this should put processor into a mode where NMI still handled */
1587 trace_output (OP_NONE
);
1588 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1589 sim_stopped
, SIM_SIGTRAP
);
1597 trace_input ("trap", OP_TRAP
, 0);
1598 trace_output (OP_TRAP
);
1600 /* Trap 31 is used for simulating OS I/O functions */
1604 int save_errno
= errno
;
1607 /* Registers passed to trap 0 */
1609 #define FUNC State.regs[6] /* function number, return value */
1610 #define PARM1 State.regs[7] /* optional parm 1 */
1611 #define PARM2 State.regs[8] /* optional parm 2 */
1612 #define PARM3 State.regs[9] /* optional parm 3 */
1614 /* Registers set by trap 0 */
1616 #define RETVAL State.regs[10] /* return value */
1617 #define RETERR State.regs[11] /* return error code */
1619 /* Turn a pointer in a register into a pointer into real memory. */
1621 #define MEMPTR(x) (map (x))
1629 case TARGET_NEWLIB_V850_SYS_fork
:
1636 case TARGET_NEWLIB_V850_SYS_execve
:
1638 char *path
= fetch_str (simulator
, PARM1
);
1639 char **argv
= fetch_argv (simulator
, PARM2
);
1640 char **envp
= fetch_argv (simulator
, PARM3
);
1641 RETVAL
= execve (path
, (void *)argv
, (void *)envp
);
1651 case TARGET_NEWLIB_V850_SYS_execv
:
1653 char *path
= fetch_str (simulator
, PARM1
);
1654 char **argv
= fetch_argv (simulator
, PARM2
);
1655 RETVAL
= execv (path
, (void *)argv
);
1664 case TARGET_NEWLIB_V850_SYS_pipe
:
1670 RETVAL
= pipe (host_fd
);
1671 SW (buf
, host_fd
[0]);
1672 buf
+= sizeof (uint16_t);
1673 SW (buf
, host_fd
[1]);
1680 case TARGET_NEWLIB_V850_SYS_wait
:
1684 RETVAL
= wait (&status
);
1691 case TARGET_NEWLIB_V850_SYS_read
:
1693 char *buf
= zalloc (PARM3
);
1694 RETVAL
= sim_io_read (simulator
, PARM1
, buf
, PARM3
);
1695 sim_write (simulator
, PARM2
, buf
, PARM3
);
1697 if ((int) RETVAL
< 0)
1698 RETERR
= sim_io_get_errno (simulator
);
1702 case TARGET_NEWLIB_V850_SYS_write
:
1704 char *buf
= zalloc (PARM3
);
1705 sim_read (simulator
, PARM2
, buf
, PARM3
);
1707 RETVAL
= sim_io_write_stdout (simulator
, buf
, PARM3
);
1709 RETVAL
= sim_io_write (simulator
, PARM1
, buf
, PARM3
);
1711 if ((int) RETVAL
< 0)
1712 RETERR
= sim_io_get_errno (simulator
);
1716 case TARGET_NEWLIB_V850_SYS_lseek
:
1717 RETVAL
= sim_io_lseek (simulator
, PARM1
, PARM2
, PARM3
);
1718 if ((int) RETVAL
< 0)
1719 RETERR
= sim_io_get_errno (simulator
);
1722 case TARGET_NEWLIB_V850_SYS_close
:
1723 RETVAL
= sim_io_close (simulator
, PARM1
);
1724 if ((int) RETVAL
< 0)
1725 RETERR
= sim_io_get_errno (simulator
);
1728 case TARGET_NEWLIB_V850_SYS_open
:
1730 char *buf
= fetch_str (simulator
, PARM1
);
1731 RETVAL
= sim_io_open (simulator
, buf
, PARM2
);
1733 if ((int) RETVAL
< 0)
1734 RETERR
= sim_io_get_errno (simulator
);
1738 case TARGET_NEWLIB_V850_SYS_exit
:
1739 if ((PARM1
& 0xffff0000) == 0xdead0000 && (PARM1
& 0xffff) != 0)
1740 /* get signal encoded by kill */
1741 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1742 sim_signalled
, PARM1
& 0xffff);
1743 else if (PARM1
== 0xdead)
1745 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1746 sim_stopped
, SIM_SIGABRT
);
1748 /* PARM1 has exit status */
1749 sim_engine_halt (simulator
, STATE_CPU (simulator
, 0), NULL
, PC
,
1753 case TARGET_NEWLIB_V850_SYS_stat
: /* added at hmsi */
1754 /* stat system call */
1756 struct stat host_stat
;
1758 char *path
= fetch_str (simulator
, PARM1
);
1760 RETVAL
= sim_io_stat (simulator
, path
, &host_stat
);
1765 /* Just wild-assed guesses. */
1766 store_mem (buf
, 2, host_stat
.st_dev
);
1767 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1768 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1769 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1770 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1771 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1772 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1773 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1774 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1775 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1776 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1778 if ((int) RETVAL
< 0)
1779 RETERR
= sim_io_get_errno (simulator
);
1783 case TARGET_NEWLIB_V850_SYS_fstat
:
1784 /* fstat system call */
1786 struct stat host_stat
;
1789 RETVAL
= sim_io_fstat (simulator
, PARM1
, &host_stat
);
1793 /* Just wild-assed guesses. */
1794 store_mem (buf
, 2, host_stat
.st_dev
);
1795 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
1796 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
1797 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
1798 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
1799 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
1800 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
1801 store_mem (buf
+ 16, 4, host_stat
.st_size
);
1802 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
1803 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
1804 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
1806 if ((int) RETVAL
< 0)
1807 RETERR
= sim_io_get_errno (simulator
);
1811 case TARGET_NEWLIB_V850_SYS_rename
:
1813 char *oldpath
= fetch_str (simulator
, PARM1
);
1814 char *newpath
= fetch_str (simulator
, PARM2
);
1815 RETVAL
= sim_io_rename (simulator
, oldpath
, newpath
);
1818 if ((int) RETVAL
< 0)
1819 RETERR
= sim_io_get_errno (simulator
);
1823 case TARGET_NEWLIB_V850_SYS_unlink
:
1825 char *path
= fetch_str (simulator
, PARM1
);
1826 RETVAL
= sim_io_unlink (simulator
, path
);
1828 if ((int) RETVAL
< 0)
1829 RETERR
= sim_io_get_errno (simulator
);
1833 case TARGET_NEWLIB_V850_SYS_chown
:
1835 char *path
= fetch_str (simulator
, PARM1
);
1836 RETVAL
= chown (path
, PARM2
, PARM3
);
1843 case TARGET_NEWLIB_V850_SYS_chmod
:
1845 char *path
= fetch_str (simulator
, PARM1
);
1846 RETVAL
= chmod (path
, PARM2
);
1854 case TARGET_NEWLIB_V850_SYS_time
:
1857 RETVAL
= time (&now
);
1858 store_mem (PARM1
, 4, now
);
1864 #if !defined(__GO32__) && !defined(_WIN32)
1865 case TARGET_NEWLIB_V850_SYS_times
:
1868 RETVAL
= times (&tms
);
1869 store_mem (PARM1
, 4, tms
.tms_utime
);
1870 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
1871 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
1872 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
1878 #if !defined(__GO32__) && !defined(_WIN32)
1879 case TARGET_NEWLIB_V850_SYS_gettimeofday
:
1883 RETVAL
= gettimeofday (&t
, &tz
);
1884 store_mem (PARM1
, 4, t
.tv_sec
);
1885 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
1886 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
1887 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
1894 case TARGET_NEWLIB_V850_SYS_utime
:
1896 /* Cast the second argument to void *, to avoid type mismatch
1897 if a prototype is present. */
1898 sim_io_error (simulator
, "Utime not supported");
1899 /* RETVAL = utime (path, (void *) MEMPTR (PARM2)); */
1912 { /* Trap 0 -> 30 */
1917 ECR
|= 0x40 + OP
[0];
1918 /* Flag that we are now doing exception processing. */
1919 PSW
|= PSW_EP
| PSW_ID
;
1920 PC
= (OP
[0] < 0x10) ? 0x40 : 0x50;
1926 /* tst1 reg2, [reg1] */
1932 trace_input ("tst1", OP_BIT
, 1);
1934 temp
= load_mem (State
.regs
[ OP
[0] ], 1);
1937 if ((temp
& (1 << (State
.regs
[ OP
[1] ] & 0x7))) == 0)
1940 trace_output (OP_BIT
);
1945 /* mulu reg1, reg2, reg3 */
1949 trace_input ("mulu", OP_REG_REG_REG
, 0);
1951 Multiply64 (0, State
.regs
[ OP
[0] ]);
1953 trace_output (OP_REG_REG_REG
);
1958 #define BIT_CHANGE_OP( name, binop ) \
1960 unsigned int temp; \
1962 trace_input (name, OP_BIT_CHANGE, 0); \
1964 bit = 1 << (State.regs[ OP[1] ] & 0x7); \
1965 temp = load_mem (State.regs[ OP[0] ], 1); \
1968 if ((temp & bit) == 0) \
1972 store_mem (State.regs[ OP[0] ], 1, temp); \
1974 trace_output (OP_BIT_CHANGE); \
1978 /* clr1 reg2, [reg1] */
1982 BIT_CHANGE_OP ("clr1", &= ~ );
1985 /* not1 reg2, [reg1] */
1989 BIT_CHANGE_OP ("not1", ^= );
1996 BIT_CHANGE_OP ("set1", |= );
2003 trace_input ("sasf", OP_EX1
, 0);
2005 State
.regs
[ OP
[1] ] = (State
.regs
[ OP
[1] ] << 1) | condition_met (OP
[0]);
2007 trace_output (OP_EX1
);
2012 /* This function is courtesy of Sugimoto at NEC, via Seow Tan
2013 (Soew_Tan@el.nec.com) */
2018 unsigned long int als
,
2019 unsigned long int sfi
,
2020 uint32_t /*unsigned long int*/ * quotient_ptr
,
2021 uint32_t /*unsigned long int*/ * remainder_ptr
,
2025 unsigned long ald
= sfi
>> (N
- 1);
2026 unsigned long alo
= als
;
2031 unsigned int R1
= 1;
2032 unsigned int DBZ
= (als
== 0) ? 1 : 0;
2033 unsigned long alt
= Q
? ~als
: als
;
2036 alo
= ald
+ alt
+ Q
;
2037 C
= (((alt
>> 31) & (ald
>> 31))
2038 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2041 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2042 if ((S
^ (alo
>>31)) && !C
)
2047 sfi
= (sfi
<< (32-N
+1)) | Q
;
2048 ald
= (alo
<< 1) | (sfi
>> 31);
2050 /* 2nd - N-1th Loop */
2051 for (i
= 2; i
< N
; i
++)
2053 alt
= Q
? ~als
: als
;
2054 alo
= ald
+ alt
+ Q
;
2055 C
= (((alt
>> 31) & (ald
>> 31))
2056 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2059 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2060 if ((S
^ (alo
>>31)) && !C
&& !DBZ
)
2065 sfi
= (sfi
<< 1) | Q
;
2066 ald
= (alo
<< 1) | (sfi
>> 31);
2070 alt
= Q
? ~als
: als
;
2071 alo
= ald
+ alt
+ Q
;
2072 C
= (((alt
>> 31) & (ald
>> 31))
2073 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2076 R1
= (alo
== 0) ? 0 : (R1
& Q
);
2077 if ((S
^ (alo
>>31)) && !C
)
2082 * quotient_ptr
= (sfi
<< 1) | Q
;
2083 * remainder_ptr
= Q
? alo
: (alo
+ als
);
2084 * overflow_ptr
= DBZ
| R1
;
2087 /* This function is courtesy of Sugimoto at NEC, via Seow Tan (Soew_Tan@el.nec.com) */
2092 unsigned long int als
,
2093 unsigned long int sfi
,
2094 int32_t /*signed long int*/ * quotient_ptr
,
2095 int32_t /*signed long int*/ * remainder_ptr
,
2099 unsigned long ald
= (signed long) sfi
>> (N
- 1);
2100 unsigned long alo
= als
;
2101 unsigned int SS
= als
>> 31;
2102 unsigned int SD
= sfi
>> 31;
2103 unsigned int R1
= 1;
2105 unsigned int DBZ
= als
== 0 ? 1 : 0;
2106 unsigned int Q
= ~(SS
^ SD
) & 1;
2110 unsigned long alt
= Q
? ~als
: als
;
2115 alo
= ald
+ alt
+ Q
;
2116 C
= (((alt
>> 31) & (ald
>> 31))
2117 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2119 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2121 sfi
= (sfi
<< (32-N
+1)) | Q
;
2122 ald
= (alo
<< 1) | (sfi
>> 31);
2123 if ((alo
>> 31) ^ (ald
>> 31))
2128 /* 2nd - N-1th Loop */
2130 for (i
= 2; i
< N
; i
++)
2132 alt
= Q
? ~als
: als
;
2133 alo
= ald
+ alt
+ Q
;
2134 C
= (((alt
>> 31) & (ald
>> 31))
2135 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2137 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2139 sfi
= (sfi
<< 1) | Q
;
2140 ald
= (alo
<< 1) | (sfi
>> 31);
2141 if ((alo
>> 31) ^ (ald
>> 31))
2148 alt
= Q
? ~als
: als
;
2149 alo
= ald
+ alt
+ Q
;
2150 C
= (((alt
>> 31) & (ald
>> 31))
2151 | (((alt
>> 31) ^ (ald
>> 31)) & (~alo
>> 31)));
2153 R1
= (alo
== 0) ? 0 : (R1
& (Q
^ (SS
^ SD
)));
2154 sfi
= (sfi
<< (32-N
+1));
2160 alt
= Q
? ~als
: als
;
2161 alo
= ald
+ alt
+ Q
;
2163 R1
= R1
& ((~alo
>> 31) ^ SD
);
2164 if ((alo
!= 0) && ((Q
^ (SS
^ SD
)) ^ R1
)) alo
= ald
;
2166 ald
= sfi
= (long) ((sfi
>> 1) | (SS
^ SD
) << 31) >> (32-N
-1) | Q
;
2168 ald
= sfi
= sfi
| Q
;
2170 OV
= DBZ
| ((alo
== 0) ? 0 : R1
);
2172 * remainder_ptr
= alo
;
2175 if (((alo
!= 0) && ((SS
^ SD
) ^ R1
))
2176 || ((alo
== 0) && (SS
^ R1
)))
2181 OV
= (DBZ
| R1
) ? OV
: ((alo
>> 31) & (~ald
>> 31));
2183 * quotient_ptr
= alo
;
2184 * overflow_ptr
= OV
;
2187 /* sdivun imm5, reg1, reg2, reg3 */
2191 uint32_t /*unsigned long int*/ quotient
;
2192 uint32_t /*unsigned long int*/ remainder
;
2193 unsigned long int divide_by
;
2194 unsigned long int divide_this
;
2198 trace_input ("sdivun", OP_IMM_REG_REG_REG
, 0);
2200 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2202 divide_by
= State
.regs
[ OP
[0] ];
2203 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2205 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2207 State
.regs
[ OP
[1] ] = quotient
;
2208 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2210 /* Set condition codes. */
2211 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2213 if (overflow
) PSW
|= PSW_OV
;
2214 if (quotient
== 0) PSW
|= PSW_Z
;
2215 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2217 trace_output (OP_IMM_REG_REG_REG
);
2222 /* sdivn imm5, reg1, reg2, reg3 */
2226 int32_t /*signed long int*/ quotient
;
2227 int32_t /*signed long int*/ remainder
;
2228 signed long int divide_by
;
2229 signed long int divide_this
;
2233 trace_input ("sdivn", OP_IMM_REG_REG_REG
, 0);
2235 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2237 divide_by
= (int32_t) State
.regs
[ OP
[0] ];
2238 divide_this
= (int32_t) (State
.regs
[ OP
[1] ] << imm5
);
2240 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2242 State
.regs
[ OP
[1] ] = quotient
;
2243 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2245 /* Set condition codes. */
2246 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2248 if (overflow
) PSW
|= PSW_OV
;
2249 if (quotient
== 0) PSW
|= PSW_Z
;
2250 if (quotient
< 0) PSW
|= PSW_S
;
2252 trace_output (OP_IMM_REG_REG_REG
);
2257 /* sdivhun imm5, reg1, reg2, reg3 */
2261 uint32_t /*unsigned long int*/ quotient
;
2262 uint32_t /*unsigned long int*/ remainder
;
2263 unsigned long int divide_by
;
2264 unsigned long int divide_this
;
2268 trace_input ("sdivhun", OP_IMM_REG_REG_REG
, 0);
2270 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2272 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2273 divide_this
= State
.regs
[ OP
[1] ] << imm5
;
2275 divun (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2277 State
.regs
[ OP
[1] ] = quotient
;
2278 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2280 /* Set condition codes. */
2281 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2283 if (overflow
) PSW
|= PSW_OV
;
2284 if (quotient
== 0) PSW
|= PSW_Z
;
2285 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2287 trace_output (OP_IMM_REG_REG_REG
);
2292 /* sdivhn imm5, reg1, reg2, reg3 */
2296 int32_t /*signed long int*/ quotient
;
2297 int32_t /*signed long int*/ remainder
;
2298 signed long int divide_by
;
2299 signed long int divide_this
;
2303 trace_input ("sdivhn", OP_IMM_REG_REG_REG
, 0);
2305 imm5
= 32 - ((OP
[3] & 0x3c0000) >> 17);
2307 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2308 divide_this
= (int32_t) (State
.regs
[ OP
[1] ] << imm5
);
2310 divn (imm5
, divide_by
, divide_this
, & quotient
, & remainder
, & overflow
);
2312 State
.regs
[ OP
[1] ] = quotient
;
2313 State
.regs
[ OP
[2] >> 11 ] = remainder
;
2315 /* Set condition codes. */
2316 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2318 if (overflow
) PSW
|= PSW_OV
;
2319 if (quotient
== 0) PSW
|= PSW_Z
;
2320 if (quotient
< 0) PSW
|= PSW_S
;
2322 trace_output (OP_IMM_REG_REG_REG
);
2327 /* divu reg1, reg2, reg3 */
2331 unsigned long int quotient
;
2332 unsigned long int remainder
;
2333 unsigned long int divide_by
;
2334 unsigned long int divide_this
;
2337 trace_input ("divu", OP_REG_REG_REG
, 0);
2339 /* Compute the result. */
2341 divide_by
= State
.regs
[ OP
[0] ];
2342 divide_this
= State
.regs
[ OP
[1] ];
2350 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2351 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2353 /* Set condition codes. */
2354 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2356 if (overflow
) PSW
|= PSW_OV
;
2357 if (quotient
== 0) PSW
|= PSW_Z
;
2358 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2361 trace_output (OP_REG_REG_REG
);
2366 /* div reg1, reg2, reg3 */
2370 signed long int quotient
;
2371 signed long int remainder
;
2372 signed long int divide_by
;
2373 signed long int divide_this
;
2375 trace_input ("div", OP_REG_REG_REG
, 0);
2377 /* Compute the result. */
2379 divide_by
= (int32_t) State
.regs
[ OP
[0] ];
2380 divide_this
= State
.regs
[ OP
[1] ];
2386 else if (divide_by
== -1 && divide_this
== (1L << 31))
2389 PSW
|= PSW_OV
| PSW_S
;
2390 State
.regs
[ OP
[1] ] = (1 << 31);
2391 State
.regs
[ OP
[2] >> 11 ] = 0;
2395 divide_this
= (int32_t) divide_this
;
2396 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2397 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2399 /* Set condition codes. */
2400 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2402 if (quotient
== 0) PSW
|= PSW_Z
;
2403 if (quotient
< 0) PSW
|= PSW_S
;
2406 trace_output (OP_REG_REG_REG
);
2411 /* divhu reg1, reg2, reg3 */
2415 unsigned long int quotient
;
2416 unsigned long int remainder
;
2417 unsigned long int divide_by
;
2418 unsigned long int divide_this
;
2421 trace_input ("divhu", OP_REG_REG_REG
, 0);
2423 /* Compute the result. */
2425 divide_by
= State
.regs
[ OP
[0] ] & 0xffff;
2426 divide_this
= State
.regs
[ OP
[1] ];
2434 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2435 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2437 /* Set condition codes. */
2438 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2440 if (overflow
) PSW
|= PSW_OV
;
2441 if (quotient
== 0) PSW
|= PSW_Z
;
2442 if (quotient
& 0x80000000) PSW
|= PSW_S
;
2445 trace_output (OP_REG_REG_REG
);
2450 /* divh reg1, reg2, reg3 */
2454 signed long int quotient
;
2455 signed long int remainder
;
2456 signed long int divide_by
;
2457 signed long int divide_this
;
2460 trace_input ("divh", OP_REG_REG_REG
, 0);
2462 /* Compute the result. */
2464 divide_by
= EXTEND16 (State
.regs
[ OP
[0] ]);
2465 divide_this
= State
.regs
[ OP
[1] ];
2471 else if (divide_by
== -1 && divide_this
== (1L << 31))
2474 PSW
|= PSW_OV
| PSW_S
;
2475 State
.regs
[ OP
[1] ] = (1 << 31);
2476 State
.regs
[ OP
[2] >> 11 ] = 0;
2480 divide_this
= (int32_t) divide_this
;
2481 State
.regs
[ OP
[1] ] = quotient
= divide_this
/ divide_by
;
2482 State
.regs
[ OP
[2] >> 11 ] = remainder
= divide_this
% divide_by
;
2484 /* Set condition codes. */
2485 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
2487 if (quotient
== 0) PSW
|= PSW_Z
;
2488 if (quotient
< 0) PSW
|= PSW_S
;
2491 trace_output (OP_REG_REG_REG
);
2496 /* mulu imm9, reg2, reg3 */
2500 trace_input ("mulu", OP_IMM_REG_REG
, 0);
2502 Multiply64 (0, (OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0));
2504 trace_output (OP_IMM_REG_REG
);
2509 /* mul imm9, reg2, reg3 */
2513 trace_input ("mul", OP_IMM_REG_REG
, 0);
2515 Multiply64 (1, SEXT9 ((OP
[3] & 0x1f) | ((OP
[3] >> 13) & 0x1e0)));
2517 trace_output (OP_IMM_REG_REG
);
2528 trace_input ("ld.hu", OP_LOAD32
, 2);
2530 adr
= State
.regs
[ OP
[0] ] + EXTEND16 (OP
[2] & ~1);
2533 State
.regs
[ OP
[1] ] = load_mem (adr
, 2);
2535 trace_output (OP_LOAD32
);
2547 trace_input ("ld.bu", OP_LOAD32
, 1);
2549 adr
= (State
.regs
[ OP
[0] ]
2550 + (EXTEND16 (OP
[2] & ~1) | ((OP
[3] >> 5) & 1)));
2552 State
.regs
[ OP
[1] ] = load_mem (adr
, 1);
2554 trace_output (OP_LOAD32
);
2559 /* prepare list12, imm5, imm32 */
2565 trace_input ("prepare", OP_PUSHPOP1
, 0);
2567 /* Store the registers with lower number registers being placed at higher addresses. */
2568 for (i
= 0; i
< 12; i
++)
2569 if ((OP
[3] & (1 << type1_regs
[ i
])))
2572 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2575 SP
-= (OP
[3] & 0x3e) << 1;
2577 EP
= load_mem (PC
+ 4, 4);
2579 trace_output (OP_PUSHPOP1
);
2584 /* prepare list12, imm5, imm16-32 */
2590 trace_input ("prepare", OP_PUSHPOP1
, 0);
2592 /* Store the registers with lower number registers being placed at higher addresses. */
2593 for (i
= 0; i
< 12; i
++)
2594 if ((OP
[3] & (1 << type1_regs
[ i
])))
2597 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2600 SP
-= (OP
[3] & 0x3e) << 1;
2602 EP
= load_mem (PC
+ 4, 2) << 16;
2604 trace_output (OP_PUSHPOP1
);
2609 /* prepare list12, imm5, imm16 */
2615 trace_input ("prepare", OP_PUSHPOP1
, 0);
2617 /* Store the registers with lower number registers being placed at higher addresses. */
2618 for (i
= 0; i
< 12; i
++)
2619 if ((OP
[3] & (1 << type1_regs
[ i
])))
2622 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2625 SP
-= (OP
[3] & 0x3e) << 1;
2627 EP
= EXTEND16 (load_mem (PC
+ 4, 2));
2629 trace_output (OP_PUSHPOP1
);
2634 /* prepare list12, imm5, sp */
2640 trace_input ("prepare", OP_PUSHPOP1
, 0);
2642 /* Store the registers with lower number registers being placed at higher addresses. */
2643 for (i
= 0; i
< 12; i
++)
2644 if ((OP
[3] & (1 << type1_regs
[ i
])))
2647 store_mem (SP
, 4, State
.regs
[ 20 + i
]);
2650 SP
-= (OP
[3] & 0x3e) << 1;
2654 trace_output (OP_PUSHPOP1
);
2659 /* mul reg1, reg2, reg3 */
2663 trace_input ("mul", OP_REG_REG_REG
, 0);
2665 Multiply64 (1, State
.regs
[ OP
[0] ]);
2667 trace_output (OP_REG_REG_REG
);
2678 trace_input ("popmh", OP_PUSHPOP2
, 0);
2680 if (OP
[3] & (1 << 19))
2682 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2684 FEPSW
= load_mem ( SP
& ~ 3, 4);
2685 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2689 EIPSW
= load_mem ( SP
& ~ 3, 4);
2690 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2696 /* Load the registers with lower number registers being retrieved from higher addresses. */
2698 if ((OP
[3] & (1 << type2_regs
[ i
])))
2700 State
.regs
[ i
+ 16 ] = load_mem (SP
& ~ 3, 4);
2704 trace_output (OP_PUSHPOP2
);
2715 trace_input ("popml", OP_PUSHPOP3
, 0);
2717 if (OP
[3] & (1 << 19))
2719 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2721 FEPSW
= load_mem ( SP
& ~ 3, 4);
2722 FEPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2726 EIPSW
= load_mem ( SP
& ~ 3, 4);
2727 EIPC
= load_mem ((SP
+ 4) & ~ 3, 4);
2733 if (OP
[3] & (1 << 3))
2735 PSW
= load_mem (SP
& ~ 3, 4);
2739 /* Load the registers with lower number registers being retrieved from higher addresses. */
2741 if ((OP
[3] & (1 << type3_regs
[ i
])))
2743 State
.regs
[ i
+ 1 ] = load_mem (SP
& ~ 3, 4);
2747 trace_output (OP_PUSHPOP2
);
2758 trace_input ("pushmh", OP_PUSHPOP2
, 0);
2760 /* Store the registers with lower number registers being placed at higher addresses. */
2761 for (i
= 0; i
< 16; i
++)
2762 if ((OP
[3] & (1 << type2_regs
[ i
])))
2765 store_mem (SP
& ~ 3, 4, State
.regs
[ i
+ 16 ]);
2768 if (OP
[3] & (1 << 19))
2772 if ((PSW
& PSW_NP
) && ((PSW
& PSW_EP
) == 0))
2774 store_mem ((SP
+ 4) & ~ 3, 4, FEPC
);
2775 store_mem ( SP
& ~ 3, 4, FEPSW
);
2779 store_mem ((SP
+ 4) & ~ 3, 4, EIPC
);
2780 store_mem ( SP
& ~ 3, 4, EIPSW
);
2784 trace_output (OP_PUSHPOP2
);
2789 /* V850E2R FPU functions */
2791 sim_fpu_status_invalid_snan = 1, -V--- (sim spec.)
2792 sim_fpu_status_invalid_qnan = 2, ----- (sim spec.)
2793 sim_fpu_status_invalid_isi = 4, (inf - inf) -V---
2794 sim_fpu_status_invalid_idi = 8, (inf / inf) -V---
2795 sim_fpu_status_invalid_zdz = 16, (0 / 0) -V---
2796 sim_fpu_status_invalid_imz = 32, (inf * 0) -V---
2797 sim_fpu_status_invalid_cvi = 64, convert to integer -V---
2798 sim_fpu_status_invalid_div0 = 128, (X / 0) --Z--
2799 sim_fpu_status_invalid_cmp = 256, compare ----- (sim spec.)
2800 sim_fpu_status_invalid_sqrt = 512, -V---
2801 sim_fpu_status_rounded = 1024, I----
2802 sim_fpu_status_inexact = 2048, I---- (sim spec.)
2803 sim_fpu_status_overflow = 4096, I--O-
2804 sim_fpu_status_underflow = 8192, I---U
2805 sim_fpu_status_denorm = 16384, ----U (sim spec.)
2809 update_fpsr (SIM_DESC sd
, sim_fpu_status status
, unsigned int mask
, unsigned int double_op_p
)
2811 unsigned int fpsr
= FPSR
& mask
;
2813 unsigned int flags
= 0;
2816 && ((status
& (sim_fpu_status_rounded
2817 | sim_fpu_status_overflow
2818 | sim_fpu_status_inexact
))
2819 || (status
& sim_fpu_status_underflow
2820 && (fpsr
& (FPSR_XEU
| FPSR_XEI
)) == 0
2821 && fpsr
& FPSR_FS
)))
2823 flags
|= FPSR_XCI
| FPSR_XPI
;
2827 && (status
& (sim_fpu_status_invalid_isi
2828 | sim_fpu_status_invalid_imz
2829 | sim_fpu_status_invalid_zdz
2830 | sim_fpu_status_invalid_idi
2831 | sim_fpu_status_invalid_cvi
2832 | sim_fpu_status_invalid_sqrt
2833 | sim_fpu_status_invalid_snan
)))
2835 flags
|= FPSR_XCV
| FPSR_XPV
;
2839 && (status
& sim_fpu_status_invalid_div0
))
2841 flags
|= FPSR_XCV
| FPSR_XPV
;
2845 && (status
& sim_fpu_status_overflow
))
2847 flags
|= FPSR_XCO
| FPSR_XPO
;
2850 if (((fpsr
& FPSR_XEU
) || (fpsr
& FPSR_FS
) == 0)
2851 && (status
& (sim_fpu_status_underflow
2852 | sim_fpu_status_denorm
)))
2854 flags
|= FPSR_XCU
| FPSR_XPU
;
2862 SignalExceptionFPE (sd
, double_op_p
);
2869 SignalException (SIM_DESC sd
)
2873 PSW
= PSW
& ~(PSW_NPV
| PSW_DMP
| PSW_IMP
);
2878 SignalExceptionFPE (SIM_DESC sd
, unsigned int double_op_p
)
2880 if (((PSW
& (PSW_NP
|PSW_ID
)) == 0)
2881 || !(FPSR
& (double_op_p
? FPSR_DEM
: FPSR_SEM
)))
2885 EIIC
= (FPSR
& (double_op_p
? FPSR_DEM
: FPSR_SEM
))
2887 PSW
|= (PSW_EP
| PSW_ID
);
2890 SignalException (sd
);
2895 check_invalid_snan (SIM_DESC sd
, sim_fpu_status status
, unsigned int double_op_p
)
2897 if ((FPSR
& FPSR_XEI
)
2898 && (status
& sim_fpu_status_invalid_snan
))
2903 SignalExceptionFPE (sd
, double_op_p
);
2908 v850_float_compare (SIM_DESC sd
, int cmp
, sim_fpu wop1
, sim_fpu wop2
, int double_op_p
)
2912 if (sim_fpu_is_nan (&wop1
) || sim_fpu_is_nan (&wop2
))
2916 if (FPSR
& FPSR_XEV
)
2918 FPSR
|= FPSR_XCV
| FPSR_XPV
;
2919 SignalExceptionFPE (sd
, double_op_p
);
2977 else if (sim_fpu_is_infinity (&wop1
) && sim_fpu_is_infinity (&wop2
)
2978 && sim_fpu_sign (&wop1
) == sim_fpu_sign (&wop2
))
3036 int gt
= 0,lt
= 0,eq
= 0, status
;
3038 status
= sim_fpu_cmp (&wop1
, &wop2
);
3042 case SIM_FPU_IS_SNAN
:
3043 case SIM_FPU_IS_QNAN
:
3047 case SIM_FPU_IS_NINF
:
3050 case SIM_FPU_IS_PINF
:
3053 case SIM_FPU_IS_NNUMBER
:
3056 case SIM_FPU_IS_PNUMBER
:
3059 case SIM_FPU_IS_NDENORM
:
3062 case SIM_FPU_IS_PDENORM
:
3065 case SIM_FPU_IS_NZERO
:
3066 case SIM_FPU_IS_PZERO
:
3124 ASSERT (result
!= -1);
3129 v850_div (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
, unsigned int *op3p
)
3131 signed long int quotient
;
3132 signed long int remainder
;
3133 signed long int divide_by
;
3134 signed long int divide_this
;
3135 bfd_boolean overflow
= FALSE
;
3137 /* Compute the result. */
3138 divide_by
= (int32_t)op0
;
3139 divide_this
= (int32_t)op1
;
3141 if (divide_by
== 0 || (divide_by
== -1 && divide_this
== (1 << 31)))
3147 quotient
= divide_this
/ divide_by
;
3148 remainder
= divide_this
% divide_by
;
3150 /* Set condition codes. */
3151 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3153 if (overflow
) PSW
|= PSW_OV
;
3154 if (quotient
== 0) PSW
|= PSW_Z
;
3155 if (quotient
< 0) PSW
|= PSW_S
;
3162 v850_divu (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
, unsigned int *op3p
)
3164 unsigned long int quotient
;
3165 unsigned long int remainder
;
3166 unsigned long int divide_by
;
3167 unsigned long int divide_this
;
3168 bfd_boolean overflow
= FALSE
;
3170 /* Compute the result. */
3181 quotient
= divide_this
/ divide_by
;
3182 remainder
= divide_this
% divide_by
;
3184 /* Set condition codes. */
3185 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3187 if (overflow
) PSW
|= PSW_OV
;
3188 if (quotient
== 0) PSW
|= PSW_Z
;
3189 if (quotient
& 0x80000000) PSW
|= PSW_S
;
3196 v850_sar (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3198 unsigned int result
, z
, s
, cy
;
3201 result
= (signed)op1
>> op0
;
3203 /* Compute the condition codes. */
3205 s
= (result
& 0x80000000);
3206 cy
= (op1
& (1 << (op0
- 1)));
3208 /* Store the result and condition codes. */
3209 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3210 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3211 | (cy
? PSW_CY
: 0));
3217 v850_shl (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3219 unsigned int result
, z
, s
, cy
;
3222 result
= op1
<< op0
;
3224 /* Compute the condition codes. */
3226 s
= (result
& 0x80000000);
3227 cy
= (op1
& (1 << (32 - op0
)));
3229 /* Store the result and condition codes. */
3230 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3231 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3232 | (cy
? PSW_CY
: 0));
3238 v850_rotl (SIM_DESC sd
, unsigned int amount
, unsigned int src
, unsigned int * dest
)
3240 unsigned int result
, z
, s
, cy
;
3243 result
= src
<< amount
;
3244 result
|= src
>> (32 - amount
);
3246 /* Compute the condition codes. */
3248 s
= (result
& 0x80000000);
3249 cy
= ! (result
& 1);
3251 /* Store the result and condition codes. */
3252 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3253 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3254 | (cy
? PSW_CY
: 0));
3260 v850_bins (SIM_DESC sd
, unsigned int source
, unsigned int lsb
, unsigned int msb
,
3261 unsigned int * dest
)
3264 unsigned int result
, pos
, width
;
3268 width
= (msb
- lsb
) + 1;
3270 /* A width of 32 exhibits undefined behavior on the shift. The easiest
3271 way to make this code safe is to just avoid that case and set the mask
3272 to the right value. */
3276 mask
= ~ (-(1 << width
));
3280 result
= (* dest
) & ~ mask
;
3281 result
|= source
<< pos
;
3283 /* Compute the condition codes. */
3285 s
= result
& 0x80000000;
3287 /* Store the result and condition codes. */
3288 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
);
3289 PSW
|= (z
? PSW_Z
: 0) | (s
? PSW_S
: 0);
3295 v850_shr (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3297 unsigned int result
, z
, s
, cy
;
3300 result
= op1
>> op0
;
3302 /* Compute the condition codes. */
3304 s
= (result
& 0x80000000);
3305 cy
= (op1
& (1 << (op0
- 1)));
3307 /* Store the result and condition codes. */
3308 PSW
&= ~(PSW_Z
| PSW_S
| PSW_OV
| PSW_CY
);
3309 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3310 | (cy
? PSW_CY
: 0));
3316 v850_satadd (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3318 unsigned int result
, z
, s
, cy
, ov
, sat
;
3322 /* Compute the condition codes. */
3324 s
= (result
& 0x80000000);
3325 cy
= (result
< op0
|| result
< op1
);
3326 ov
= ((op0
& 0x80000000) == (op1
& 0x80000000)
3327 && (op0
& 0x80000000) != (result
& 0x80000000));
3330 /* Store the result and condition codes. */
3331 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3332 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3333 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
3334 | (sat
? PSW_SAT
: 0));
3336 /* Handle saturated results. */
3339 result
= 0x7fffffff;
3344 result
= 0x80000000;
3352 v850_satsub (SIM_DESC sd
, unsigned int op0
, unsigned int op1
, unsigned int *op2p
)
3354 unsigned int result
, z
, s
, cy
, ov
, sat
;
3356 /* Compute the result. */
3359 /* Compute the condition codes. */
3361 s
= (result
& 0x80000000);
3363 ov
= ((op1
& 0x80000000) != (op0
& 0x80000000)
3364 && (op1
& 0x80000000) != (result
& 0x80000000));
3367 /* Store the result and condition codes. */
3368 PSW
&= ~(PSW_Z
| PSW_S
| PSW_CY
| PSW_OV
);
3369 PSW
|= ((z
? PSW_Z
: 0) | (s
? PSW_S
: 0)
3370 | (cy
? PSW_CY
: 0) | (ov
? PSW_OV
: 0)
3371 | (sat
? PSW_SAT
: 0));
3373 /* Handle saturated results. */
3376 result
= 0x7fffffff;
3381 result
= 0x80000000;
3389 load_data_mem (SIM_DESC sd
,
3398 data
= sim_core_read_unaligned_1 (STATE_CPU (sd
, 0),
3399 PC
, read_map
, addr
);
3402 data
= sim_core_read_unaligned_2 (STATE_CPU (sd
, 0),
3403 PC
, read_map
, addr
);
3406 data
= sim_core_read_unaligned_4 (STATE_CPU (sd
, 0),
3407 PC
, read_map
, addr
);
3416 store_data_mem (SIM_DESC sd
,
3424 store_mem (addr
, 1, data
);
3427 store_mem (addr
, 2, data
);
3430 store_mem (addr
, 4, data
);
3438 mpu_load_mem_test (SIM_DESC sd
, unsigned int addr
, int size
, int base_reg
)
3444 if (IPE0
&& addr
>= IPA2ADDR (IPA0L
) && addr
<= IPA2ADDR (IPA0L
) && IPR0
)
3448 else if (IPE1
&& addr
>= IPA2ADDR (IPA1L
) && addr
<= IPA2ADDR (IPA1L
) && IPR1
)
3452 else if (IPE2
&& addr
>= IPA2ADDR (IPA2L
) && addr
<= IPA2ADDR (IPA2L
) && IPR2
)
3456 else if (IPE3
&& addr
>= IPA2ADDR (IPA3L
) && addr
<= IPA2ADDR (IPA3L
) && IPR3
)
3460 else if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3462 /* preifarallel area */
3464 else if (addr
>= PPA2ADDR (SPAL
) && addr
<= DPA2ADDR (SPAU
))
3468 else if (DPE0
&& addr
>= DPA2ADDR (DPA0L
) && addr
<= DPA2ADDR (DPA0L
) && DPR0
3469 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3473 else if (DPE1
&& addr
>= DPA2ADDR (DPA1L
) && addr
<= DPA2ADDR (DPA1L
) && DPR1
3474 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3478 else if (DPE2
&& addr
>= DPA2ADDR (DPA2L
) && addr
<= DPA2ADDR (DPA2L
) && DPR2
3479 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3483 else if (DPE3
&& addr
>= DPA2ADDR (DPA3L
) && addr
<= DPA2ADDR (DPA3L
) && DPR3
3484 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3490 VMECR
&= ~(VMECR_VMW
| VMECR_VMX
);
3498 SignalException (sd
);
3507 mpu_store_mem_test (SIM_DESC sd
, unsigned int addr
, int size
, int base_reg
)
3513 if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3515 /* preifarallel area */
3517 else if (addr
>= PPA2ADDR (SPAL
) && addr
<= DPA2ADDR (SPAU
))
3521 else if (DPE0
&& addr
>= DPA2ADDR (DPA0L
) && addr
<= DPA2ADDR (DPA0L
) && DPW0
3522 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3526 else if (DPE1
&& addr
>= DPA2ADDR (DPA1L
) && addr
<= DPA2ADDR (DPA1L
) && DPW1
3527 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3531 else if (DPE2
&& addr
>= DPA2ADDR (DPA2L
) && addr
<= DPA2ADDR (DPA2L
) && DPW2
3532 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3536 else if (DPE3
&& addr
>= DPA2ADDR (DPA3L
) && addr
<= DPA2ADDR (DPA3L
) && DPW3
3537 && ((SPAL
& SPAL_SPS
) ? base_reg
== SP_REGNO
: 1))
3543 if (addr
>= PPA2ADDR (PPA
& ~PPM
) && addr
<= DPA2ADDR (PPA
| PPM
))
3558 VMECR
&= ~(VMECR_VMW
| VMECR_VMX
);