sys-utils/hwclock-cmos.c

   1 /*
   2  * i386 CMOS starts out with 14 bytes clock data alpha has something
   3  * similar, but with details depending on the machine type.
   4  *
   5  * byte 0: seconds              0-59
   6  * byte 2: minutes              0-59
   7  * byte 4: hours                0-23 in 24hr mode,
   8  *                              1-12 in 12hr mode, with high bit unset/set
   9  *                                      if am/pm.
  10  * byte 6: weekday              1-7, Sunday=1
  11  * byte 7: day of the month     1-31
  12  * byte 8: month                1-12
  13  * byte 9: year                 0-99
  14  *
  15  * Numbers are stored in BCD/binary if bit 2 of byte 11 is unset/set The
  16  * clock is in 12hr/24hr mode if bit 1 of byte 11 is unset/set The clock is
  17  * undefined (being updated) if bit 7 of byte 10 is set. The clock is frozen
  18  * (to be updated) by setting bit 7 of byte 11 Bit 7 of byte 14 indicates
  19  * whether the CMOS clock is reliable: it is 1 if RTC power has been good
  20  * since this bit was last read; it is 0 when the battery is dead and system
  21  * power has been off.
  22  *
  23  * Avoid setting the RTC clock within 2 seconds of the day rollover that
  24  * starts a new month or enters daylight saving time.
  25  *
  26  * The century situation is messy:
  27  *
  28  * Usually byte 50 (0x32) gives the century (in BCD, so 19 or 20 hex), but
  29  * IBM PS/2 has (part of) a checksum there and uses byte 55 (0x37).
  30  * Sometimes byte 127 (0x7f) or Bank 1, byte 0x48 gives the century. The
  31  * original RTC will not access any century byte; some modern versions will.
  32  * If a modern RTC or BIOS increments the century byte it may go from 0x19
  33  * to 0x20, but in some buggy cases 0x1a is produced.
  34  */
  35 /*
  36  * A struct tm has int fields
  37  *   tm_sec     0-59, 60 or 61 only for leap seconds
  38  *   tm_min     0-59
  39  *   tm_hour    0-23
  40  *   tm_mday    1-31
  41  *   tm_mon     0-11
  42  *   tm_year    number of years since 1900
  43  *   tm_wday    0-6, 0=Sunday
  44  *   tm_yday    0-365
  45  *   tm_isdst   >0: yes, 0: no, <0: unknown
  46  */
  47
  48 #include <fcntl.h>
  49 #include <stdio.h>
  50 #include <string.h>
  51 #include <time.h>
  52 #include <unistd.h>
  53
  54 #include "c.h"
  55 #include "nls.h"
  56 #include "pathnames.h"
  57
  58 /* for inb, outb */
  59 #ifdef HAVE_SYS_IO_H
  60 # include <sys/io.h>
  61 #elif defined(HAVE_ASM_IO_H)
  62 # include <asm/io.h>
  63 #else
  64 # error "no sys/io.h or asm/io.h"
  65 #endif  /* HAVE_SYS_IO_H, HAVE_ASM_IO_H */
  66
  67 #include "hwclock.h"
  68
  69 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
  70 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
  71
  72 #define IOPL_NOT_IMPLEMENTED -2
  73
  74 /*
  75  * POSIX uses 1900 as epoch for a struct tm, and 1970 for a time_t.
  76  */
  77 #define TM_EPOCH 1900
  78
  79 static unsigned short clock_ctl_addr = 0x70;
  80 static unsigned short clock_data_addr = 0x71;
  81
  82 /*
  83  * Hmmh, this isn't very atomic. Maybe we should force an error instead?
  84  *
  85  * TODO: optimize the access to CMOS by mlockall(MCL_CURRENT) and SCHED_FIFO
  86  */
  87 static unsigned long atomic(unsigned long (*op) (unsigned long),
  88                             unsigned long arg)
  89 {
  90         return (*op) (arg);
  91 }
  92
  93 /*
  94  * We only want to read CMOS data, but unfortunately writing to bit 7
  95  * disables (1) or enables (0) NMI; since this bit is read-only we have
  96  * to guess the old status. Various docs suggest that one should disable
  97  * NMI while reading/writing CMOS data, and enable it again afterwards.
  98  * This would yield the sequence
  99  *
 100  *  outb (reg | 0x80, 0x70);
 101  *  val = inb(0x71);
 102  *  outb (0x0d, 0x70);  // 0x0d: random read-only location
 103  *
 104  * Other docs state that "any write to 0x70 should be followed by an
 105  * action to 0x71 or the RTC will be left in an unknown state". Most
 106  * docs say that it doesn't matter at all what one does.
 107  *
 108  * bit 0x80: disable NMI while reading - should we? Let us follow the
 109  * kernel and not disable. Called only with 0 <= reg < 128
 110  */
 111
 112 static inline unsigned long cmos_read(unsigned long reg)
 113 {
 114         outb(reg, clock_ctl_addr);
 115         return inb(clock_data_addr);
 116 }
 117
 118 static inline unsigned long cmos_write(unsigned long reg, unsigned long val)
 119 {
 120         outb(reg, clock_ctl_addr);
 121         outb(val, clock_data_addr);
 122         return 0;
 123 }
 124
 125 static unsigned long cmos_set_time(unsigned long arg)
 126 {
 127         unsigned char save_control, save_freq_select, pmbit = 0;
 128         struct tm tm = *(struct tm *)arg;
 129
 130 /*
 131  * CMOS byte 10 (clock status register A) has 3 bitfields:
 132  * bit 7: 1 if data invalid, update in progress (read-only bit)
 133  *         (this is raised 224 us before the actual update starts)
 134  *  6-4    select base frequency
 135  *         010: 32768 Hz time base (default)
 136  *         111: reset
 137  *         all other combinations are manufacturer-dependent
 138  *         (e.g.: DS1287: 010 = start oscillator, anything else = stop)
 139  *  3-0    rate selection bits for interrupt
 140  *         0000 none (may stop RTC)
 141  *         0001, 0010 give same frequency as 1000, 1001
 142  *         0011 122 microseconds (minimum, 8192 Hz)
 143  *         .... each increase by 1 halves the frequency, doubles the period
 144  *         1111 500 milliseconds (maximum, 2 Hz)
 145  *         0110 976.562 microseconds (default 1024 Hz)
 146  */
 147         save_control = cmos_read(11);   /* tell the clock it's being set */
 148         cmos_write(11, (save_control | 0x80));
 149         save_freq_select = cmos_read(10);       /* stop and reset prescaler */
 150         cmos_write(10, (save_freq_select | 0x70));
 151
 152         tm.tm_year %= 100;
 153         tm.tm_mon += 1;
 154         tm.tm_wday += 1;
 155
 156         if (!(save_control & 0x02)) {   /* 12hr mode; the default is 24hr mode */
 157                 if (tm.tm_hour == 0)
 158                         tm.tm_hour = 24;
 159                 if (tm.tm_hour > 12) {
 160                         tm.tm_hour -= 12;
 161                         pmbit = 0x80;
 162                 }
 163         }
 164
 165         if (!(save_control & 0x04)) {   /* BCD mode - the default */
 166                 BIN_TO_BCD(tm.tm_sec);
 167                 BIN_TO_BCD(tm.tm_min);
 168                 BIN_TO_BCD(tm.tm_hour);
 169                 BIN_TO_BCD(tm.tm_wday);
 170                 BIN_TO_BCD(tm.tm_mday);
 171                 BIN_TO_BCD(tm.tm_mon);
 172                 BIN_TO_BCD(tm.tm_year);
 173         }
 174
 175         cmos_write(0, tm.tm_sec);
 176         cmos_write(2, tm.tm_min);
 177         cmos_write(4, tm.tm_hour | pmbit);
 178         cmos_write(6, tm.tm_wday);
 179         cmos_write(7, tm.tm_mday);
 180         cmos_write(8, tm.tm_mon);
 181         cmos_write(9, tm.tm_year);
 182
 183         /*
 184          * The kernel sources, linux/arch/i386/kernel/time.c, have the
 185          * following comment:
 186          *
 187          * The following flags have to be released exactly in this order,
 188          * otherwise the DS12887 (popular MC146818A clone with integrated
 189          * battery and quartz) will not reset the oscillator and will not
 190          * update precisely 500 ms later. You won't find this mentioned in
 191          * the Dallas Semiconductor data sheets, but who believes data
 192          * sheets anyway ... -- Markus Kuhn
 193          */
 194         cmos_write(11, save_control);
 195         cmos_write(10, save_freq_select);
 196         return 0;
 197 }
 198
 199 static int hclock_read(unsigned long reg)
 200 {
 201         return atomic(cmos_read, reg);
 202 }
 203
 204 static void hclock_set_time(const struct tm *tm)
 205 {
 206         atomic(cmos_set_time, (unsigned long)(tm));
 207 }
 208
 209 static inline int cmos_clock_busy(void)
 210 {
 211         return
 212             /* poll bit 7 (UIP) of Control Register A */
 213             (hclock_read(10) & 0x80);
 214 }
 215
 216 static int synchronize_to_clock_tick_cmos(const struct hwclock_control *ctl
 217                                           __attribute__((__unused__)))
 218 {
 219         int i;
 220
 221         /*
 222          * Wait for rise. Should be within a second, but in case something
 223          * weird happens, we have a limit on this loop to reduce the impact
 224          * of this failure.
 225          */
 226         for (i = 0; !cmos_clock_busy(); i++)
 227                 if (i >= 10000000)
 228                         return 1;
 229
 230         /* Wait for fall.  Should be within 2.228 ms. */
 231         for (i = 0; cmos_clock_busy(); i++)
 232                 if (i >= 1000000)
 233                         return 1;
 234         return 0;
 235 }
 236
 237 /*
 238  * Read the hardware clock and return the current time via <tm> argument.
 239  * Assume we have an ISA machine and read the clock directly with CPU I/O
 240  * instructions.
 241  *
 242  * This function is not totally reliable.  It takes a finite and
 243  * unpredictable amount of time to execute the code below. During that time,
 244  * the clock may change and we may even read an invalid value in the middle
 245  * of an update. We do a few checks to minimize this possibility, but only
 246  * the kernel can actually read the clock properly, since it can execute
 247  * code in a short and predictable amount of time (by turning of
 248  * interrupts).
 249  *
 250  * In practice, the chance of this function returning the wrong time is
 251  * extremely remote.
 252  */
 253 static int read_hardware_clock_cmos(const struct hwclock_control *ctl
 254                                     __attribute__((__unused__)), struct tm *tm)
 255 {
 256         unsigned char status = 0, pmbit = 0;
 257
 258         while (1) {
 259                 /*
 260                  * Bit 7 of Byte 10 of the Hardware Clock value is the
 261                  * Update In Progress (UIP) bit, which is on while and 244
 262                  * uS before the Hardware Clock updates itself. It updates
 263                  * the counters individually, so reading them during an
 264                  * update would produce garbage. The update takes 2mS, so we
 265                  * could be spinning here that long waiting for this bit to
 266                  * turn off.
 267                  *
 268                  * Furthermore, it is pathologically possible for us to be
 269                  * in this code so long that even if the UIP bit is not on
 270                  * at first, the clock has changed while we were running. We
 271                  * check for that too, and if it happens, we start over.
 272                  */
 273                 if (!cmos_clock_busy()) {
 274                         /* No clock update in progress, go ahead and read */
 275                         tm->tm_sec = hclock_read(0);
 276                         tm->tm_min = hclock_read(2);
 277                         tm->tm_hour = hclock_read(4);
 278                         tm->tm_wday = hclock_read(6);
 279                         tm->tm_mday = hclock_read(7);
 280                         tm->tm_mon = hclock_read(8);
 281                         tm->tm_year = hclock_read(9);
 282                         status = hclock_read(11);
 283                         /*
 284                          * Unless the clock changed while we were reading,
 285                          * consider this a good clock read .
 286                          */
 287                         if (tm->tm_sec == hclock_read(0))
 288                                 break;
 289                 }
 290                 /*
 291                  * Yes, in theory we could have been running for 60 seconds
 292                  * and the above test wouldn't work!
 293                  */
 294         }
 295
 296         if (!(status & 0x04)) { /* BCD mode - the default */
 297                 BCD_TO_BIN(tm->tm_sec);
 298                 BCD_TO_BIN(tm->tm_min);
 299                 pmbit = (tm->tm_hour & 0x80);
 300                 tm->tm_hour &= 0x7f;
 301                 BCD_TO_BIN(tm->tm_hour);
 302                 BCD_TO_BIN(tm->tm_wday);
 303                 BCD_TO_BIN(tm->tm_mday);
 304                 BCD_TO_BIN(tm->tm_mon);
 305                 BCD_TO_BIN(tm->tm_year);
 306         }
 307
 308         /*
 309          * We don't use the century byte of the Hardware Clock since we
 310          * don't know its address (usually 50 or 55). Here, we follow the
 311          * advice of the X/Open Base Working Group: "if century is not
 312          * specified, then values in the range [69-99] refer to years in the
 313          * twentieth century (1969 to 1999 inclusive), and values in the
 314          * range [00-68] refer to years in the twenty-first century (2000 to
 315          * 2068 inclusive)."
 316          */
 317         tm->tm_wday -= 1;
 318         tm->tm_mon -= 1;
 319         if (tm->tm_year < 69)
 320                 tm->tm_year += 100;
 321         if (pmbit) {
 322                 tm->tm_hour += 12;
 323                 if (tm->tm_hour == 24)
 324                         tm->tm_hour = 0;
 325         }
 326
 327         tm->tm_isdst = -1;      /* don't know whether it's daylight */
 328         return 0;
 329 }
 330
 331 static int set_hardware_clock_cmos(const struct hwclock_control *ctl
 332                                    __attribute__((__unused__)),
 333                                    const struct tm *new_broken_time)
 334 {
 335         hclock_set_time(new_broken_time);
 336         return 0;
 337 }
 338
 339 # if defined(HAVE_IOPL)
 340 static int i386_iopl(const int level)
 341 {
 342         return iopl(level);
 343 }
 344 # else
 345 static int i386_iopl(const int level __attribute__ ((__unused__)))
 346 {
 347         extern int ioperm(unsigned long from, unsigned long num, int turn_on);
 348         return ioperm(clock_ctl_addr, 2, 1);
 349 }
 350 # endif
 351
 352 static int get_permissions_cmos(void)
 353 {
 354         int rc;
 355
 356         rc = i386_iopl(3);
 357         if (rc == IOPL_NOT_IMPLEMENTED) {
 358                 warnx(_("ISA port access is not implemented"));
 359         } else if (rc != 0) {
 360                 warn(_("iopl() port access failed"));
 361         }
 362         return rc;
 363 }
 364
 365 static const char *get_device_path(void)
 366 {
 367         return NULL;
 368 }
 369
 370 static struct clock_ops cmos_interface = {
 371         N_("Using direct ISA access to the clock"),
 372         get_permissions_cmos,
 373         read_hardware_clock_cmos,
 374         set_hardware_clock_cmos,
 375         synchronize_to_clock_tick_cmos,
 376         get_device_path,
 377 };
 378
 379 /*
 380  * return &cmos if cmos clock present, NULL otherwise.
 381  */
 382 struct clock_ops *probe_for_cmos_clock(void)
 383 {
 384         return &cmos_interface;
 385 }