2 * SPDX-License-Identifier: GPL-2.0-or-later
4 * i386 CMOS starts out with 14 bytes clock data alpha has something
5 * similar, but with details depending on the machine type.
9 * byte 4: hours 0-23 in 24hr mode,
10 * 1-12 in 12hr mode, with high bit unset/set
12 * byte 6: weekday 1-7, Sunday=1
13 * byte 7: day of the month 1-31
17 * Numbers are stored in BCD/binary if bit 2 of byte 11 is unset/set The
18 * clock is in 12hr/24hr mode if bit 1 of byte 11 is unset/set The clock is
19 * undefined (being updated) if bit 7 of byte 10 is set. The clock is frozen
20 * (to be updated) by setting bit 7 of byte 11 Bit 7 of byte 14 indicates
21 * whether the CMOS clock is reliable: it is 1 if RTC power has been good
22 * since this bit was last read; it is 0 when the battery is dead and system
25 * Avoid setting the RTC clock within 2 seconds of the day rollover that
26 * starts a new month or enters daylight saving time.
28 * The century situation is messy:
30 * Usually byte 50 (0x32) gives the century (in BCD, so 19 or 20 hex), but
31 * IBM PS/2 has (part of) a checksum there and uses byte 55 (0x37).
32 * Sometimes byte 127 (0x7f) or Bank 1, byte 0x48 gives the century. The
33 * original RTC will not access any century byte; some modern versions will.
34 * If a modern RTC or BIOS increments the century byte it may go from 0x19
35 * to 0x20, but in some buggy cases 0x1a is produced.
38 * A struct tm has int fields
39 * tm_sec 0-59, 60 or 61 only for leap seconds
44 * tm_year number of years since 1900
45 * tm_wday 0-6, 0=Sunday
47 * tm_isdst >0: yes, 0: no, <0: unknown
58 #include "pathnames.h"
63 #elif defined(HAVE_ASM_IO_H)
66 # error "no sys/io.h or asm/io.h"
67 #endif /* HAVE_SYS_IO_H, HAVE_ASM_IO_H */
71 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
72 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
74 #define IOPL_NOT_IMPLEMENTED -2
77 * POSIX uses 1900 as epoch for a struct tm, and 1970 for a time_t.
81 static unsigned short clock_ctl_addr
= 0x70;
82 static unsigned short clock_data_addr
= 0x71;
85 * Hmmh, this isn't very atomic. Maybe we should force an error instead?
87 * TODO: optimize the access to CMOS by mlockall(MCL_CURRENT) and SCHED_FIFO
89 static unsigned long atomic(unsigned long (*op
) (unsigned long),
96 * We only want to read CMOS data, but unfortunately writing to bit 7
97 * disables (1) or enables (0) NMI; since this bit is read-only we have
98 * to guess the old status. Various docs suggest that one should disable
99 * NMI while reading/writing CMOS data, and enable it again afterwards.
100 * This would yield the sequence
102 * outb (reg | 0x80, 0x70);
104 * outb (0x0d, 0x70); // 0x0d: random read-only location
106 * Other docs state that "any write to 0x70 should be followed by an
107 * action to 0x71 or the RTC will be left in an unknown state". Most
108 * docs say that it doesn't matter at all what one does.
110 * bit 0x80: disable NMI while reading - should we? Let us follow the
111 * kernel and not disable. Called only with 0 <= reg < 128
114 static inline unsigned long cmos_read(unsigned long reg
)
116 outb(reg
, clock_ctl_addr
);
117 return inb(clock_data_addr
);
120 static inline unsigned long cmos_write(unsigned long reg
, unsigned long val
)
122 outb(reg
, clock_ctl_addr
);
123 outb(val
, clock_data_addr
);
127 static unsigned long cmos_set_time(unsigned long arg
)
129 unsigned char save_control
, save_freq_select
, pmbit
= 0;
130 struct tm tm
= *(struct tm
*)arg
;
133 * CMOS byte 10 (clock status register A) has 3 bitfields:
134 * bit 7: 1 if data invalid, update in progress (read-only bit)
135 * (this is raised 224 us before the actual update starts)
136 * 6-4 select base frequency
137 * 010: 32768 Hz time base (default)
139 * all other combinations are manufacturer-dependent
140 * (e.g.: DS1287: 010 = start oscillator, anything else = stop)
141 * 3-0 rate selection bits for interrupt
142 * 0000 none (may stop RTC)
143 * 0001, 0010 give same frequency as 1000, 1001
144 * 0011 122 microseconds (minimum, 8192 Hz)
145 * .... each increase by 1 halves the frequency, doubles the period
146 * 1111 500 milliseconds (maximum, 2 Hz)
147 * 0110 976.562 microseconds (default 1024 Hz)
149 save_control
= cmos_read(11); /* tell the clock it's being set */
150 cmos_write(11, (save_control
| 0x80));
151 save_freq_select
= cmos_read(10); /* stop and reset prescaler */
152 cmos_write(10, (save_freq_select
| 0x70));
158 if (!(save_control
& 0x02)) { /* 12hr mode; the default is 24hr mode */
161 if (tm
.tm_hour
> 12) {
167 if (!(save_control
& 0x04)) { /* BCD mode - the default */
168 BIN_TO_BCD(tm
.tm_sec
);
169 BIN_TO_BCD(tm
.tm_min
);
170 BIN_TO_BCD(tm
.tm_hour
);
171 BIN_TO_BCD(tm
.tm_wday
);
172 BIN_TO_BCD(tm
.tm_mday
);
173 BIN_TO_BCD(tm
.tm_mon
);
174 BIN_TO_BCD(tm
.tm_year
);
177 cmos_write(0, tm
.tm_sec
);
178 cmos_write(2, tm
.tm_min
);
179 cmos_write(4, tm
.tm_hour
| pmbit
);
180 cmos_write(6, tm
.tm_wday
);
181 cmos_write(7, tm
.tm_mday
);
182 cmos_write(8, tm
.tm_mon
);
183 cmos_write(9, tm
.tm_year
);
186 * The kernel sources, linux/arch/i386/kernel/time.c, have the
189 * The following flags have to be released exactly in this order,
190 * otherwise the DS12887 (popular MC146818A clone with integrated
191 * battery and quartz) will not reset the oscillator and will not
192 * update precisely 500 ms later. You won't find this mentioned in
193 * the Dallas Semiconductor data sheets, but who believes data
194 * sheets anyway ... -- Markus Kuhn
196 cmos_write(11, save_control
);
197 cmos_write(10, save_freq_select
);
201 static int hclock_read(unsigned long reg
)
203 return atomic(cmos_read
, reg
);
206 static void hclock_set_time(const struct tm
*tm
)
208 atomic(cmos_set_time
, (unsigned long)(tm
));
211 static inline int cmos_clock_busy(void)
214 /* poll bit 7 (UIP) of Control Register A */
215 (hclock_read(10) & 0x80);
218 static int synchronize_to_clock_tick_cmos(const struct hwclock_control
*ctl
219 __attribute__((__unused__
)))
224 * Wait for rise. Should be within a second, but in case something
225 * weird happens, we have a limit on this loop to reduce the impact
228 for (i
= 0; !cmos_clock_busy(); i
++)
232 /* Wait for fall. Should be within 2.228 ms. */
233 for (i
= 0; cmos_clock_busy(); i
++)
240 * Read the hardware clock and return the current time via <tm> argument.
241 * Assume we have an ISA machine and read the clock directly with CPU I/O
244 * This function is not totally reliable. It takes a finite and
245 * unpredictable amount of time to execute the code below. During that time,
246 * the clock may change and we may even read an invalid value in the middle
247 * of an update. We do a few checks to minimize this possibility, but only
248 * the kernel can actually read the clock properly, since it can execute
249 * code in a short and predictable amount of time (by turning of
252 * In practice, the chance of this function returning the wrong time is
255 static int read_hardware_clock_cmos(const struct hwclock_control
*ctl
256 __attribute__((__unused__
)), struct tm
*tm
)
258 unsigned char status
= 0, pmbit
= 0;
262 * Bit 7 of Byte 10 of the Hardware Clock value is the
263 * Update In Progress (UIP) bit, which is on while and 244
264 * uS before the Hardware Clock updates itself. It updates
265 * the counters individually, so reading them during an
266 * update would produce garbage. The update takes 2mS, so we
267 * could be spinning here that long waiting for this bit to
270 * Furthermore, it is pathologically possible for us to be
271 * in this code so long that even if the UIP bit is not on
272 * at first, the clock has changed while we were running. We
273 * check for that too, and if it happens, we start over.
275 if (!cmos_clock_busy()) {
276 /* No clock update in progress, go ahead and read */
277 tm
->tm_sec
= hclock_read(0);
278 tm
->tm_min
= hclock_read(2);
279 tm
->tm_hour
= hclock_read(4);
280 tm
->tm_wday
= hclock_read(6);
281 tm
->tm_mday
= hclock_read(7);
282 tm
->tm_mon
= hclock_read(8);
283 tm
->tm_year
= hclock_read(9);
284 status
= hclock_read(11);
286 * Unless the clock changed while we were reading,
287 * consider this a good clock read .
289 if (tm
->tm_sec
== hclock_read(0))
293 * Yes, in theory we could have been running for 60 seconds
294 * and the above test wouldn't work!
298 if (!(status
& 0x04)) { /* BCD mode - the default */
299 BCD_TO_BIN(tm
->tm_sec
);
300 BCD_TO_BIN(tm
->tm_min
);
301 pmbit
= (tm
->tm_hour
& 0x80);
303 BCD_TO_BIN(tm
->tm_hour
);
304 BCD_TO_BIN(tm
->tm_wday
);
305 BCD_TO_BIN(tm
->tm_mday
);
306 BCD_TO_BIN(tm
->tm_mon
);
307 BCD_TO_BIN(tm
->tm_year
);
311 * We don't use the century byte of the Hardware Clock since we
312 * don't know its address (usually 50 or 55). Here, we follow the
313 * advice of the X/Open Base Working Group: "if century is not
314 * specified, then values in the range [69-99] refer to years in the
315 * twentieth century (1969 to 1999 inclusive), and values in the
316 * range [00-68] refer to years in the twenty-first century (2000 to
321 if (tm
->tm_year
< 69)
325 if (tm
->tm_hour
== 24)
329 tm
->tm_isdst
= -1; /* don't know whether it's daylight */
333 static int set_hardware_clock_cmos(const struct hwclock_control
*ctl
334 __attribute__((__unused__
)),
335 const struct tm
*new_broken_time
)
337 hclock_set_time(new_broken_time
);
341 # if defined(HAVE_IOPL)
342 static int i386_iopl(const int level
)
347 static int i386_iopl(const int level
__attribute__ ((__unused__
)))
349 extern int ioperm(unsigned long from
, unsigned long num
, int turn_on
);
350 return ioperm(clock_ctl_addr
, 2, 1);
354 static int get_permissions_cmos(void)
359 if (rc
== IOPL_NOT_IMPLEMENTED
) {
360 warnx(_("ISA port access is not implemented"));
361 } else if (rc
!= 0) {
362 warn(_("iopl() port access failed"));
367 static const char *get_device_path(void)
372 static const struct clock_ops cmos_interface
= {
373 N_("Using direct ISA access to the clock"),
374 get_permissions_cmos
,
375 read_hardware_clock_cmos
,
376 set_hardware_clock_cmos
,
377 synchronize_to_clock_tick_cmos
,
382 * return &cmos if cmos clock present, NULL otherwise.
384 const struct clock_ops
*probe_for_cmos_clock(void)
386 return &cmos_interface
;