sys-utils/lscpu-arm.c

   1 /*
   2  * lscpu-arm.c - ARM CPU identification tables
   3  *
   4  * Copyright (C) 2018 Riku Voipio <riku.voipio@iki.fi>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it would be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * The information here is gathered from
  21  *  - ARM manuals
  22  *  - Linux kernel: arch/armX/include/asm/cputype.h
  23  *  - GCC sources: config/arch/arch-cores.def
  24  *  - Ancient wisdom
  25  *  - SMBIOS tables (if applicable)
  26  */
  27 #include "lscpu.h"
  28
  29 struct id_part {
  30     const int id;
  31     const char* name;
  32 };
  33
  34 static const struct id_part arm_part[] = {
  35     { 0x810, "ARM810" },
  36     { 0x920, "ARM920" },
  37     { 0x922, "ARM922" },
  38     { 0x926, "ARM926" },
  39     { 0x940, "ARM940" },
  40     { 0x946, "ARM946" },
  41     { 0x966, "ARM966" },
  42     { 0xa20, "ARM1020" },
  43     { 0xa22, "ARM1022" },
  44     { 0xa26, "ARM1026" },
  45     { 0xb02, "ARM11 MPCore" },
  46     { 0xb36, "ARM1136" },
  47     { 0xb56, "ARM1156" },
  48     { 0xb76, "ARM1176" },
  49     { 0xc05, "Cortex-A5" },
  50     { 0xc07, "Cortex-A7" },
  51     { 0xc08, "Cortex-A8" },
  52     { 0xc09, "Cortex-A9" },
  53     { 0xc0d, "Cortex-A17" },    /* Originally A12 */
  54     { 0xc0f, "Cortex-A15" },
  55     { 0xc0e, "Cortex-A17" },
  56     { 0xc14, "Cortex-R4" },
  57     { 0xc15, "Cortex-R5" },
  58     { 0xc17, "Cortex-R7" },
  59     { 0xc18, "Cortex-R8" },
  60     { 0xc20, "Cortex-M0" },
  61     { 0xc21, "Cortex-M1" },
  62     { 0xc23, "Cortex-M3" },
  63     { 0xc24, "Cortex-M4" },
  64     { 0xc27, "Cortex-M7" },
  65     { 0xc60, "Cortex-M0+" },
  66     { 0xd01, "Cortex-A32" },
  67     { 0xd03, "Cortex-A53" },
  68     { 0xd04, "Cortex-A35" },
  69     { 0xd05, "Cortex-A55" },
  70     { 0xd06, "Cortex-A65" },
  71     { 0xd07, "Cortex-A57" },
  72     { 0xd08, "Cortex-A72" },
  73     { 0xd09, "Cortex-A73" },
  74     { 0xd0a, "Cortex-A75" },
  75     { 0xd0b, "Cortex-A76" },
  76     { 0xd0c, "Neoverse-N1" },
  77     { 0xd0d, "Cortex-A77" },
  78     { 0xd0e, "Cortex-A76AE" },
  79     { 0xd13, "Cortex-R52" },
  80     { 0xd20, "Cortex-M23" },
  81     { 0xd21, "Cortex-M33" },
  82     { 0xd41, "Cortex-A78" },
  83     { 0xd42, "Cortex-A78AE" },
  84     { 0xd4a, "Neoverse-E1" },
  85     { 0xd4b, "Cortex-A78C" },
  86     { -1, "unknown" },
  87 };
  88
  89 static const struct id_part brcm_part[] = {
  90     { 0x0f, "Brahma B15" },
  91     { 0x100, "Brahma B53" },
  92     { 0x516, "ThunderX2" },
  93     { -1, "unknown" },
  94 };
  95
  96 static const struct id_part dec_part[] = {
  97     { 0xa10, "SA110" },
  98     { 0xa11, "SA1100" },
  99     { -1, "unknown" },
 100 };
 101
 102 static const struct id_part cavium_part[] = {
 103     { 0x0a0, "ThunderX" },
 104     { 0x0a1, "ThunderX 88XX" },
 105     { 0x0a2, "ThunderX 81XX" },
 106     { 0x0a3, "ThunderX 83XX" },
 107     { 0x0af, "ThunderX2 99xx" },
 108     { -1, "unknown" },
 109 };
 110
 111 static const struct id_part apm_part[] = {
 112     { 0x000, "X-Gene" },
 113     { -1, "unknown" },
 114 };
 115
 116 static const struct id_part qcom_part[] = {
 117     { 0x00f, "Scorpion" },
 118     { 0x02d, "Scorpion" },
 119     { 0x04d, "Krait" },
 120     { 0x06f, "Krait" },
 121     { 0x201, "Kryo" },
 122     { 0x205, "Kryo" },
 123     { 0x211, "Kryo" },
 124     { 0x800, "Falkor V1/Kryo" },
 125     { 0x801, "Kryo V2" },
 126     { 0xc00, "Falkor" },
 127     { 0xc01, "Saphira" },
 128     { -1, "unknown" },
 129 };
 130
 131 static const struct id_part samsung_part[] = {
 132     { 0x001, "exynos-m1" },
 133     { -1, "unknown" },
 134 };
 135
 136 static const struct id_part nvidia_part[] = {
 137     { 0x000, "Denver" },
 138     { 0x003, "Denver 2" },
 139     { 0x004, "Carmel" },
 140     { -1, "unknown" },
 141 };
 142
 143 static const struct id_part marvell_part[] = {
 144     { 0x131, "Feroceon 88FR131" },
 145     { 0x581, "PJ4/PJ4b" },
 146     { 0x584, "PJ4B-MP" },
 147     { -1, "unknown" },
 148 };
 149
 150 static const struct id_part faraday_part[] = {
 151     { 0x526, "FA526" },
 152     { 0x626, "FA626" },
 153     { -1, "unknown" },
 154 };
 155
 156 static const struct id_part intel_part[] = {
 157     { 0x200, "i80200" },
 158     { 0x210, "PXA250A" },
 159     { 0x212, "PXA210A" },
 160     { 0x242, "i80321-400" },
 161     { 0x243, "i80321-600" },
 162     { 0x290, "PXA250B/PXA26x" },
 163     { 0x292, "PXA210B" },
 164     { 0x2c2, "i80321-400-B0" },
 165     { 0x2c3, "i80321-600-B0" },
 166     { 0x2d0, "PXA250C/PXA255/PXA26x" },
 167     { 0x2d2, "PXA210C" },
 168     { 0x411, "PXA27x" },
 169     { 0x41c, "IPX425-533" },
 170     { 0x41d, "IPX425-400" },
 171     { 0x41f, "IPX425-266" },
 172     { 0x682, "PXA32x" },
 173     { 0x683, "PXA930/PXA935" },
 174     { 0x688, "PXA30x" },
 175     { 0x689, "PXA31x" },
 176     { 0xb11, "SA1110" },
 177     { 0xc12, "IPX1200" },
 178     { -1, "unknown" },
 179 };
 180
 181 static const struct id_part fujitsu_part[] = {
 182     { 0x001, "A64FX" },
 183     { -1, "unknown" },
 184 };
 185
 186 static const struct id_part hisi_part[] = {
 187     { 0xd01, "Kunpeng-920" },   /* aka tsv110 */
 188     { -1, "unknown" },
 189 };
 190
 191 static const struct id_part unknown_part[] = {
 192     { -1, "unknown" },
 193 };
 194
 195 struct hw_impl {
 196    const int    id;
 197    const struct id_part     *parts;
 198    const char   *name;
 199 };
 200
 201 static const struct hw_impl hw_implementer[] = {
 202     { 0x41, arm_part,     "ARM" },
 203     { 0x42, brcm_part,    "Broadcom" },
 204     { 0x43, cavium_part,  "Cavium" },
 205     { 0x44, dec_part,     "DEC" },
 206     { 0x46, fujitsu_part, "FUJITSU" },
 207     { 0x48, hisi_part,    "HiSilicon" },
 208     { 0x49, unknown_part, "Infineon" },
 209     { 0x4d, unknown_part, "Motorola/Freescale" },
 210     { 0x4e, nvidia_part,  "NVIDIA" },
 211     { 0x50, apm_part,     "APM" },
 212     { 0x51, qcom_part,    "Qualcomm" },
 213     { 0x53, samsung_part, "Samsung" },
 214     { 0x56, marvell_part, "Marvell" },
 215     { 0x61, unknown_part, "Apple" },
 216     { 0x66, faraday_part, "Faraday" },
 217     { 0x69, intel_part,   "Intel" },
 218     { 0xc0, unknown_part, "Ampere" },
 219     { -1,   unknown_part, "unknown" },
 220 };
 221
 222 static int parse_id(const char *str)
 223 {
 224         int id;
 225         char *end = NULL;
 226
 227         if (!str || strncmp(str, "0x",2) != 0)
 228                 return -EINVAL;
 229
 230         errno = 0;
 231         id = (int) strtol(str, &end, 0);
 232         if (errno || str == end)
 233                 return -EINVAL;
 234
 235         return id;
 236 }
 237
 238 #define parse_model_id(_cxt)            (parse_id((_cxt)->model))
 239
 240 static inline int parse_implementer_id(struct lscpu_cputype *ct)
 241 {
 242         if (ct->vendor_id)
 243                 return ct->vendor_id;
 244         ct->vendor_id = parse_id(ct->vendor);
 245         return ct->vendor_id;
 246 }
 247
 248 /*
 249  * Use model and vendor IDs to decode to human readable names.
 250  */
 251 static int arm_ids_decode(struct lscpu_cputype *ct)
 252 {
 253         int impl, part, j;
 254         const struct id_part *parts = NULL;
 255
 256         impl = parse_implementer_id(ct);
 257         if (impl <= 0)
 258                 return -EINVAL; /* no ARM or missing ID */
 259
 260         /* decode vendor */
 261         for (j = 0; hw_implementer[j].id != -1; j++) {
 262                 if (hw_implementer[j].id == impl) {
 263                         parts = hw_implementer[j].parts;
 264                         free(ct->vendor);
 265                         ct->vendor = xstrdup(hw_implementer[j].name);
 266                         break;
 267                 }
 268         }
 269
 270         /* decode model */
 271         if (!parts)
 272                 goto done;
 273
 274         part = parse_model_id(ct);
 275         if (part <= 0)
 276                 goto done;
 277
 278         for (j = 0; parts[j].id != -1; j++) {
 279                 if (parts[j].id == part) {
 280                         free(ct->modelname);
 281                         ct->modelname = xstrdup(parts[j].name);
 282                         break;
 283                 }
 284         }
 285 done:
 286         return 0;
 287 }
 288
 289 /* use "rXpY" string as stepping */
 290 static int arm_rXpY_decode(struct lscpu_cputype *ct)
 291 {
 292         int impl, revision, variant;
 293         char *end = NULL;
 294         char buf[8];
 295
 296         impl = parse_implementer_id(ct);
 297
 298         if (impl != 0x41 || !ct->revision || !ct->stepping)
 299                 return -EINVAL;
 300
 301         errno = 0;
 302         revision = (int) strtol(ct->revision, &end, 10);
 303         if (errno || ct->revision == end)
 304                 return -EINVAL;
 305
 306         errno = 0;
 307         variant = (int) strtol(ct->stepping, &end, 0);
 308         if (errno || ct->stepping == end)
 309                 return -EINVAL;
 310
 311         snprintf(buf, sizeof(buf), "r%dp%d", variant, revision);
 312         free(ct->stepping);
 313         ct->stepping = xstrdup(buf);
 314
 315         return 0;
 316 }
 317
 318 static void arm_decode(struct lscpu_cxt *cxt, struct lscpu_cputype *ct)
 319 {
 320         if (!cxt->noalive && access(_PATH_SYS_DMI, R_OK) == 0)
 321                 dmi_decode_cputype(ct);
 322
 323         arm_ids_decode(ct);
 324         arm_rXpY_decode(ct);
 325         if (cxt->is_cluster)
 326                 ct->nr_socket_on_cluster = get_number_of_physical_sockets_from_dmi();
 327 }
 328
 329 static int is_cluster_arm(struct lscpu_cxt *cxt)
 330 {
 331         struct stat st;
 332
 333         if (!(strcmp(cxt->arch->name, "aarch64")) &&
 334              (stat(_PATH_ACPI_PPTT, &st) < 0) && (cxt->ncputypes == 1))
 335                 return 1;
 336         else
 337                 return 0;
 338 }
 339
 340 void lscpu_decode_arm(struct lscpu_cxt *cxt)
 341 {
 342         size_t i;
 343
 344         cxt->is_cluster = is_cluster_arm(cxt);
 345
 346         for (i = 0; i < cxt->ncputypes; i++)
 347                 arm_decode(cxt, cxt->cputypes[i]);
 348 }