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git.ipfire.org Git - thirdparty/util-linux.git/blob - sys-utils/lscpu-arm.c
2 * lscpu-arm.c - ARM CPU identification tables
4 * Copyright (C) 2018 Riku Voipio <riku.voipio@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it would be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 * The information here is gathered from
22 * - Linux kernel: arch/armX/include/asm/cputype.h
23 * - GCC sources: config/arch/arch-cores.def
25 * - SMBIOS tables (if applicable)
34 static const struct id_part arm_part
[] = {
45 { 0xb02, "ARM11 MPCore" },
49 { 0xc05, "Cortex-A5" },
50 { 0xc07, "Cortex-A7" },
51 { 0xc08, "Cortex-A8" },
52 { 0xc09, "Cortex-A9" },
53 { 0xc0d, "Cortex-A17" }, /* Originally A12 */
54 { 0xc0f, "Cortex-A15" },
55 { 0xc0e, "Cortex-A17" },
56 { 0xc14, "Cortex-R4" },
57 { 0xc15, "Cortex-R5" },
58 { 0xc17, "Cortex-R7" },
59 { 0xc18, "Cortex-R8" },
60 { 0xc20, "Cortex-M0" },
61 { 0xc21, "Cortex-M1" },
62 { 0xc23, "Cortex-M3" },
63 { 0xc24, "Cortex-M4" },
64 { 0xc27, "Cortex-M7" },
65 { 0xc60, "Cortex-M0+" },
66 { 0xd01, "Cortex-A32" },
67 { 0xd02, "Cortex-A34" },
68 { 0xd03, "Cortex-A53" },
69 { 0xd04, "Cortex-A35" },
70 { 0xd05, "Cortex-A55" },
71 { 0xd06, "Cortex-A65" },
72 { 0xd07, "Cortex-A57" },
73 { 0xd08, "Cortex-A72" },
74 { 0xd09, "Cortex-A73" },
75 { 0xd0a, "Cortex-A75" },
76 { 0xd0b, "Cortex-A76" },
77 { 0xd0c, "Neoverse-N1" },
78 { 0xd0d, "Cortex-A77" },
79 { 0xd0e, "Cortex-A76AE" },
80 { 0xd13, "Cortex-R52" },
81 { 0xd15, "Cortex-R82" },
82 { 0xd16, "Cortex-R52+" },
83 { 0xd20, "Cortex-M23" },
84 { 0xd21, "Cortex-M33" },
85 { 0xd22, "Cortex-M55" },
86 { 0xd23, "Cortex-M85" },
87 { 0xd40, "Neoverse-V1" },
88 { 0xd41, "Cortex-A78" },
89 { 0xd42, "Cortex-A78AE" },
90 { 0xd43, "Cortex-A65AE" },
91 { 0xd44, "Cortex-X1" },
92 { 0xd46, "Cortex-A510" },
93 { 0xd47, "Cortex-A710" },
94 { 0xd48, "Cortex-X2" },
95 { 0xd49, "Neoverse-N2" },
96 { 0xd4a, "Neoverse-E1" },
97 { 0xd4b, "Cortex-A78C" },
98 { 0xd4c, "Cortex-X1C" },
99 { 0xd4d, "Cortex-A715" },
100 { 0xd4e, "Cortex-X3" },
101 { 0xd4f, "Neoverse-V2" },
102 { 0xd80, "Cortex-A520" },
103 { 0xd81, "Cortex-A720" },
104 { 0xd82, "Cortex-X4" },
108 static const struct id_part brcm_part
[] = {
109 { 0x0f, "Brahma-B15" },
110 { 0x100, "Brahma-B53" },
111 { 0x516, "ThunderX2" },
115 static const struct id_part dec_part
[] = {
121 static const struct id_part cavium_part
[] = {
122 { 0x0a0, "ThunderX" },
123 { 0x0a1, "ThunderX-88XX" },
124 { 0x0a2, "ThunderX-81XX" },
125 { 0x0a3, "ThunderX-83XX" },
126 { 0x0af, "ThunderX2-99xx" },
127 { 0x0b0, "OcteonTX2" },
128 { 0x0b1, "OcteonTX2-98XX" },
129 { 0x0b2, "OcteonTX2-96XX" },
130 { 0x0b3, "OcteonTX2-95XX" },
131 { 0x0b4, "OcteonTX2-95XXN" },
132 { 0x0b5, "OcteonTX2-95XXMM" },
133 { 0x0b6, "OcteonTX2-95XXO" },
134 { 0x0b8, "ThunderX3-T110" },
138 static const struct id_part apm_part
[] = {
143 static const struct id_part qcom_part
[] = {
144 { 0x00f, "Scorpion" },
145 { 0x02d, "Scorpion" },
151 { 0x800, "Falkor-V1/Kryo" },
152 { 0x801, "Kryo-V2" },
153 { 0x802, "Kryo-3XX-Gold" },
154 { 0x803, "Kryo-3XX-Silver" },
155 { 0x804, "Kryo-4XX-Gold" },
156 { 0x805, "Kryo-4XX-Silver" },
158 { 0xc01, "Saphira" },
162 static const struct id_part samsung_part
[] = {
163 { 0x001, "exynos-m1" },
164 { 0x002, "exynos-m3" },
165 { 0x003, "exynos-m4" },
166 { 0x004, "exynos-m5" },
170 static const struct id_part nvidia_part
[] = {
172 { 0x003, "Denver 2" },
177 static const struct id_part marvell_part
[] = {
178 { 0x131, "Feroceon-88FR131" },
179 { 0x581, "PJ4/PJ4b" },
180 { 0x584, "PJ4B-MP" },
184 static const struct id_part apple_part
[] = {
186 { 0x001, "Cyclone" },
187 { 0x002, "Typhoon" },
188 { 0x003, "Typhoon/Capri" },
189 { 0x004, "Twister" },
190 { 0x005, "Twister/Elba/Malta" },
191 { 0x006, "Hurricane" },
192 { 0x007, "Hurricane/Myst" },
193 { 0x008, "Monsoon" },
194 { 0x009, "Mistral" },
196 { 0x00c, "Tempest" },
197 { 0x00f, "Tempest-M9" },
198 { 0x010, "Vortex/Aruba" },
199 { 0x011, "Tempest/Aruba" },
200 { 0x012, "Lightning" },
201 { 0x013, "Thunder" },
202 { 0x020, "Icestorm-A14" },
203 { 0x021, "Firestorm-A14" },
204 { 0x022, "Icestorm-M1" },
205 { 0x023, "Firestorm-M1" },
206 { 0x024, "Icestorm-M1-Pro" },
207 { 0x025, "Firestorm-M1-Pro" },
208 { 0x026, "Thunder-M10" },
209 { 0x028, "Icestorm-M1-Max" },
210 { 0x029, "Firestorm-M1-Max" },
211 { 0x030, "Blizzard-A15" },
212 { 0x031, "Avalanche-A15" },
213 { 0x032, "Blizzard-M2" },
214 { 0x033, "Avalanche-M2" },
215 { 0x034, "Blizzard-M2-Pro" },
216 { 0x035, "Avalanche-M2-Pro" },
217 { 0x036, "Sawtooth-A16" },
218 { 0x037, "Everest-A16" },
219 { 0x038, "Blizzard-M2-Max" },
220 { 0x039, "Avalanche-M2-Max" },
224 static const struct id_part faraday_part
[] = {
230 static const struct id_part intel_part
[] = {
232 { 0x210, "PXA250A" },
233 { 0x212, "PXA210A" },
234 { 0x242, "i80321-400" },
235 { 0x243, "i80321-600" },
236 { 0x290, "PXA250B/PXA26x" },
237 { 0x292, "PXA210B" },
238 { 0x2c2, "i80321-400-B0" },
239 { 0x2c3, "i80321-600-B0" },
240 { 0x2d0, "PXA250C/PXA255/PXA26x" },
241 { 0x2d2, "PXA210C" },
243 { 0x41c, "IPX425-533" },
244 { 0x41d, "IPX425-400" },
245 { 0x41f, "IPX425-266" },
247 { 0x683, "PXA930/PXA935" },
251 { 0xc12, "IPX1200" },
255 static const struct id_part fujitsu_part
[] = {
260 static const struct id_part hisi_part
[] = {
261 { 0xd01, "TaiShan-v110" }, /* used in Kunpeng-920 SoC */
262 { 0xd02, "TaiShan-v120" }, /* used in Kirin 990A and 9000S SoCs */
263 { 0xd40, "Cortex-A76" }, /* HiSilicon uses this ID though advertises A76 */
264 { 0xd41, "Cortex-A77" }, /* HiSilicon uses this ID though advertises A77 */
268 static const struct id_part ampere_part
[] = {
269 { 0xac3, "Ampere-1" },
270 { 0xac4, "Ampere-1a" },
274 static const struct id_part ft_part
[] = {
285 static const struct id_part unknown_part
[] = {
291 const struct id_part
*parts
;
295 static const struct hw_impl hw_implementer
[] = {
296 { 0x41, arm_part
, "ARM" },
297 { 0x42, brcm_part
, "Broadcom" },
298 { 0x43, cavium_part
, "Cavium" },
299 { 0x44, dec_part
, "DEC" },
300 { 0x46, fujitsu_part
, "FUJITSU" },
301 { 0x48, hisi_part
, "HiSilicon" },
302 { 0x49, unknown_part
, "Infineon" },
303 { 0x4d, unknown_part
, "Motorola/Freescale" },
304 { 0x4e, nvidia_part
, "NVIDIA" },
305 { 0x50, apm_part
, "APM" },
306 { 0x51, qcom_part
, "Qualcomm" },
307 { 0x53, samsung_part
, "Samsung" },
308 { 0x56, marvell_part
, "Marvell" },
309 { 0x61, apple_part
, "Apple" },
310 { 0x66, faraday_part
, "Faraday" },
311 { 0x69, intel_part
, "Intel" },
312 { 0x70, ft_part
, "Phytium" },
313 { 0xc0, ampere_part
, "Ampere" },
314 { -1, unknown_part
, "unknown" },
317 static int parse_id(const char *str
)
322 if (!str
|| strncmp(str
, "0x",2) != 0)
326 id
= (int) strtol(str
, &end
, 0);
327 if (errno
|| str
== end
)
333 #define parse_model_id(_cxt) (parse_id((_cxt)->model))
335 static inline int parse_implementer_id(struct lscpu_cputype
*ct
)
338 return ct
->vendor_id
;
339 ct
->vendor_id
= parse_id(ct
->vendor
);
340 return ct
->vendor_id
;
344 * Use model and vendor IDs to decode to human readable names.
346 static int arm_ids_decode(struct lscpu_cputype
*ct
)
349 const struct id_part
*parts
= NULL
;
351 impl
= parse_implementer_id(ct
);
353 return -EINVAL
; /* no ARM or missing ID */
356 for (j
= 0; hw_implementer
[j
].id
!= -1; j
++) {
357 if (hw_implementer
[j
].id
== impl
) {
358 parts
= hw_implementer
[j
].parts
;
360 ct
->vendor
= xstrdup(hw_implementer
[j
].name
);
369 part
= parse_model_id(ct
);
373 for (j
= 0; parts
[j
].id
!= -1; j
++) {
374 if (parts
[j
].id
== part
) {
376 ct
->modelname
= xstrdup(parts
[j
].name
);
384 /* use "rXpY" string as stepping */
385 static int arm_rXpY_decode(struct lscpu_cputype
*ct
)
387 int impl
, revision
, variant
;
391 impl
= parse_implementer_id(ct
);
393 if (impl
!= 0x41 || !ct
->revision
|| !ct
->stepping
)
397 revision
= (int) strtol(ct
->revision
, &end
, 10);
398 if (errno
|| ct
->revision
== end
)
402 variant
= (int) strtol(ct
->stepping
, &end
, 0);
403 if (errno
|| ct
->stepping
== end
)
406 snprintf(buf
, sizeof(buf
), "r%dp%d", variant
, revision
);
408 ct
->stepping
= xstrdup(buf
);
413 static void arm_decode(struct lscpu_cxt
*cxt
, struct lscpu_cputype
*ct
)
415 if (!cxt
->noalive
&& access(_PATH_SYS_DMI
, R_OK
) == 0)
416 dmi_decode_cputype(ct
);
421 if (!cxt
->noalive
&& cxt
->is_cluster
)
422 ct
->nr_socket_on_cluster
= get_number_of_physical_sockets_from_dmi();
425 static int is_cluster_arm(struct lscpu_cxt
*cxt
)
430 && strcmp(cxt
->arch
->name
, "aarch64") == 0
431 && stat(_PATH_ACPI_PPTT
, &st
) < 0 && cxt
->ncputypes
== 1)
437 void lscpu_decode_arm(struct lscpu_cxt
*cxt
)
441 cxt
->is_cluster
= is_cluster_arm(cxt
);
443 for (i
= 0; i
< cxt
->ncputypes
; i
++)
444 arm_decode(cxt
, cxt
->cputypes
[i
]);