+ /* Fields for various kinds of instructions. */
+ unsigned int b2, r1, r2, x2, r3;
+ int i2, d2;
+
+ /* The values of SP and FP before this instruction,
+ for detecting instructions that change them. */
+ pv_t pre_insn_sp, pre_insn_fp;
+ /* Likewise for the flag whether the back chain was saved. */
+ int pre_insn_back_chain_saved_p;
+
+ /* If we got an error trying to read the instruction, report it. */
+ if (insn_len < 0)
+ {
+ result = 0;
+ break;
+ }
+
+ next_pc = pc + insn_len;
+
+ pre_insn_sp = data->gpr[S390_SP_REGNUM - S390_R0_REGNUM];
+ pre_insn_fp = data->gpr[S390_FRAME_REGNUM - S390_R0_REGNUM];
+ pre_insn_back_chain_saved_p = data->back_chain_saved_p;
+
+
+ /* LHI r1, i2 --- load halfword immediate. */
+ /* LGHI r1, i2 --- load halfword immediate (64-bit version). */
+ /* LGFI r1, i2 --- load fullword immediate. */
+ if (is_ri (insn32, op1_lhi, op2_lhi, &r1, &i2)
+ || is_ri (insn64, op1_lghi, op2_lghi, &r1, &i2)
+ || is_ril (insn, op1_lgfi, op2_lgfi, &r1, &i2))
+ data->gpr[r1] = pv_constant (i2);
+
+ /* LR r1, r2 --- load from register. */
+ /* LGR r1, r2 --- load from register (64-bit version). */
+ else if (is_rr (insn32, op_lr, &r1, &r2)
+ || is_rre (insn64, op_lgr, &r1, &r2))
+ data->gpr[r1] = data->gpr[r2];
+
+ /* L r1, d2(x2, b2) --- load. */
+ /* LY r1, d2(x2, b2) --- load (long-displacement version). */
+ /* LG r1, d2(x2, b2) --- load (64-bit version). */
+ else if (is_rx (insn32, op_l, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_ly, op2_ly, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_lg, op2_lg, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = s390_load (data, d2, x2, b2, data->gpr_size);
+
+ /* ST r1, d2(x2, b2) --- store. */
+ /* STY r1, d2(x2, b2) --- store (long-displacement version). */
+ /* STG r1, d2(x2, b2) --- store (64-bit version). */
+ else if (is_rx (insn32, op_st, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_sty, op2_sty, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_stg, op2_stg, &r1, &d2, &x2, &b2))
+ s390_store (data, d2, x2, b2, data->gpr_size, data->gpr[r1]);
+
+ /* STD r1, d2(x2,b2) --- store floating-point register. */
+ else if (is_rx (insn, op_std, &r1, &d2, &x2, &b2))
+ s390_store (data, d2, x2, b2, data->fpr_size, data->fpr[r1]);
+
+ /* STM r1, r3, d2(b2) --- store multiple. */
+ /* STMY r1, r3, d2(b2) --- store multiple (long-displacement version). */
+ /* STMG r1, r3, d2(b2) --- store multiple (64-bit version). */
+ else if (is_rs (insn32, op_stm, &r1, &r3, &d2, &b2)
+ || is_rsy (insn32, op1_stmy, op2_stmy, &r1, &r3, &d2, &b2)
+ || is_rsy (insn64, op1_stmg, op2_stmg, &r1, &r3, &d2, &b2))
+ {
+ for (; r1 <= r3; r1++, d2 += data->gpr_size)
+ s390_store (data, d2, 0, b2, data->gpr_size, data->gpr[r1]);
+ }
+
+ /* AHI r1, i2 --- add halfword immediate. */
+ /* AGHI r1, i2 --- add halfword immediate (64-bit version). */
+ /* AFI r1, i2 --- add fullword immediate. */
+ /* AGFI r1, i2 --- add fullword immediate (64-bit version). */
+ else if (is_ri (insn32, op1_ahi, op2_ahi, &r1, &i2)
+ || is_ri (insn64, op1_aghi, op2_aghi, &r1, &i2)
+ || is_ril (insn32, op1_afi, op2_afi, &r1, &i2)
+ || is_ril (insn64, op1_agfi, op2_agfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1], i2);
+
+ /* ALFI r1, i2 --- add logical immediate. */
+ /* ALGFI r1, i2 --- add logical immediate (64-bit version). */
+ else if (is_ril (insn32, op1_alfi, op2_alfi, &r1, &i2)
+ || is_ril (insn64, op1_algfi, op2_algfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1],
+ (CORE_ADDR)i2 & 0xffffffff);
+
+ /* AR r1, r2 -- add register. */
+ /* AGR r1, r2 -- add register (64-bit version). */
+ else if (is_rr (insn32, op_ar, &r1, &r2)
+ || is_rre (insn64, op_agr, &r1, &r2))
+ data->gpr[r1] = pv_add (data->gpr[r1], data->gpr[r2]);
+
+ /* A r1, d2(x2, b2) -- add. */
+ /* AY r1, d2(x2, b2) -- add (long-displacement version). */
+ /* AG r1, d2(x2, b2) -- add (64-bit version). */
+ else if (is_rx (insn32, op_a, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_ay, op2_ay, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_ag, op2_ag, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = pv_add (data->gpr[r1],
+ s390_load (data, d2, x2, b2, data->gpr_size));
+
+ /* SLFI r1, i2 --- subtract logical immediate. */
+ /* SLGFI r1, i2 --- subtract logical immediate (64-bit version). */
+ else if (is_ril (insn32, op1_slfi, op2_slfi, &r1, &i2)
+ || is_ril (insn64, op1_slgfi, op2_slgfi, &r1, &i2))
+ data->gpr[r1] = pv_add_constant (data->gpr[r1],
+ -((CORE_ADDR)i2 & 0xffffffff));
+
+ /* SR r1, r2 -- subtract register. */
+ /* SGR r1, r2 -- subtract register (64-bit version). */
+ else if (is_rr (insn32, op_sr, &r1, &r2)
+ || is_rre (insn64, op_sgr, &r1, &r2))
+ data->gpr[r1] = pv_subtract (data->gpr[r1], data->gpr[r2]);
+
+ /* S r1, d2(x2, b2) -- subtract. */
+ /* SY r1, d2(x2, b2) -- subtract (long-displacement version). */
+ /* SG r1, d2(x2, b2) -- subtract (64-bit version). */
+ else if (is_rx (insn32, op_s, &r1, &d2, &x2, &b2)
+ || is_rxy (insn32, op1_sy, op2_sy, &r1, &d2, &x2, &b2)
+ || is_rxy (insn64, op1_sg, op2_sg, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = pv_subtract (data->gpr[r1],
+ s390_load (data, d2, x2, b2, data->gpr_size));
+
+ /* LA r1, d2(x2, b2) --- load address. */
+ /* LAY r1, d2(x2, b2) --- load address (long-displacement version). */
+ else if (is_rx (insn, op_la, &r1, &d2, &x2, &b2)
+ || is_rxy (insn, op1_lay, op2_lay, &r1, &d2, &x2, &b2))
+ data->gpr[r1] = s390_addr (data, d2, x2, b2);
+
+ /* LARL r1, i2 --- load address relative long. */
+ else if (is_ril (insn, op1_larl, op2_larl, &r1, &i2))
+ data->gpr[r1] = pv_constant (pc + i2 * 2);
+
+ /* BASR r1, 0 --- branch and save.
+ Since r2 is zero, this saves the PC in r1, but doesn't branch. */
+ else if (is_rr (insn, op_basr, &r1, &r2)
+ && r2 == 0)
+ data->gpr[r1] = pv_constant (next_pc);
+
+ /* BRAS r1, i2 --- branch relative and save. */
+ else if (is_ri (insn, op1_bras, op2_bras, &r1, &i2))
+ {
+ data->gpr[r1] = pv_constant (next_pc);
+ next_pc = pc + i2 * 2;
+
+ /* We'd better not interpret any backward branches. We'll
+ never terminate. */
+ if (next_pc <= pc)
+ break;
+ }
+
+ /* Terminate search when hitting any other branch instruction. */
+ else if (is_rr (insn, op_basr, &r1, &r2)
+ || is_rx (insn, op_bas, &r1, &d2, &x2, &b2)
+ || is_rr (insn, op_bcr, &r1, &r2)
+ || is_rx (insn, op_bc, &r1, &d2, &x2, &b2)
+ || is_ri (insn, op1_brc, op2_brc, &r1, &i2)
+ || is_ril (insn, op1_brcl, op2_brcl, &r1, &i2)
+ || is_ril (insn, op1_brasl, op2_brasl, &r2, &i2))
+ break;
+
+ else
+ /* An instruction we don't know how to simulate. The only
+ safe thing to do would be to set every value we're tracking
+ to 'unknown'. Instead, we'll be optimistic: we assume that
+ we *can* interpret every instruction that the compiler uses
+ to manipulate any of the data we're interested in here --
+ then we can just ignore anything else. */
+ ;
+
+ /* Record the address after the last instruction that changed
+ the FP, SP, or backlink. Ignore instructions that changed
+ them back to their original values --- those are probably
+ restore instructions. (The back chain is never restored,
+ just popped.) */
+ {
+ pv_t sp = data->gpr[S390_SP_REGNUM - S390_R0_REGNUM];
+ pv_t fp = data->gpr[S390_FRAME_REGNUM - S390_R0_REGNUM];
+
+ if ((! pv_is_identical (pre_insn_sp, sp)
+ && ! pv_is_register_k (sp, S390_SP_REGNUM, 0)
+ && sp.kind != pvk_unknown)
+ || (! pv_is_identical (pre_insn_fp, fp)
+ && ! pv_is_register_k (fp, S390_FRAME_REGNUM, 0)
+ && fp.kind != pvk_unknown)
+ || pre_insn_back_chain_saved_p != data->back_chain_saved_p)
+ result = next_pc;
+ }
+ }
+
+ /* Record where all the registers were saved. */
+ pv_area_scan (data->stack, s390_check_for_saved, data);
+
+ free_pv_area (data->stack);
+ data->stack = NULL;
+
+ return result;
+}
+
+/* Advance PC across any function entry prologue instructions to reach
+ some "real" code. */
+static CORE_ADDR
+s390_skip_prologue (CORE_ADDR pc)
+{
+ struct s390_prologue_data data;
+ CORE_ADDR skip_pc;
+ skip_pc = s390_analyze_prologue (current_gdbarch, pc, (CORE_ADDR)-1, &data);
+ return skip_pc ? skip_pc : pc;
+}
+
+/* Return true if we are in the functin's epilogue, i.e. after the
+ instruction that destroyed the function's stack frame. */
+static int
+s390_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)