+2020-10-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (load_insn_p): Check opcodeprefix == 0 for
+ base_opcode == 0xfc7.
+ (match_template): Likewise.
+ (process_suffix): Check opcodeprefix == PREFIX_0XF2 for CRC32.
+ (check_byte_reg): Likewise.
+ (output_insn): Don't add the 0xf3 prefix twice for PadLock
+ instructions. Don't add prefix from non-VEX/EVEX base_opcode.
+
+2020-10-13 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_vex_prefix): Replace vexopcode with
+ opcodeprefix.
+ (build_evex_prefix): Likewise.
+ (is_any_vex_encoding): Don't check vexopcode.
+ (output_insn): Handle opcodeprefix.
+
+2020-10-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26703
+ * config/tc-i386.c (xstate): Add xstate_mask.
+ (md_assemble): Check i.types[j], instead of i.tm.operand_types[j],
+ for xstate. Set xstate_mask, instead of xstate_zmm, for RegMask.
+ (output_insn): Update for GNU_PROPERTY_X86_ISA_1_V[234]. Update
+ xstate for mask register and VSIB.
+ * testsuite/gas/i386/i386.exp: Run more GNU_PROPERTY tests.
+ * testsuite/gas/i386/property-1.s: Updated to the current
+ GNU_PROPERTY_X86_ISA_1_USED value.
+ * testsuite/gas/i386/property-2.s: Only keep cmove.
+ * testsuite/gas/i386/property-3.s: Changed to addsubpd.
+ * testsuite/gas/i386/property-1.d: Updated.
+ * testsuite/gas/i386/property-2.d: Likewise.
+ * testsuite/gas/i386/property-3.d: Likewise.
+ * testsuite/gas/i386/property-4.d: Likewise.
+ * testsuite/gas/i386/property-5.d: Likewise.
+ * testsuite/gas/i386/property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-1.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-2.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-3.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-4.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-5.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-6.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-7.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-8.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-9.d: Likewise.
+ * testsuite/gas/i386/property-11.d: New file.
+ * testsuite/gas/i386/property-11.s: Likewise.
+ * testsuite/gas/i386/property-12.d: Likewise.
+ * testsuite/gas/i386/property-12.s: Likewise.
+ * testsuite/gas/i386/property-13.d: Likewise.
+ * testsuite/gas/i386/property-13.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-11.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-12.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-13.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.d: Likewise.
+ * testsuite/gas/i386/x86-64-property-14.s: Likewise.
+
+2020-10-06 Alex Coplan <alex.coplan@arm.com>
+
+ PR 26699
+ * config/tc-aarch64.c (asm_barrier_opt): Delete.
+ (parse_barrier): Fix bogus type punning.
+ * testsuite/gas/aarch64/system.d: Update disassembly.
+ * testsuite/gas/aarch64/system.s: Add isb sy test.
+
+2020-10-06 Sergey Belyashav <sergey.belyashov@gmail.com>
+
+ PR 26692
+ * config/tc-z80.c (md_begin): Ensure that xpressions are empty
+ before using them.
+ (unify_indexed): Likewise.
+ (z80_start_line_hook): Improve hash sign handling when SDCC
+ compatibility mode enabled.
+ (md_parse_exp_not_indexed): Improve indirect addressing
+ detection.
+ (md_pseudo_table): Accept hd64 as an alias of z810.
+
+2020-10-06 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/elf/sh-link-zero.s: Don't start directives in
+ first column. Don't use numeric labels.
+
+2020-10-05 Kamil Rytarowski <n54@gmx.com>
+
+ * configure.tgt (aarch64*-*-netbsd*): Add target.
+
+2020-10-05 Samanta Navarro <ferivoz@riseup.net>
+
+ * doc/as.texi: Fix spelling mistakes.
+ * doc/c-wasm32.texi: Likewise.
+
+2020-10-05 T.K. Chia <u1049321969@caramail.com>
+
+ PR gas/26694
+ * NEWS: Updated for i386 lcall and ljmp change.
+ * config/tc-i386.c (output_interseg_jump): Allow non-absolute
+ segment operand for immediate lcall and ljmp.
+ * testsuite/gas/i386/jump.d,
+ * testsuite/gas/i386/jump.s,
+ * testsuite/gas/i386/jump16.d,
+ * testsuite/gas/i386/jump16.e,
+ * testsuite/gas/i386/jump16.s: Add tests for non-absolute
+ segment operand for immediate ljmp.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26704
+ * testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
+ sysret.
+ * testsuite/gas/i386/noreg64.d: Likewise.
+ * testsuite/gas/i386/x86-64-intel64.d: Likewise.
+ * testsuite/gas/i386/x86-64-opcode.d: Likewise.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26705
+ * testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
+ sysretq.
+ * testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-suffix.d: Likewise.
+
+2020-10-05 Nick Clifton <nickc@redhat.com>
+
+ PR 26253
+ * config/obj-elf.c (obj_elf_section): Accept a numeric value for
+ the "o" section flag. Interpret it as a section index. Allow an
+ index of zero.
+ * doc/as.texi: Document the new behaviour.
+ * NEWS: Mention the new feature. Tidy entries.
+ * testsuite/gas/elf/sh-link-zero.s: New test.
+ * testsuite/gas/elf/sh-link-zero.d: New test driver.
+ * testsuite/gas/elf/elf.exp: Run the new test.
+ * testsuite/gas/elf/section21.l: Updated expected assembler
+ output.
+
+2020-10-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26685
+ * config/tc-i386.c (process_suffix): Also check the register
+ operand for the address size prefix if the memory operand has
+ no real registers.
+ * testsuite/gas/i386/enqcmd-16bit.d: New file.
+ * testsuite/gas/i386/enqcmd-16bit.s: Likewise.
+ * testsuite/gas/i386/movdir-16bit.d: Likewise.
+ * testsuite/gas/i386/movdir-16bit.s: Likewise.
+ * testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP.
+ * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.s: Likewise.
+ * testsuite/gas/i386/movdir.s: Add tests with symbol and DISP.
+ Remove the .code16 test.
+ * testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+ * testsuite/gas/i386/enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/enqcmd.d: Likewise.
+ * testsuite/gas/i386/movdir-intel.d: Likewise.
+ * testsuite/gas/i386/movdir.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+
+2020-10-02 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/arm/mve-vcvtne-it.d: Allow for padding inserted by
+ PE based targets.
+
+2020-10-01 Nick Clifton <nickc@redhat.com>
+
+ * config/obj-elf (elf_pseudo_table): Add attach_to_group.
+ (obj_elf_attach_to_group): New function.
+ * doc/as.texi: Document the new directive.
+ * NEWS: Mention the new feature.
+ * testsuite/gas/elf/attach-1.s: New test.
+ * testsuite/gas/elf/attach-1.d: New test driver.
+ * testsuite/gas/elf/attach-2.s: New test.
+ * testsuite/gas/elf/attach-2.d: New test driver.
+ * testsuite/gas/elf/attach-err.s: New test.
+ * testsuite/gas/elf/attach-err.d: New test driver.
+ * testsuite/gas/elf/attach-err.err: New test error output.
+ * testsuite/gas/elf/elf.exp: Run the new tests.
+
+2020-09-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26685
+ * config/tc-i386.c (process_suffix): Check the register operand
+ for the address size prefix if the memory operand is symbol(%rip).
+ * testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative
+ addressing.
+ * testsuite/gas/i386/x86-64-movdir.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-movdir.d: Likewise.
+
+2020-09-30 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: Add Cortex-A78 and Cortex-A78AE cores.
+ * doc/c-aarch64.texi: Update docs.
+ * NEWS: Update news.
+
+2020-09-30 Alex Coplan <alex.coplan@arm.com>
+
+ * NEWS: Mention recent Arm processor support.
+
+2020-09-30 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2.
+ * doc/c-aarch64.texi: Document support for Neoverse N2.
+
+2020-09-30 Alan Modra <amodra@gmail.com>
+
+ * config/obj-elf.c (obj_elf_change_section): Rename variable to
+ avoid shadowing warning.
+ * symbols.c (symbol_entry_find): Init all symbol_flags fields.
+
+2020-09-29 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * NEWS: TRBE, ETE, ETMv4 and Cortex-X1 news updates.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-arm.c: (arm_cpus): Add Cortex-X1.
+ * doc/c-arm.texi: Document -mcpu=cortex-x1.
+ * testsuite/gas/arm/cpu-cortex-x1.d: New test.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/etm-ro-invalid.d: New test.
+ * testsuite/gas/aarch64/etm-ro-invalid.l: New test.
+ * testsuite/gas/aarch64/etm-ro-invalid.s: New test.
+ * testsuite/gas/aarch64/etm-ro.s: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.d: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.l: New test.
+ * testsuite/gas/aarch64/etm-wo-invalid.s: New test.
+ * testsuite/gas/aarch64/etm-wo.s: New test.
+ * testsuite/gas/aarch64/etm.s: New test.
+ * testsuite/gas/aarch64/sysreg.d: system register s2_1_c0_c3_0
+ disassembled now to trcstatr.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * config/tc-aarch64.c: (aarch64_cpus): Add Cortex-X1.
+ * doc/c-aarch64.texi: Document -mcpu=cortex-x1.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/ete.d: New test.
+ * testsuite/gas/aarch64/ete.s: New test.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * testsuite/gas/aarch64/trbe-invalid.d: New test.
+ * testsuite/gas/aarch64/trbe-invalid.l: New test.
+ * testsuite/gas/aarch64/trbe-invalid.s: New test.
+ * testsuite/gas/aarch64/trbe.d: New test.
+ * testsuite/gas/aarch64/trbe.s: New test.
+
+2020-09-28 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
+
+2020-09-28 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores together,
+ add missing F16 bit to Neoverse V1.
+
+2020-09-26 Alan Modra <amodra@gmail.com>
+
+ * config/tc-csky.c (parse_type_ctrlreg): Don't mask mach_flag
+ for csky_get_control_regno.
+ (csky_get_reg_val): Likewise when calling csky_get_general_regno.
+
+2020-09-24 Jim Wilson <jimw@sifive.com>
+
+ PR 26400
+ * config/tc-riscv.c (append_insn): If in absolute section, emit
+ error before add_relaxed_insn call.
+ * testsuite/gas/riscv/absolute-sec.d: New.
+ * testsuite/gas/riscv/absolute-sec.l: New.
+ * testsuite/gas/riscv/absolute-sec.s: New.
+
+2020-09-23 Mark Wielaard <mark@klomp.org>
+
+ * testsuite/gas/elf/dwarf-5-cu.d: Adjust expected output.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Neoverse V1.
+ * doc/c-arm.texi: Document Neoverse V1 support.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1.
+ * doc/c-aarch64.texi: Document Neoverse V1 support.
+
+2020-09-24 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Add Neoverse N2.
+ * doc/c-arm.texi: Document -mcpu=neoverse-n2.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add TDX.
+ * config/tc-i386.c (cpu_arch): Add .tdx.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document tdx.
+ * testsuite/gas/i386/i386.exp: Run tdx tests.
+ * testsuite/gas/i386/tdx.d: Likewise.
+ * testsuite/gas/i386/tdx.s: Likewise.
+ * testsuite/gas/i386/x86-64-tdx.d: Likewise.
+ * testsuite/gas/i386/x86-64-tdx.s: Likewise.
+
+2020-09-17 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (parse_type_ctrlreg): Use function
+ csky_get_control_regno to operand.
+ (csky_get_reg_val): Likewise.
+ (is_reg_sp_with_bracket): Use function csky_get_reg_val
+ to parse operand.
+ (is_reg_sp): Refine.
+ (is_oimm_within_range): Fix, report error when operand
+ is not constant.
+ (parse_type_cpreg): Refine.
+ (parse_type_cpcreg): Refine.
+ (get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
+ (md_assemble): Fix no error reporting somtimes when
+ operands number are not fit.
+ (csky_addc64): Refine.
+ (csky_subc64): Refine.
+ (csky_or64): Refine.
+ (v1_work_fpu_fo): Refine.
+ (v1_work_fpu_read): Refine.
+ (v1_work_fpu_writed): Refine.
+ (v1_work_fpu_readd): Refine.
+ (v2_work_addc): New function, strengthen the operands legality
+ check of addc.
+ * testsuite/gas/csky/all.d : Use register number format when
+ disassemble register name by default.
+ * testsuite/gas/csky/cskyv2_all.d : Likewise.
+ * testsuite/gas/csky/trust.d: Likewise.
+ * testsuite/gas/csky/cskyv2_ck860.d : Fix.
+ * testsuite/gas/csky/trust.s : Fix.
+
+2020-09-23 Lili Cui <lili.cui@intel.com>
+
+ * NEWS: Add Key Locker.
+ * config/tc-i386.c (cpu_arch): Add .kl and .wide_kl.
+ (cpu_noarch): Likewise.
+ * doc/c-i386.texi: Document kl and wide_kl.
+ * testsuite/gas/i386/i386.exp: Run keylocker tests.
+ * testsuite/gas/i386/keylocker-intel.d: New test.
+ * testsuite/gas/i386/keylocker.d: Likewise.
+ * testsuite/gas/i386/keylocker.s: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker.d: Likewise.
+ * testsuite/gas/i386/x86-64-keylocker.s: Likewise.
+ * testsuite/gas/i386/x86-64-property-10.d: Likewise.
+ * testsuite/gas/i386/property-10.d: Likewise.
+ * testsuite/gas/i386/property-10.s: Likewise.
+
+2020-09-21 Alan Modra <amodra@gmail.com>
+
+ PR 26569
+ * config/tc-riscv.c (append_insn): Don't tie off frags at CALL
+ relocs.
+ (riscv_call): Tie them off after the jalr.
+ (md_apply_fix): Zero fx_size of RELAX fixup.
+
+2020-09-018 David Faust <david.faust@oracle.com>
+
+ * testsuite/gas/bpf/alu-xbpf.d: New file.
+ * testsuite/gas/bpf/alu-xbpf.s: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testsuite/gas/bpf/alu32-xbpf.d: Likewise.
+ * testuiste/gas/bpf/bpf.exp: Run new tests.
+
+2020-09-18 Tucker <tuckkern+sourceware@gmail.com>
+
+ PR 26556
+ * read.c (bss_alloc): Convert size parameter from octets to
+ bytes.
+
+2020-09-17 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/i386/i386.exp: Return early if not x86.
+
+2020-09-16 Alan Modra <amodra@gmail.com>
+
+ * config/obj-elf.c (obj_elf_visibility, elf_frob_symbol): Adjust
+ elf_symbol_from invocation.
+ * config/tc-aarch64.c (s_variant_pcs): Likewise.
+ * config/tc-m68hc11.c (s_m68hc11_mark_symbol): Likewise.
+ * config/tc-ppc.c (ppc_elf_localentry, ppc_force_relocation),
+ (ppc_fix_adjustable): Likewise.
+ * config/tc-xgate.c (xgate_frob_symbol): Likewise.
+
+2020-09-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * testsuite/gas/cfi/reloc-pe-i386.d: Updated.
+ * testsuite/gas/i386/x86-64-w64-pcrel.d: Likewise.
+
+2020-09-15 Alan Modra <amodra@gmail.com>
+
+ PR 26610
+ * config/tc-arm.c (move_or_literal_pool): Correct extraction of
+ bignum. Use unsigned "v"
+ (is_double_a_single): Make "v" and "mantissa" unsigned. Formatting.
+ (double_to_single): Likewise.
+
+2020-09-15 Nick Clifton <nickc@redhat.com>
+
+ * read.c (s_nop): Preserve the input_line_pointer around the call
+ to md_assemble.
+ * config/tc-s12z.c (md_assemble): Revert previous delta.
+
+2020-09-15 David Faust <david.faust@oracle.com>
+
+ * config/tc-bpf.h (md_single_noop_insn): Use 'ja 0' for no-op.
+
+2020-09-14 Nick Clifton <nickc@redhat.com>
+
+ * read.c (s_nop): New function. Handles the .nop directive.
+ (potable): Add entry for "nop".
+ (s_nops): Code tidy.
+ * read.h (s_nop): Add prototype.
+ * config/tc-bpf.h (md_single_noop_insn): Define.
+ * config/tc-mmix.h (md_single_noop_insn): Define.
+ * config/tc-or1k.h (md_single_noop_insn): Define.
+ * config/tc-ia64.h (md_single_noop_insn): Define.
+ * config/tc-s12z.c (md_assemble): Preserve the input line pointer,
+ rather than corrupting it.
+ * write.c (relax_segment): Update error message regarding
+ non-absolute values passed to .fill and .nops.
+ * NEWS: Mention the new directive.
+ * doc/as.texi: Document the new directive.
+ * doc/internals.texi: Document the new internal macros used to
+ implement the new directive.
+ * testsuite/gas/all/nop.s: New test.
+ * testsuite/gas/all/nop.d: New test control file.
+ * testsuite/gas/all/gas.exp: Run the new test.
+ * testsuite/gas/elf/dwarf-5-nop-for-line-table.s: New test.
+ * testsuite/gas/elf/dwarf-5-nop-for-line-table.d: New test
+ control file.
+ * testsuite/gas/elf/elf.exp: Run the new test.
+ * testsuite/gas/i386/space1.l: Adjust expected output.
+
+2020-09-07 Mark Wielaard <mark@klomp.org>
+
+ * as.texi (-g): Explicitly mention when .debug_info and .debug_line
+ are generated for the DWARF format.
+ (Loc): Add that it is an error to both use a .loc directive and
+ generate a .debug_line yourself.
+ * dwarf2dbg.c (dwarf2_any_loc_directive_seen): New static variable.
+ (dwarf2_directive_loc): Set dwarf2_any_loc_directive_seen to TRUE.
+ (dwarf2_finish): Check dwarf2_any_loc_directive_seen before emitting
+ an error. Only create .debug_line if it is empty (or doesn't exist).
+ * testsuite/gas/i386/i386.exp: Add dwarf2-line-{1,2,3,4} when testing
+ an elf target.
+ * testsuite/gas/i386/dwarf2-line-{1,2,3,4}.{s,d,l}: New test files.
+
+2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (md_begin): Enable extend lrw by default for
+ CK802, CK803 and CK860.
+
+2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (struct csky_cpu_info): Add new members
+ isa_flag, features and ver.
+ (struct csky_cpu_feature): New.
+ (struct csky_cpu_version): New.
+ (CSKY_FEATURE_MAX): Define.
+ (CSKY_CPU_REVERISON_MAX): Define.
+ (FEATURE_DSP_EXT, FEATURE_DSP, FEATURE_MMU, FEATURE_VDSP,
+ FEATURE_FLOAT, FEATURE_TRUST, FEATURE_JAVA, FEATURE_SHIELD):
+ Define, each standard one collection of instructions.
+ (CSKY_FEATURES_DEF_NULL, CSKY_FEATURES_DEF_e,
+ CSKY_FEATURES_DEF_t, CSKY_FEATURES_DEF_f, CSKY_FEATURES_DEF_v,
+ CSKY_FEATURES_DEF_ef, CSKY_FEATURES_DEF_jt,
+ CSKY_FEATURES_DEF_efht, CSKY_FEATURES_DEF_efv,
+ CSKY_FEATURES_DEF_eft, CSKY_FEATURES_DEF_d,
+ CSKY_FEATURES_DEF_df, CSKY_FEATURES_DEF_ft,
+ CSKY_FEATURES_DEF_tv, CSKY_FEATURES_DEF_fv,
+ CSKY_FEATURES_DEF_dft, CSKY_FEATURES_DEF_dfv,
+ CSKY_FEATURES_DEF_ftv, CSKY_FEATURES_DEF_eftv): Define,
+ the features combination used by cpu.
+ (CSKY_CPU_REVERISON_r0p0, CSKY_CPU_REVERISON_r1p0,
+ CSKY_CPU_REVERISON_r2p0, CSKY_CPU_REVERISON_r3p0,
+ CSKY_CPU_REVERISON_RESERVED, CSKY_CPU_REVERISON_R3):
+ Define, version information used by cpu.
+ (csky_cpus): Refine, and add CK804, CK805 and CK800.
+ (parse_cpu): Refine.
+ (parse_arch): Refine.
+ (md_show_usage): Refine.
+ (md_begin): Refine.
+
+2020-09-09 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Emit prefix insn by parts when
+ valueT is smaller than 64 bits.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (CSKYV2_ISA_DSP): CSKY_ISA_DSPE60.
+ (CSKY_ISA_860): Likewise.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (float_abi): New.
+ (md_longopts): Add mfloat-abi.
+ (struct sky_option_value_table): New.
+ (csky_float_abis): New, the possible values for -mfloat-abi.
+ (parse_float_abi): New funtion.
+ (md_show_usage): Show help information for -mfloat-abi.
+ (set_csky_attribute): Store float-abi value.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * config/tc-csky.c (float_work_fpuv3_fmovi): New function,
+ helper function to encode fpuv3 fmovi instructions.
+ (float_work_fpuv3_fstore): New function.
+ (struct literal): Add new member 'offset'.
+ (csky_cpus): New cpu CK860f.
+ (enter_literal): Return literal pool pointer instead of offset.
+ (parse_rt): Adjust the change of enter_literal.
+ (parse_rtf): Likewise.
+ (v1_work_lrw): Likewise.
+ (v1_work_jbsr): Likewise.
+ (v2_work_lrw): Likewise.
+ (v2_work_jbsr): Likewise.
+ (v2_work_jsri): Likewise.
+ (vdsp_work_vlrw): Likewise.
+ (is_freglist_legal): Add handler for FPUV3.
+ (parse_type_freg): Likewise.
+ (is_imm_within_range): Set e.X_add_number if it is a signed and
+ negtive number.
+ (get_operand_value): Add handler for OPRND_TYPE_IMM9b,
+ OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI
+ and OPRND_TYPE_DFLOAT_FMOVI.
+ (float_to_half): Convert float number to harf float.
+ * testsuite/gas/csky/case-fpuv3-ck860f/ : New folder containing
+ the test cases for FPUV3, they are divided by instruction
+ operands format and both have legal cases and illegal cases.
+
+2020-09-08 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+ Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-msp430.c (msp430_insert_uleb128_fixes): New.
+ (msp430_md_end): Call msp430_insert_uleb128_fixes.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add Cortex-R82.
+ * doc/c-aarch64.texi: Document -mcpu=cortex-r82.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (parse_sys_reg): Also pass sysreg name to
+ validation function.
+ (parse_sys_ins_reg): Likewise.
+ (print_operands): Pass CPU features to aarch64_print_operand().
+ * testsuite/gas/aarch64/v8-r-bad-sysregs.d: New test.
+ * testsuite/gas/aarch64/v8-r-bad-sysregs.l: Error output.
+ * testsuite/gas/aarch64/v8-r-bad-sysregs.s: Input.
+ * testsuite/gas/aarch64/v8-r-sysregs-need-arch.d: New test.
+ * testsuite/gas/aarch64/v8-r-sysregs-need-arch.l: Error output.
+ * testsuite/gas/aarch64/v8-r-sysregs.d: New test.
+ * testsuite/gas/aarch64/v8-r-sysregs.s: Input for previous two tests.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * testsuite/gas/aarch64/dfb.d: New test.
+ * testsuite/gas/aarch64/dfb.s: Input.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): Add armv8-r.
+ * doc/c-aarch64.texi: Document -march=armv8-r.
+
+2020-09-07 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2dbg.c (add_line_strp): New function.
+ (out_dir_and_file_list): Take line_seg and sizeof_offset as
+ arguments, Use DW_FORM_line_strp for dir and file. Call
+ add_line_strp and set symbol offset for DWARF2_LINE_VERSION 5.
+ (out_debug_line): Call out_dir_and_file_list with line_seg and
+ sizeof_offset.
+ * testsuite/gas/elf/dwarf-5-file0.d: Expect indirect line
+ strings.
+
+2020-09-07 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2dbg.c (DWARF2_RNGLISTS_VERSION): New constant.
+ (out_debug_ranges): Add ranges_sym argument and set it.
+ (out_debug_rnglists): New function.
+ (out_debug_info): Change ranges_seg argument to ranges_sym
+ and use it to set DW_AT_ranges value.
+ (dwarf2_finish): Remove ranges_seg, add ranges_sym. For
+ DWARF2_VERSION 5 call out_debug_rnglists.
+
+2020-09-07 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2dbg.c (dwarf2_directive_filename): Initialize with_md5 to
+ FALSE.
+ * testsuite/gas/elf/dwarf-5-file0.s: Add a random bignum.
+
+2020-09-01 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_sec_offset for DWARF
+ version 4 or higher.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * expr.c (add_to_result, subtract_from_result): Use unsigned
+ addition and subtraction.
+
2020-09-02 Alan Modra <amodra@gmail.com>
* config/tc-z80.c (is_overflow): Avoid too large shift.
2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
- * gas/config/tc-csky.c (md_begin): Set attributes.
+ * config/tc-csky.c (md_begin): Set attributes.
(isa_flag): Change type to unsigned 64 bits.
(struct csky_cpu_info): Likewise.
(struct csky_macro_info): Likewise.
2020-08-25 Alan Modra <amodra@gmail.com>
PR 26501
- * gas/config/tc-tic54x.c (tic54x_undefined_symbol): Properly treat
+ * config/tc-tic54x.c (tic54x_undefined_symbol): Properly treat
misc_symbol_hash entries without values.
2020-08-25 Alan Modra <amodra@gmail.com>
PR 26500
- * tc-tic4x.c (tic4x_inst_make): Don't die on terminating insn
- with name = "".
+ * config/tc-tic4x.c (tic4x_inst_make): Don't die on terminating
+ insn with name = "".
2020-08-25 Alan Modra <amodra@gmail.com>
(csky_cpus): Add item for CK860.
(md_begin): Enable DSP for CK810 and CK807 by default.
(md_apply_fix): Fix CKCORE_TLS_IE32 relocation failure.
- * gas/testsuite/gas/csky/cskyv2_all.d: Change 'sync 0'
- to 'sync'.
- * gas/testsuite/gas/csky/cskyv2_all.s: Likewise.
- * gas/testsuite/gas/csky/cskyv2_ck860.d: New.
- * gas/testsuite/gas/csky/cskyv2_ck860.s: New.
- * gas/testsuite/gas/csky/enhance_dsp.d: Change plsli.u16
- to plsli.16.
- * gas/testsuite/gas/csky/enhance_dsp.s: Likewise.
+ * testsuite/gas/csky/cskyv2_all.d: Change 'sync 0' to 'sync'.
+ * testsuite/gas/csky/cskyv2_all.s: Likewise.
+ * testsuite/gas/csky/cskyv2_ck860.d: New.
+ * testsuite/gas/csky/cskyv2_ck860.s: New.
+ * testsuite/gas/csky/enhance_dsp.d: Change plsli.u16 to plsli.16.
+ * testsuite/gas/csky/enhance_dsp.s: Likewise.
2020-08-24 Alan Modra <amodra@gmail.com>
2020-08-04 Christian Groessler <chris@groessler.org>
- * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
+ * testsuite/gas/z8k/inout.d: Adapt to correct encoding of
"sout/soutb #imm,reg"
2020-08-04 H.J. Lu <hongjiu.lu@intel.com>
2020-08-02 Mark Wielaard <mark@klomp.org>
- * gas/dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
+ * dwarf2dbg.c (out_dir_and_file_list): For DWARF5 emit at
least one directory if there is at least one file. Use dirs[1]
if dirs[0] is not set, or if there is no dirs[1] the current
working directory. Use files[1] filename, when files[0] filename
* dwarf2dbg.c (out_debug_info): Emit unit type and abbrev offset
for DWARF5.
- * gas/testsuite/gas/elf/dwarf-4-cu.d: New file.
- * gas/testsuite/gas/elf/dwarf-4-cu.s: Likewise.
- * gas/testsuite/gas/elf/dwarf-5-cu.d: Likewise.
- * gas/testsuite/gas/elf/dwarf-5-cu.s: Likewise.
+ * testsuite/gas/elf/dwarf-4-cu.d: New file.
+ * testsuite/gas/elf/dwarf-4-cu.s: Likewise.
+ * testsuite/gas/elf/dwarf-5-cu.d: Likewise.
+ * testsuite/gas/elf/dwarf-5-cu.s: Likewise.
* testsuite/gas/elf/elf.exp: Run dwarf-4-cu and dwarf-5-cu.
2020-08-02 Mark Wielaard <mark@klomp.org>
2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
- * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+ * config/tc-i386.c (build_vex_prefix): Support VEX base opcode
+ length > 1.
(md_assemble): Don't process ImmExt without operands.
2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
2020-05-27 Simon Cook <simon.cook@embecosm.com>
- * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
- pointer when creating struct riscv_csr_extra.
+ * config/tc-riscv.c (riscv_init_csr_hash): NULL initilize next
+ pointer when creating struct riscv_csr_extra.
2020-05-26 H.J. Lu <hongjiu.lu@intel.com>
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
- * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
* testsuite/gas/i386/solaris/x86-64-branch-3.d: New file.
* testsuite/gas/i386/solaris/x86-64-jump.d: Incorporate changes to
testsuite/gas/i386/x86-64-jump.d.
- * gas/testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
+ * testsuite/gas/i386/solaris/x86-64-mpx-branch-1.d:
Incorporate changes to
gas/testsuite/gas/i386/x86-64-mpx-branch-1.d.
* testsuite/gas/i386/solaris/x86-64-mpx-branch-2.d : Incorporate
2020-02-01 Anthony Green <green@moxielogic.com>
- * config/tc-moxie.c (md_begin): Don't force big-endian mode.
+ * config/tc-moxie.c (md_begin): Don't force big-endian mode.
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
projects / thirdparty / binutils-gdb.git / blobdiff