+2020-07-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (build_modrm_byte): Check vexswapsources to
+ swap two source operands.
+
+2020-07-02 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/all/fill-1.d: Skip for MeP targets.
+
+2020-07-02 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-aarch64.c (reg_name_p): Fix cast so that we don't
+ segfault on negative chars.
+ * testsuite/gas/aarch64/reglike-label-unicode-segv.d: New test.
+ * testsuite/gas/aarch64/reglike-label-unicode-segv.s: Input.
+
+2020-07-02 Nick Clifton <nickc@redhat.com>
+
+ PR 26028
+ * testsuite/gas/ia64/group-2.d: Add -T option to readelf
+ command line.
+ * testsuite/gas/ia64/unwind.d: Likewise.
+ * testsuite/gas/mmix/bspec-1.d: Likewise.
+ * testsuite/gas/mmix/bspec-2.d: Likewise.
+ * testsuite/gas/mmix/comment-1.d: Likewise.
+ * testsuite/gas/tic6x/scomm-directive-4.d: Likewise.
+
+2020-07-01 Alan Modra <amodra@gmail.com>
+
+ * config/tc-xc16x.c (md_apply_fix): Add FIXME.
+
+2020-07-01 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/all/eqv-dot.d: xfail targets that set linkrelax
+ in data sections, and mep.
+
+2020-06-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention x86 NaCl target support removal.
+ * config/tc-i386.c: Remove x86 NaCl target support.
+ * config/tc-i386.h: Likewise.
+ * configure.tgt: Likewise.
+ * testsuite/gas/i386/i386.exp: Likewise.
+ * testsuite/gas/i386/iamcu-1.d: Likewise.
+ * testsuite/gas/i386/iamcu-2.d: Likewise.
+ * testsuite/gas/i386/iamcu-3.d: Likewise.
+ * testsuite/gas/i386/iamcu-4.d: Likewise.
+ * testsuite/gas/i386/iamcu-5.d: Likewise.
+ * testsuite/gas/i386/k1om.d: Likewise.
+ * testsuite/gas/i386/l1om.d: Likewise.
+
+2020-06-30 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (riscv_csr_class_check): Removed. Move the
+ checking into riscv_csr_address.
+ (riscv_csr_version_check): Likewise.
+ (riscv_csr_address): New function. Return the suitable CSR address
+ after checking the ISA dependency and versions. Issue warnings if
+ we find any conflict and -mcsr-check is set. CSR_CLASS_F and
+ CSR_CLASS_DEBUG are unprivileged CSR for now, so don't check the
+ priv spec versions for them.
+ (reg_csr_lookup_internal): Call riscv_csr_address to find the
+ suitable CSR address.
+ * testsuite/gas/riscv/priv-reg-fail-fext.d: Remove -mpriv-spec=1.11.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-fext.l: We don't care the
+ priv spec warnings here. These warnings are added by accident.
+ Remove them and only focus on the ISA dependency warnings.
+ * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Updated since
+ dscratch0 and dscratch1 are regarded as the unprivileged CSR rather
+ than the privileged ones.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
+ * testsuite/gas/riscv/priv-reg.s: Likewise. Add missing debug CSR.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
+ * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
+
+2020-06-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * tc-i386.c (build_vex_prefix): Support VEX base opcode length > 1.
+ (md_assemble): Don't process ImmExt without operands.
+
+2020-06-29 Hans-Peter Nilsson <hp@bitrange.com>
+
+ PR gas/25331
+ * config/tc-mmix.c (md_assemble) <fixup for
+ BFD_RELOC_MMIX_BASE_PLUS_OFFSET>: This fixup affects 1 byte, not 8.
+ Also, set its fx_no_overflow.
+ (md_convert_frag) <case ENCODE_RELAX (STATE_PUSHJSTUB, STATE_ZERO)>:
+ Similarly this fixup affects 4 bytes, not 8 and needs its
+ fx_no_overflow set.
+ * config/tc-mmix.h (TC_FX_SIZE_SLACK): Don't define.
+ * testsuite/gas/mmix/pr25331.d, testsuite/gas/mmix/pr25331.s: New test.
+
+2020-06-29 Alan Modra <amodra@gmail.com>
+
+ * config/tc-s12z.c: Use C style comments.
+ * config/tc-z80.c: Likewise.
+ * config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (md_assemble): Process ImmExt without
+ operands.
+
+2020-06-26 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
+ Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
+ VECSIB256 and VECSIB512, respectively.
+ (build_modrm_byte): Replace vecsib with sib.
+
+2020-06-26 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/nop-1-suffix.d: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+
+2020-06-26 Pat Bernardi <bernardi@adacore.com>
+
+ * config/tc-m68k.c (m68k_elf_gnu_attribute): New function.
+ (md_pseudo_table): Handle "gnu_attribute".
+ * doc/as.texi: Document GNU attribute for M68K.
+
+2020-06-25 Nick Clifton <nickc@redhat.com>
+
+ PR 26141
+ * config/tc-arm.c (arm_force_relocation): Force resolution of
+ BFD_RELOC_THUMB_PCREL_BRANCH12 relocations.
+ * testsuite/gas/arm/plt-1.d: Adjust expected disassembly.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Move call to process_immext()
+ ...
+ (process_operands): ... here.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Skip ambiguous operand size
+ diagnostic when there is a sizing prefix. Switch to word/dword/
+ qword encoding when there is a sizing prefix and no (explicit or
+ derived) suffix.
+ (update_imm): Handle presence of a sizing prefix.
+ * testsuite/gas/i386/noreg16-data32.d,
+ testsuite/gas/i386/noreg32-data16.d,
+ testsuite/gas/i386/noreg32-data16.e,
+ testsuite/gas/i386/noreg64-data16.d,
+ testsuite/gas/i386/noreg64-data16.e,
+ testsuite/gas/i386/noreg64-rex64.d: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+ * testsuite/gas/i386/noreg32.s, testsuite/gas/i386/noreg64.s:
+ Introduce and use pfx* macros.
+ * testsuite/gas/i386/noreg16.s: Likewise. Replace 32-bit
+ addressing.
+ * testsuite/gas/i386/noreg16.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx-16bit.d,
+ testsuite/gas/i386/avx-scalar.d, testsuite/gas/i386/avx.d,
+ testsuite/gas/i386/avx512f-16bit.d,
+ testsuite/gas/i386/avx512f.d,
+ testsuite/gas/i386/evex-lig256.d,
+ testsuite/gas/i386/evex-lig512.d
+ testsuite/gas/i386/evex-wig1.d, testsuite/gas/i386/katmai.d,
+ testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg32.d,
+ testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/simd.d,
+ testsuite/gas/i386/sse2-16bit.d,
+ testsuite/gas/i386/sse2.d, testsuite/gas/i386/sse2avx.d: Adjust
+ expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Also reject explicit REX
+ prefixes with VEX and alike encoded insns. Zap consumed bits
+ from i.rex.
+ (output_insn): Don't ignore REX prefix for VEX and alike
+ encodings; abort() instead if encountered.
+ * testsuite/gas/i386/x86-64-pseudos.s: Move REX-with-VEX cases
+ ...
+ * testsuite/gas/i386/x86-64-pseudos-bad.s: ... here.
+ * testsuite/gas/i386/x86-64-pseudos.d,
+ testsuite/gas/i386/x86-64-pseudos-bad.l: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_operands): Translate explicit REX
+ prefix into i.rex for SSE2AVX templates.
+ (set_rex_vrex): New helper.
+ (build_modrm_byte): Use it.
+ * testsuite/gas/i386/x86-64-sse2avx.s: Add cases with explict
+ REX prefixes.
+ * testsuite/gas/i386/x86-64-sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (cpu_flags_match): Only match SSE2AVX
+ templates when there's no data size prefix.
+ (md_assemble): Reject data size prefix also for legacy encoded
+ SIMD templates.
+ * testsuite/gas/i386/prefix32.s, testsuite/gas/i386/prefix64.s:
+ Uncomment previously not working line.
+ * testsuite/gas/i386/sse2avx.s: Add ldmxcsr/stmxcsr cases with
+ data16 prefix.
+ * testsuite/gas/i386/prefix32.l, testsuite/gas/i386/prefix64.l,
+ testsuite/gas/i386/sse2avx.d: Adjust expectations.
+
+2020-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (build_evex_prefix): Drop early setting of
+ vec_length.
+
+2020-06-23 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (explicit_priv_attr): Rename explicit_csr to
+ explicit_priv_attr. It used to indicate CSR or priv instructions are
+ explictly used.
+ (riscv_is_priv_insn): Return True if it is a privileged instruction.
+ (riscv_ip): Call riscv_is_priv_insn to check whether the instruction
+ is privileged or not. If it is, then set explicit_priv_attr to TRUE.
+ (riscv_write_out_attrs): Clarification of when to generate the elf
+ priv spec attributes.
+ * testsuite/gas/riscv/attribute-11.s: Add comments.
+ * testsuite/gas/riscv/attribute-14.s: New testcase. Use symbol
+ `priv_insn_<n>` to decide which priv instruction is expected to used.
+ (<n> is a to e.)
+ * testsuite/gas/riscv/attribute-14a.d: Likewise.
+ * testsuite/gas/riscv/attribute-14b.d: Likewise.
+ * testsuite/gas/riscv/attribute-14c.d: Likewise.
+ * testsuite/gas/riscv/attribute-14d.d: Likewise.
+ * testsuite/gas/riscv/attribute-14e.d: Likewise.
+
+2020-06-22 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (buf_size, buf): Remove the unused variables.
+ (riscv_set_default_priv_spec): Get the priv spec version from the
+ priv spec attributes by riscv_get_priv_spec_class_from_numbers.
+
+2020-06-20 Alan Modra <amodra@gmail.com>
+
+ * configure.tgt: Set bfd_gas for all SH targets.
+
+2020-06-18 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/arch-13.s: Add alternative VMGEXIT case.
+ * testsuite/gas/i386/arch-13.d: Extend -march=. Adjust
+ expectations.
+
+2020-06-16 Lili Cui <lili.cui@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Correct noavx512_vp2intersect
+ cpu_arch to CPU_ANY_VP2INTERSECT_FLAGS.
+ * doc/c-i386.texi: Add avx512_vp2intersect.
+
+2020-06-16 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (md_assemble): Drop SSE4a from SSE check
+ conditional.
+ * testsuite/gas/i386/sse-check.s: Adjust comment.
+ * testsuite/gas/i386/sse-check-error.l,
+ testsuite/gas/i386/sse-check-warn.e,
+ testsuite/gas/i386/x86-64-sse-check-error.l: Adjust
+ expectations.
+
+2020-06-16 Alan Modra <amodra@gmail.com>
+
+ * config/tc-tic30.h: Remove OBJ_AOUT support.
+ * configure.tgt: Delete tic30-*-*aout* entry.
+
+2020-06-15 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New
+ macros.
+ (elf32xtensa_abi): New declaration.
+ (option_abi_windowed, option_abi_call0): New enum constants.
+ (md_longopts): Add entries for --abi-windowed and --abi-call0.
+ (md_parse_option): Add handlers for --abi-windowed and
+ --abi-call0.
+ (xtensa_add_config_info): Use xtensa_abi_choice instead of
+ XSHAL_ABI to format ABI tag.
+ * doc/as.texi (Target Xtensa options): Add --abi-windowed and
+ --abi-call0 to the list of options.
+ * doc/c-xtensa.texi: Add description for options --abi-windowed
+ and --abi-call0.
+ * testsuite/gas/xtensa/abi-call0.d: New test definition.
+ * testsuite/gas/xtensa/abi-windowed.d: New test definition.
+ * testsuite/gas/xtensa/abi.s: New test source.
+
+2020-06-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26115
+ * testsuite/gas/i386/tsxldtrk.d: Replace xsuspldtrk with
+ xsusldtrk.
+ * testsuite/gas/i386/tsxldtrk.s: Likewise.
+ * testsuite/gas/i386/x86-64-tsxldtrk.d: Likewise.
+ * testsuite/gas/i386/x86-64-tsxldtrk.s: Likewise.
+
+2020-06-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed.
+ * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
+ * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise.
+
+2020-06-09 Seth Girvan <snth@snthhacks.com>
+
+ * doc/c-avr.texi: Improve wording.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/x86-64-pseudos-bad.s,
+ testsuite/gas/i386/x86-64-pseudos-bad.l: New.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/prefix.s: Add bogus prefix-with-VEX/EVEX
+ encoding tests.
+ * testsuite/gas/i386/prefix.d: Adjust expectations.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/prefix.s: Add bogus REP / EVEX.W prefix
+ with VEX/EVEX encoding tests.
+ * testsuite/gas/i386/prefix.d: Adjust expectations.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (process_suffix): Restrict defaulting to 'q'
+ suffix.
+ * testsuite/gas/i386/noreg64.s: Add lcall/ljmp cases.
+ * testsuite/gas/i386/noreg64.d: Adjust expectations.
+ * testsuite/gas/i386/noreg-intel64.d,
+ testsuite/gas/i386/noreg-intel64.l,
+ testsuite/gas/i386/noreg-intel64.s: New.
+ * testsuite/gas/i386/i386.exp: Run new tests.
+
+2020-06-09 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (vex_encoding_error): New enumerator.
+ (VEX_check_operands): Rename to VEX_check_encoding. Check
+ for vex_encoding_error. Move Imm4 handling ...
+ (check_VecOperands): ... here.
+ (match_template): Call VEX_check_encoding when there are no
+ operands. Split construct calling check_VecOperands and
+ VEX_check_encoding (when there are operands).
+ (check_register): Don't blindly set vex_encoding_evex.
+ * testsuite/gas/i386/pseudos-bad.s,
+ testsuite/gas/i386/pseudos-bad.l: New.
+ * testsuite/gas/i386/i386.exp: Run new test.
+ * testsuite/gas/i386/xmmhi64.s: Drop {vex2}.
+
+2020-06-08 Alex Coplan <alex.coplan@arm.com>
+
+ * config/tc-arm.c (insns): Add dfb.
+ * testsuite/gas/arm/dfb.d: New test.
+ * testsuite/gas/arm/dfb.s: Input for test.
+
+2020-06-08 Nick Clifton <nickc@redhat.com>
+
+ * testsuite/gas/cfi/cfi-i386-2.d: Skip for PE based targets.
+
+2020-06-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (pi): Add checks for RegMask and RegBND.
+
2020-06-08 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_byte_reg): Drop dead conditional