Revert "2.41 Release sources"

[thirdparty/binutils-gdb.git] / gas / doc / c-bpf.texi

diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
index be29d8d2a5659ca1aa3680f46644a9d3dcc6e704..6b43c77d5a08d6af110e09a2a1b95a393ba31bf5 100644 (file)
--- a/gas/doc/c-bpf.texi
+++ b/gas/doc/c-bpf.texi
@@ -53,6 +53,10 @@ when assembling.  The BPF ISA versions supported are @option{v1} @option{v2}, @o
 The value @option{xbpf} can be specified to recognize extra
 instructions that are used by GCC for testing purposes.  But beware
 this is not valid BPF.
+
+@cindex @option{-mno-relax} command-line options, BPF
+@item -mno-relax
+This option tells the assembler to not relax instructions.
 @end table
 
 Note that if no endianness option is specified in the command line,
@@ -64,9 +68,8 @@ the host endianness is used.
 
 @cindex line comment character, BPF
 @cindex BPF line comment character
-The presence of a @samp{;} on a line indicates the start of a comment
-that extends to the end of the current line.  If a @samp{#} appears as
-the first character of a line, the whole line is treated as a comment.
+The presence of a @samp{;} or a @samp{#} on a line indicates the start
+of a comment that extends to the end of the current line.
 
 @cindex statement separator, BPF
 Statements and assembly directives are separated by newlines.
@@ -244,9 +247,9 @@ registers.
 @itemx rd s>>= imm32
 64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
 
-@item neg rd, rs
+@item neg rd
 @itemx neg rd, imm32
-@itemx rd = - rs
+@itemx rd = - rd
 @itemx rd = - imm32
 64-bit arithmetic negation.
 
@@ -351,9 +354,9 @@ in the same instruction.
 @itemx rd s>>= imm32
 32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
 
-@item neg32 rd, rs
+@item neg32 rd
 @itemx neg32 rd, imm32
-@itemx rd = - rs
+@itemx rd = - rd
 @itemx rd = - imm32
 32-bit arithmetic negation.
 
@@ -404,6 +407,26 @@ Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
 and store it back in @code{rd}.
 @end table
 
+@subsection Byte swap instructions
+
+@table @code
+@item bswap rd, 16
+@itemx rd = bswap16 rd
+Swap the least-significant 16-bit word in @code{rd} with the
+most-significant 16-bit word.
+
+@item bswap rd, 32
+@itemx rd = bswap32 rd
+Swap the least-significant 32-bit word in @code{rd} with the
+most-significant 32-bit word.
+
+@item bswap rd, 64
+@itemx rd = bswap64 rd
+Swap the least-significant 64-bit word in @code{rd} with the
+most-significant 64-bit word.
+@end table
+
+
 @subsection 64-bit load and pseudo maps
 
 @table @code
@@ -725,48 +748,64 @@ Jump if signed lesser or equal.
 
 @subsection Atomic instructions
 
-Atomic exchange-and-add instructions are provided in two flavors: one
-for swapping 64-bit quantities and another for 32-bit quantities.
+Atomic exchange instructions are provided in two flavors: one for
+compare-and-swap, one for unconditional exchange.
+
+@table @code
+@item acmp [rd + offset16], rs
+@itemx r0 = cmpxchg_64 (rd + offset16, r0, rs)
+Atomic compare-and-swap.  Compares value in @code{r0} to value
+addressed by @code{rd + offset16}.  On match, the value addressed by
+@code{rd + offset16} is replaced with the value in @code{rs}.
+Regardless, the value that was at @code{rd + offset16} is
+zero-extended and loaded into @code{r0}.
+
+@item axchg [rd + offset16], rs
+@itemx rs = xchg_64 (rd + offset16, rs)
+Atomic exchange.  Atomically exchanges the value in @code{rs} with
+the value addressed by @code{rd + offset16}.
+@end table
+
+@noindent
+The following instructions provide atomic arithmetic operations.
 
 @table @code
 @item aadd [rd + offset16], rs
-@itemx *(u64 *)(rd + offset16) = rs
+@itemx lock *(u64 *)(rd + offset16) = rs
 Atomic add instruction.
 
 @item aor [rd + offset16], rs
-@itemx *(u64 *) (rd + offset16) |= rs
+@itemx lock *(u64 *) (rd + offset16) |= rs
 Atomic or instruction.
 
 @item aand [rd + offset16], rs
-@itemx *(u64 *) (rd + offset16) &= rs
+@itemx lock *(u64 *) (rd + offset16) &= rs
 Atomic and instruction.
 
 @item axor [rd + offset16], rs
-@itemx *(u64 *) (rd + offset16) ^= rs
-Atomic xor instruction
-@item xaddw [%d+offset16],%s
-Exchange-and-add a 32-bit value at the specified location.
+@itemx lock *(u64 *) (rd + offset16) ^= rs
+Atomic xor instruction.
 @end table
 
 @noindent
 The following variants perform fetching before the atomic operation.
 
 @table @code
-@item afadd [dr + offset16], rs
-@itemx ???
+@item afadd [rd + offset16], rs
+@itemx rs = atomic_fetch_add ((u64 *)(rd + offset16), rs)
 Atomic fetch-and-add instruction.
 
-@item afor [dr + offset16], rs
-@itemx ???
+@item afor [rd + offset16], rs
+@itemx rs = atomic_fetch_or ((u64 *)(rd + offset16), rs)
 Atomic fetch-and-or instruction.
 
-@item afand [dr + offset16], rs
-@itemx ???
+@item afand [rd + offset16], rs
+@itemx rs = atomic_fetch_and ((u64 *)(rd + offset16), rs)
 Atomic fetch-and-and instruction.
 
-@item afxor [dr + offset16], rs
-@itemx ???
-Atomic fetch-and-or instruction
+@item afxor [rd + offset16], rs
+@itemx rs = atomic_fetch_xor ((u64 *)(rd + offset16), rs)
+Atomic fetch-and-or instruction.
 @end table
 
 The above instructions were introduced in the V3 of the BPF
@@ -780,24 +819,42 @@ Alias to @code{aadd}.
 
 @subsection 32-bit atomic instructions
 
-Atomic exchange-and-add instructions are provided in two flavors: one
-for swapping 32-bit quantities and another for 32-bit quantities.
+32-bit atomic exchange instructions are provided in two flavors: one
+for compare-and-swap, one for unconditional exchange.
+
+@table @code
+@item acmp32 [rd + offset16], rs
+@itemx w0 = cmpxchg32_32 (rd + offset16, w0, ws)
+Atomic compare-and-swap.  Compares value in @code{w0} to value
+addressed by @code{rd + offset16}.  On match, the value addressed by
+@code{rd + offset16} is replaced with the value in @code{ws}.
+Regardless, the value that was at @code{rd + offset16} is
+zero-extended and loaded into @code{w0}.
+
+@item axchg [rd + offset16], rs
+@itemx ws = xchg32_32 (rd + offset16, ws)
+Atomic exchange.  Atomically exchanges the value in @code{ws} with
+the value addressed by @code{rd + offset16}.
+@end table
+
+@noindent
+The following instructions provide 32-bit atomic arithmetic operations.
 
 @table @code
 @item aadd32 [rd + offset16], rs
-@itemx *(u32 *)(rd + offset16) = rs
+@itemx lock *(u32 *)(rd + offset16) = rs
 Atomic add instruction.
 
 @item aor32 [rd + offset16], rs
-@itemx *(u32 *) (rd + offset16) |= rs
+@itemx lock *(u32 *) (rd + offset16) |= rs
 Atomic or instruction.
 
 @item aand32 [rd + offset16], rs
-@itemx *(u32 *) (rd + offset16) &= rs
+@itemx lock *(u32 *) (rd + offset16) &= rs
 Atomic and instruction.
 
 @item axor32 [rd + offset16], rs
-@itemx *(u32 *) (rd + offset16) ^= rs
+@itemx lock *(u32 *) (rd + offset16) ^= rs
 Atomic xor instruction
 @end table
 
@@ -806,19 +863,19 @@ The following variants perform fetching before the atomic operation.
 
 @table @code
 @item afadd32 [dr + offset16], rs
-@itemx ???
+@itemx ws = atomic_fetch_add ((u32 *)(rd + offset16), ws)
 Atomic fetch-and-add instruction.
 
 @item afor32 [dr + offset16], rs
-@itemx ???
+@itemx ws = atomic_fetch_or ((u32 *)(rd + offset16), ws)
 Atomic fetch-and-or instruction.
 
 @item afand32 [dr + offset16], rs
-@itemx ???
+@itemx ws = atomic_fetch_and ((u32 *)(rd + offset16), ws)
 Atomic fetch-and-and instruction.
 
 @item afxor32 [dr + offset16], rs
-@itemx ???
+@itemx ws = atomic_fetch_xor ((u32 *)(rd + offset16), ws)
 Atomic fetch-and-or instruction
 @end table