FT32B is a new FT32 family member. It has a code compression scheme, which requires...

[thirdparty/binutils-gdb.git] / gas / testsuite / gas / elf / dwarf2-5.d

diff --git a/gas/testsuite/gas/elf/dwarf2-5.d b/gas/testsuite/gas/elf/dwarf2-5.d
index 8b2ea2a6e8d09138c3b30febd1366063a0d27158..03829fb8959fff7f1a2a623d85dca6ba2ad558dc 100644 (file)
--- a/gas/testsuite/gas/elf/dwarf2-5.d
+++ b/gas/testsuite/gas/elf/dwarf2-5.d
@@ -1,11 +1,11 @@
 #as:
 #readelf: -x.rodata -wlL
 #name: DWARF2 5
-# The am33 avr cr16 crx mn10 msp430 nds32 pru rl78 rx and xtensa targets do not evaluate the subtraction of symbols at assembly time.
+# The am33 avr cr16 crx ft32 mn10 msp430 nds32 pru rl78 rx and xtensa targets do not evaluate the subtraction of symbols at assembly time.
 # The mep target tries to relay code sections which breaks symbolic view computations.
 # The riscv targets do not support the subtraction of symbols.
 # The tile targets require 8-byte instructions, but the test only simulates 4-byte instructions.
-#not-target: am3*-* avr-* cr16-* crx-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* rx-* tile*-* xtensa-*
+#not-target: am3*-* avr-* cr16-* crx-* ft32*-* mep-* mn10*-* msp430-* nds32*-* pru-* riscv*-* rl78-* rx-* tile*-* xtensa-*
 
 Hex dump of section '\.rodata':
   0x00000000 01010201 010203 *.*