/* Common target dependent code for GDB on ARM systems.
- Copyright (C) 1988-2016 Free Software Foundation, Inc.
+ Copyright (C) 1988-2019 Free Software Foundation, Inc.
This file is part of GDB.
#include "gdbcmd.h"
#include "gdbcore.h"
#include "dis-asm.h" /* For register styles. */
+#include "disasm.h"
#include "regcache.h"
#include "reggroups.h"
-#include "doublest.h"
+#include "target-float.h"
#include "value.h"
#include "arch-utils.h"
#include "osabi.h"
#include "remote.h"
#include "target-descriptions.h"
#include "user-regs.h"
-#include "observer.h"
+#include "observable.h"
#include "arch/arm.h"
#include "arch/arm-get-next-pcs.h"
#include "coff/internal.h"
#include "elf/arm.h"
-#include "vec.h"
+#include "common/vec.h"
#include "record.h"
#include "record-full.h"
#include "features/arm/arm-with-vfpv3.c"
#include "features/arm/arm-with-neon.c"
+#if GDB_SELF_TEST
+#include "common/selftest.h"
+#endif
+
static int arm_debug;
/* Macros for setting and testing a bit in a minimal symbol that marks
static const char *arm_fallback_mode_string = "auto";
static const char *arm_force_mode_string = "auto";
-/* Internal override of the execution mode. -1 means no override,
- 0 means override to ARM mode, 1 means override to Thumb mode.
- The effect is the same as if arm_force_mode has been set by the
- user (except the internal override has precedence over a user's
- arm_force_mode override). */
-static int arm_override_mode = -1;
-
-/* Number of different reg name sets (options). */
-static int num_disassembly_options;
-
/* The standard register names, and all the valid aliases for them. Note
that `fp', `sp' and `pc' are not added in this alias list, because they
have been added as builtin user registers in
"f4", "f5", "f6", "f7", /* 20 21 22 23 */
"fps", "cpsr" }; /* 24 25 */
+/* Holds the current set of options to be passed to the disassembler. */
+static char *arm_disassembler_options;
+
/* Valid register name styles. */
static const char **valid_disassembly_styles;
/* This is used to keep the bfd arch_info in sync with the disassembly
style. */
-static void set_disassembly_style_sfunc(char *, int,
+static void set_disassembly_style_sfunc (const char *, int,
struct cmd_list_element *);
-static void set_disassembly_style (void);
-
-static void convert_from_extended (const struct floatformat *, const void *,
- void *, int);
-static void convert_to_extended (const struct floatformat *, void *,
- const void *, int);
+static void show_disassembly_style_sfunc (struct ui_file *, int,
+ struct cmd_list_element *,
+ const char *);
static enum register_status arm_neon_quad_read (struct gdbarch *gdbarch,
- struct regcache *regcache,
+ readable_regcache *regcache,
int regnum, gdb_byte *buf);
static void arm_neon_quad_write (struct gdbarch *gdbarch,
struct regcache *regcache,
arm_is_thumb (struct regcache *regcache)
{
ULONGEST cpsr;
- ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regcache));
+ ULONGEST t_bit = arm_psr_thumb_bit (regcache->arch ());
cpsr = regcache_raw_get_unsigned (regcache, ARM_PS_REGNUM);
{
struct bound_minimal_symbol sym;
char type;
- struct displaced_step_closure* dsc
- = get_displaced_step_closure_by_addr(memaddr);
+ arm_displaced_step_closure *dsc
+ = ((arm_displaced_step_closure * )
+ get_displaced_step_closure_by_addr (memaddr));
/* If checking the mode of displaced instruction in copy area, the mode
should be determined by instruction on the original address. */
if (IS_THUMB_ADDR (memaddr))
return 1;
- /* Respect internal mode override if active. */
- if (arm_override_mode != -1)
- return arm_override_mode;
-
/* If the user wants to override the symbol table, let him. */
if (strcmp (arm_force_mode_string, "arm") == 0)
return 0;
implementation (this is hand-written ARM assembler in glibc). */
if (!is_thumb
- && read_memory_unsigned_integer (pc, 4, byte_order_for_code)
+ && read_code_unsigned_integer (pc, 4, byte_order_for_code)
== 0xe3e00a0f /* mov r0, #0xffff0fff */
- && read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code)
+ && read_code_unsigned_integer (pc + 4, 4, byte_order_for_code)
== 0xe240f01f) /* sub pc, r0, #31 */
return 1;
}
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
int i;
pv_t regs[16];
- struct pv_area *stack;
- struct cleanup *back_to;
CORE_ADDR offset;
CORE_ADDR unrecognized_pc = 0;
for (i = 0; i < 16; i++)
regs[i] = pv_register (i, 0);
- stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
- back_to = make_cleanup_free_pv_area (stack);
+ pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
while (start < limit)
{
unsigned short insn;
- insn = read_memory_unsigned_integer (start, 2, byte_order_for_code);
+ insn = read_code_unsigned_integer (start, 2, byte_order_for_code);
if ((insn & 0xfe00) == 0xb400) /* push { rlist } */
{
int regno;
int mask;
- if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ if (stack.store_would_trash (regs[ARM_SP_REGNUM]))
break;
/* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
{
regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
-4);
- pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
+ stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]);
}
}
else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */
offset = (insn & 0xff) << 2;
addr = pv_add_constant (regs[ARM_SP_REGNUM], offset);
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
- pv_area_store (stack, addr, 4, regs[regno]);
+ stack.store (addr, 4, regs[regno]);
}
else if ((insn & 0xf800) == 0x6000) /* str rd, [rn, #off] */
{
offset = bits (insn, 6, 10) << 2;
addr = pv_add_constant (regs[rn], offset);
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
- pv_area_store (stack, addr, 4, regs[rd]);
+ stack.store (addr, 4, regs[rd]);
}
else if (((insn & 0xf800) == 0x7000 /* strb Rd, [Rn, #off] */
|| (insn & 0xf800) == 0x8000) /* strh Rd, [Rn, #off] */
{
unsigned short inst2;
- inst2 = read_memory_unsigned_integer (start + 2, 2,
- byte_order_for_code);
+ inst2 = read_code_unsigned_integer (start + 2, 2,
+ byte_order_for_code);
if ((insn & 0xf800) == 0xf000 && (inst2 & 0xe800) == 0xe800)
{
pv_t addr = regs[bits (insn, 0, 3)];
int regno;
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
/* Calculate offsets of saved registers. */
if (inst2 & (1 << regno))
{
addr = pv_add_constant (addr, -4);
- pv_area_store (stack, addr, 4, regs[regno]);
+ stack.store (addr, 4, regs[regno]);
}
if (insn & 0x0020)
else
addr = pv_add_constant (addr, -offset);
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
- pv_area_store (stack, addr, 4, regs[regno1]);
- pv_area_store (stack, pv_add_constant (addr, 4),
- 4, regs[regno2]);
+ stack.store (addr, 4, regs[regno1]);
+ stack.store (pv_add_constant (addr, 4),
+ 4, regs[regno2]);
if (insn & 0x0020)
regs[bits (insn, 0, 3)] = addr;
else
addr = pv_add_constant (addr, -offset);
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
- pv_area_store (stack, addr, 4, regs[regno]);
+ stack.store (addr, 4, regs[regno]);
if (inst2 & 0x0100)
regs[bits (insn, 0, 3)] = addr;
offset = inst2 & 0xfff;
addr = pv_add_constant (regs[bits (insn, 0, 3)], offset);
- if (pv_area_store_would_trash (stack, addr))
+ if (stack.store_would_trash (addr))
break;
- pv_area_store (stack, addr, 4, regs[regno]);
+ stack.store (addr, 4, regs[regno]);
}
else if ((insn & 0xffd0) == 0xf880 /* str{bh}.w Rt,[Rn,#imm] */
unrecognized_pc = start;
if (cache == NULL)
- {
- do_cleanups (back_to);
- return unrecognized_pc;
- }
+ return unrecognized_pc;
if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM))
{
}
for (i = 0; i < 16; i++)
- if (pv_area_find_reg (stack, gdbarch, i, &offset))
+ if (stack.find_reg (gdbarch, i, &offset))
cache->saved_regs[i].addr = offset;
- do_cleanups (back_to);
return unrecognized_pc;
}
if (is_thumb)
{
unsigned short insn1
- = read_memory_unsigned_integer (pc, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc, 2, byte_order_for_code);
if ((insn1 & 0xf800) == 0x4800) /* ldr Rd, #immed */
{
else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */
{
unsigned short insn2
- = read_memory_unsigned_integer (pc + 2, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 2, 2, byte_order_for_code);
low = EXTRACT_MOVW_MOVT_IMM_T (insn1, insn2);
insn1
- = read_memory_unsigned_integer (pc + 4, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 4, 2, byte_order_for_code);
insn2
- = read_memory_unsigned_integer (pc + 6, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 6, 2, byte_order_for_code);
/* movt Rd, #const */
if ((insn1 & 0xfbc0) == 0xf2c0)
else
{
unsigned int insn
- = read_memory_unsigned_integer (pc, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc, 4, byte_order_for_code);
if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */
{
low = EXTRACT_MOVW_MOVT_IMM_A (insn);
insn
- = read_memory_unsigned_integer (pc + 4, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc + 4, 4, byte_order_for_code);
if ((insn & 0x0ff00000) == 0x03400000) /* movt Rd, #const */
{
{
unsigned int destreg;
unsigned short insn
- = read_memory_unsigned_integer (pc + offset, 2, byte_order_for_code);
+ = read_code_unsigned_integer (pc + offset, 2, byte_order_for_code);
/* Step 2: ldr Rd, [Rn, #immed], encoding T1. */
if ((insn & 0xf800) != 0x6800)
return pc;
destreg = bits (insn, 0, 2);
- insn = read_memory_unsigned_integer (pc + offset + 2, 2,
- byte_order_for_code);
+ insn = read_code_unsigned_integer (pc + offset + 2, 2,
+ byte_order_for_code);
/* Step 3: str Rd, [Rn, #immed], encoding T1. */
if ((insn & 0xf800) != 0x6000)
return pc;
{
unsigned int destreg;
unsigned int insn
- = read_memory_unsigned_integer (pc + offset, 4, byte_order_for_code);
+ = read_code_unsigned_integer (pc + offset, 4, byte_order_for_code);
/* Step 2: ldr Rd, [Rn, #immed], encoding A1. */
if ((insn & 0x0e500000) != 0x04100000)
return pc;
destreg = bits (insn, 12, 15);
/* Step 3: str Rd, [Rn, #immed], encoding A1. */
- insn = read_memory_unsigned_integer (pc + offset + 4,
+ insn = read_code_unsigned_integer (pc + offset + 4,
4, byte_order_for_code);
if ((insn & 0x0e500000) != 0x04000000)
return pc;
int regno;
CORE_ADDR offset, current_pc;
pv_t regs[ARM_FPS_REGNUM];
- struct pv_area *stack;
- struct cleanup *back_to;
CORE_ADDR unrecognized_pc = 0;
/* Search the prologue looking for instructions that set up the
for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
regs[regno] = pv_register (regno, 0);
- stack = make_pv_area (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
- back_to = make_cleanup_free_pv_area (stack);
+ pv_area stack (ARM_SP_REGNUM, gdbarch_addr_bit (gdbarch));
for (current_pc = prologue_start;
current_pc < prologue_end;
current_pc += 4)
{
unsigned int insn
- = read_memory_unsigned_integer (current_pc, 4, byte_order_for_code);
+ = read_code_unsigned_integer (current_pc, 4, byte_order_for_code);
if (insn == 0xe1a0c00d) /* mov ip, sp */
{
else if ((insn & 0xffff0fff) == 0xe52d0004) /* str Rd,
[sp, #-4]! */
{
- if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ if (stack.store_would_trash (regs[ARM_SP_REGNUM]))
break;
regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -4);
- pv_area_store (stack, regs[ARM_SP_REGNUM], 4,
- regs[bits (insn, 12, 15)]);
+ stack.store (regs[ARM_SP_REGNUM], 4,
+ regs[bits (insn, 12, 15)]);
continue;
}
else if ((insn & 0xffff0000) == 0xe92d0000)
{
int mask = insn & 0xffff;
- if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ if (stack.store_would_trash (regs[ARM_SP_REGNUM]))
break;
/* Calculate offsets of saved registers. */
{
regs[ARM_SP_REGNUM]
= pv_add_constant (regs[ARM_SP_REGNUM], -4);
- pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
+ stack.store (regs[ARM_SP_REGNUM], 4, regs[regno]);
}
}
else if ((insn & 0xffff0000) == 0xe54b0000 /* strb rx,[r11,#-n] */
[sp, -#c]! */
&& gdbarch_tdep (gdbarch)->have_fpa_registers)
{
- if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ if (stack.store_would_trash (regs[ARM_SP_REGNUM]))
break;
regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
regno = ARM_F0_REGNUM + ((insn >> 12) & 0x07);
- pv_area_store (stack, regs[ARM_SP_REGNUM], 12, regs[regno]);
+ stack.store (regs[ARM_SP_REGNUM], 12, regs[regno]);
}
else if ((insn & 0xffbf0fff) == 0xec2d0200 /* sfmfd f0, 4,
[sp!] */
int n_saved_fp_regs;
unsigned int fp_start_reg, fp_bound_reg;
- if (pv_area_store_would_trash (stack, regs[ARM_SP_REGNUM]))
+ if (stack.store_would_trash (regs[ARM_SP_REGNUM]))
break;
if ((insn & 0x800) == 0x800) /* N0 is set */
for (; fp_start_reg < fp_bound_reg; fp_start_reg++)
{
regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -12);
- pv_area_store (stack, regs[ARM_SP_REGNUM], 12,
- regs[fp_start_reg++]);
+ stack.store (regs[ARM_SP_REGNUM], 12,
+ regs[fp_start_reg++]);
}
}
else if ((insn & 0xff000000) == 0xeb000000 && cache == NULL) /* bl */
cache->framesize = framesize;
for (regno = 0; regno < ARM_FPS_REGNUM; regno++)
- if (pv_area_find_reg (stack, gdbarch, regno, &offset))
+ if (stack.find_reg (gdbarch, regno, &offset))
cache->saved_regs[regno].addr = offset;
}
fprintf_unfiltered (gdb_stdlog, "Prologue scan stopped at %s\n",
paddress (gdbarch, unrecognized_pc));
- do_cleanups (back_to);
return unrecognized_pc;
}
the callee (or at the present moment if this is the innermost frame).
The value stored there should be the address of the stmfd + 8. */
CORE_ADDR frame_loc;
- LONGEST return_value;
+ ULONGEST return_value;
+
+ /* AAPCS does not use a frame register, so we can abort here. */
+ if (gdbarch_tdep (gdbarch)->arm_abi == ARM_ABI_AAPCS)
+ return;
frame_loc = get_frame_register_unsigned (this_frame, ARM_FP_REGNUM);
- if (!safe_read_memory_integer (frame_loc, 4, byte_order, &return_value))
+ if (!safe_read_memory_unsigned_integer (frame_loc, 4, byte_order,
+ &return_value))
return;
else
{
static void
arm_exidx_new_objfile (struct objfile *objfile)
{
- struct cleanup *cleanups;
struct arm_exidx_data *data;
asection *exidx, *extab;
bfd_vma exidx_vma = 0, extab_vma = 0;
- bfd_size_type exidx_size = 0, extab_size = 0;
- gdb_byte *exidx_data = NULL, *extab_data = NULL;
LONGEST i;
/* If we've already touched this file, do nothing. */
if (!objfile || objfile_data (objfile, arm_exidx_data_key) != NULL)
return;
- cleanups = make_cleanup (null_cleanup, NULL);
/* Read contents of exception table and index. */
exidx = bfd_get_section_by_name (objfile->obfd, ELF_STRING_ARM_unwind);
+ gdb::byte_vector exidx_data;
if (exidx)
{
exidx_vma = bfd_section_vma (objfile->obfd, exidx);
- exidx_size = bfd_get_section_size (exidx);
- exidx_data = (gdb_byte *) xmalloc (exidx_size);
- make_cleanup (xfree, exidx_data);
+ exidx_data.resize (bfd_get_section_size (exidx));
if (!bfd_get_section_contents (objfile->obfd, exidx,
- exidx_data, 0, exidx_size))
- {
- do_cleanups (cleanups);
- return;
- }
+ exidx_data.data (), 0,
+ exidx_data.size ()))
+ return;
}
extab = bfd_get_section_by_name (objfile->obfd, ".ARM.extab");
+ gdb::byte_vector extab_data;
if (extab)
{
extab_vma = bfd_section_vma (objfile->obfd, extab);
- extab_size = bfd_get_section_size (extab);
- extab_data = (gdb_byte *) xmalloc (extab_size);
- make_cleanup (xfree, extab_data);
+ extab_data.resize (bfd_get_section_size (extab));
if (!bfd_get_section_contents (objfile->obfd, extab,
- extab_data, 0, extab_size))
- {
- do_cleanups (cleanups);
- return;
- }
+ extab_data.data (), 0,
+ extab_data.size ()))
+ return;
}
/* Allocate exception table data structure. */
VEC(arm_exidx_entry_s) *);
/* Fill in exception table. */
- for (i = 0; i < exidx_size / 8; i++)
+ for (i = 0; i < exidx_data.size () / 8; i++)
{
struct arm_exidx_entry new_exidx_entry;
- bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8);
- bfd_vma val = bfd_h_get_32 (objfile->obfd, exidx_data + i * 8 + 4);
+ bfd_vma idx = bfd_h_get_32 (objfile->obfd, exidx_data.data () + i * 8);
+ bfd_vma val = bfd_h_get_32 (objfile->obfd,
+ exidx_data.data () + i * 8 + 4);
bfd_vma addr = 0, word = 0;
int n_bytes = 0, n_words = 0;
struct obj_section *sec;
addr = ((val & 0x7fffffff) ^ 0x40000000) - 0x40000000;
addr += exidx_vma + i * 8 + 4;
- if (addr >= extab_vma && addr + 4 <= extab_vma + extab_size)
+ if (addr >= extab_vma && addr + 4 <= extab_vma + extab_data.size ())
{
word = bfd_h_get_32 (objfile->obfd,
- extab_data + addr - extab_vma);
+ extab_data.data () + addr - extab_vma);
addr += 4;
if ((word & 0xff000000) == 0x80000000)
byte, followed by the same unwind instructions as the
pre-defined forms. */
if (gnu_personality
- && addr + 4 <= extab_vma + extab_size)
+ && addr + 4 <= extab_vma + extab_data.size ())
{
word = bfd_h_get_32 (objfile->obfd,
- extab_data + addr - extab_vma);
+ (extab_data.data ()
+ + addr - extab_vma));
addr += 4;
n_bytes = 3;
n_words = ((word >> 24) & 0xff);
/* Sanity check address. */
if (n_words)
- if (addr < extab_vma || addr + 4 * n_words > extab_vma + extab_size)
+ if (addr < extab_vma
+ || addr + 4 * n_words > extab_vma + extab_data.size ())
n_words = n_bytes = 0;
/* The unwind instructions reside in WORD (only the N_BYTES least
while (n_words--)
{
word = bfd_h_get_32 (objfile->obfd,
- extab_data + addr - extab_vma);
+ extab_data.data () + addr - extab_vma);
addr += 4;
*p++ = (gdb_byte) ((word >> 24) & 0xff);
data->section_maps[sec->the_bfd_section->index],
&new_exidx_entry);
}
-
- do_cleanups (cleanups);
}
/* Search for the exception table entry covering MEMADDR. If one is found,
ensure this, so that e.g. pthread cancellation works. */
if (arm_frame_is_thumb (this_frame))
{
- LONGEST insn;
+ ULONGEST insn;
- if (safe_read_memory_integer (get_frame_pc (this_frame) - 2, 2,
- byte_order_for_code, &insn)
+ if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 2,
+ 2, byte_order_for_code, &insn)
&& (insn & 0xff00) == 0xdf00 /* svc */)
exc_valid = 1;
}
else
{
- LONGEST insn;
+ ULONGEST insn;
- if (safe_read_memory_integer (get_frame_pc (this_frame) - 4, 4,
- byte_order_for_code, &insn)
+ if (safe_read_memory_unsigned_integer (get_frame_pc (this_frame) - 4,
+ 4, byte_order_for_code, &insn)
&& (insn & 0x0f000000) == 0x0f000000 /* svc */)
exc_valid = 1;
}
arm_normal_frame_base
};
-/* Assuming THIS_FRAME is a dummy, return the frame ID of that
- dummy frame. The frame ID's base needs to match the TOS value
- saved by save_dummy_frame_tos() and returned from
- arm_push_dummy_call, and the PC needs to match the dummy frame's
- breakpoint. */
-
-static struct frame_id
-arm_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
-{
- return frame_id_build (get_frame_register_unsigned (this_frame,
- ARM_SP_REGNUM),
- get_frame_pc (this_frame));
-}
-
-/* Given THIS_FRAME, find the previous frame's resume PC (which will
- be used to construct the previous frame's ID, after looking up the
- containing function). */
-
-static CORE_ADDR
-arm_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
-{
- CORE_ADDR pc;
- pc = frame_unwind_register_unsigned (this_frame, ARM_PC_REGNUM);
- return arm_addr_bits_remove (gdbarch, pc);
-}
-
-static CORE_ADDR
-arm_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame)
-{
- return frame_unwind_register_unsigned (this_frame, ARM_SP_REGNUM);
-}
-
static struct value *
arm_dwarf2_prev_register (struct frame_info *this_frame, void **this_cache,
int regnum)
case TYPE_CODE_SET:
case TYPE_CODE_RANGE:
case TYPE_CODE_REF:
+ case TYPE_CODE_RVALUE_REF:
case TYPE_CODE_CHAR:
case TYPE_CODE_BOOL:
return TYPE_LENGTH (t);
static CORE_ADDR
arm_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
- struct value **args, CORE_ADDR sp, int struct_return,
+ struct value **args, CORE_ADDR sp,
+ function_call_return_method return_method,
CORE_ADDR struct_addr)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* The struct_return pointer occupies the first parameter
passing register. */
- if (struct_return)
+ if (return_method == return_method_struct)
{
if (arm_debug)
fprintf_unfiltered (gdb_stdlog, "struct return in %s = %s\n",
reg_char, reg_scaled + i);
regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
strlen (name_buf));
- regcache_cooked_write (regcache, regnum,
- val + i * unit_length);
+ regcache->cooked_write (regnum, val + i * unit_length);
}
}
continue;
internal_error (__FILE__, __LINE__, _("Bad REGNUM %d"), regnum);
}
-/* NOTE: cagney/2001-08-20: Both convert_from_extended() and
- convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
- It is thought that this is is the floating-point register format on
- little-endian systems. */
-
-static void
-convert_from_extended (const struct floatformat *fmt, const void *ptr,
- void *dbl, int endianess)
-{
- DOUBLEST d;
-
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_to_doublest (&floatformat_arm_ext_big, ptr, &d);
- else
- floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword,
- ptr, &d);
- floatformat_from_doublest (fmt, &d, dbl);
-}
-
-static void
-convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr,
- int endianess)
-{
- DOUBLEST d;
-
- floatformat_to_doublest (fmt, ptr, &d);
- if (endianess == BFD_ENDIAN_BIG)
- floatformat_from_doublest (&floatformat_arm_ext_big, &d, dbl);
- else
- floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword,
- &d, dbl);
-}
-
-/* Like insert_single_step_breakpoint, but make sure we use a breakpoint
- of the appropriate mode (as encoded in the PC value), even if this
- differs from what would be expected according to the symbol tables. */
-
-void
-arm_insert_single_step_breakpoint (struct gdbarch *gdbarch,
- struct address_space *aspace,
- CORE_ADDR pc)
-{
- scoped_restore save_override_mode
- = make_scoped_restore (&arm_override_mode,
- (int) IS_THUMB_ADDR (pc));
- pc = gdbarch_addr_bits_remove (gdbarch, pc);
-
- insert_single_step_breakpoint (gdbarch, aspace, pc);
-}
-
/* Given BUF, which is OLD_LEN bytes ending at ENDADDR, expand
the buffer to be NEW_LEN bytes ending at ENDADDR. Return
NULL if an error occurs. BUF is freed. */
new_buf = (gdb_byte *) xmalloc (new_len);
memcpy (new_buf + bytes_to_read, buf, old_len);
xfree (buf);
- if (target_read_memory (endaddr - new_len, new_buf, bytes_to_read) != 0)
+ if (target_read_code (endaddr - new_len, new_buf, bytes_to_read) != 0)
{
xfree (new_buf);
return NULL;
return bpaddr;
buf = (gdb_byte *) xmalloc (buf_len);
- if (target_read_memory (bpaddr - buf_len, buf, buf_len) != 0)
+ if (target_read_code (bpaddr - buf_len, buf, buf_len) != 0)
return bpaddr;
any = 0;
for (i = 0; i < buf_len; i += 2)
location. */
ULONGEST
-displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
int regno)
{
ULONGEST ret;
displaced_in_arm_mode (struct regcache *regs)
{
ULONGEST ps;
- ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
+ ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ());
regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
/* Write to the PC as from a branch instruction. */
static void
-branch_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
+branch_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc,
ULONGEST val)
{
if (!dsc->is_thumb)
bx_write_pc (struct regcache *regs, ULONGEST val)
{
ULONGEST ps;
- ULONGEST t_bit = arm_psr_thumb_bit (get_regcache_arch (regs));
+ ULONGEST t_bit = arm_psr_thumb_bit (regs->arch ());
regcache_cooked_read_unsigned (regs, ARM_PS_REGNUM, &ps);
/* Write to the PC as if from a load instruction. */
static void
-load_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
+load_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc,
ULONGEST val)
{
if (DISPLACED_STEPPING_ARCH_VERSION >= 5)
/* Write to the PC as if from an ALU instruction. */
static void
-alu_write_pc (struct regcache *regs, struct displaced_step_closure *dsc,
+alu_write_pc (struct regcache *regs, arm_displaced_step_closure *dsc,
ULONGEST val)
{
if (DISPLACED_STEPPING_ARCH_VERSION >= 7 && !dsc->is_thumb)
this is controlled by the WRITE_PC argument. */
void
-displaced_write_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+displaced_write_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
int regno, ULONGEST val, enum pc_write_style write_pc)
{
if (regno == ARM_PC_REGNUM)
static int
arm_copy_unmodified (struct gdbarch *gdbarch, uint32_t insn,
- const char *iname, struct displaced_step_closure *dsc)
+ const char *iname, arm_displaced_step_closure *dsc)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.8lx, "
static int
thumb_copy_unmodified_32bit (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, const char *iname,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x %.4x, "
static int
thumb_copy_unmodified_16bit (struct gdbarch *gdbarch, uint16_t insn,
const char *iname,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog, "displaced: copying insn %.4x, "
static void
cleanup_preload (struct gdbarch *gdbarch,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
if (!dsc->u.preload.immed)
static void
install_preload (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc, unsigned int rn)
+ arm_displaced_step_closure *dsc, unsigned int rn)
{
ULONGEST rn_val;
/* Preload instructions:
static int
arm_copy_preload (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
static int
thumb2_copy_preload (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn1, 0, 3);
unsigned int u_bit = bit (insn1, 7);
static void
install_preload_reg(struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc, unsigned int rn,
+ arm_displaced_step_closure *dsc, unsigned int rn,
unsigned int rm)
{
ULONGEST rn_val, rm_val;
static int
arm_copy_preload_reg (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
unsigned int rm = bits (insn, 0, 3);
static void
cleanup_copro_load_store (struct gdbarch *gdbarch,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
ULONGEST rn_val = displaced_read_reg (regs, dsc, 0);
static void
install_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
int writeback, unsigned int rn)
{
ULONGEST rn_val;
static int
arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
static int
thumb2_copy_copro_load_store (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn1, 0, 3);
static void
cleanup_branch (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
int branch_taken = condition_true (dsc->u.branch.cond, status);
static void
install_b_bl_blx (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
unsigned int cond, int exchange, int link, long offset)
{
/* Implement "BL<cond> <label>" as:
}
static int
arm_copy_b_bl_blx (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
unsigned int cond = bits (insn, 28, 31);
int exchange = (cond == 0xf);
static int
thumb2_copy_b_bl_blx (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int link = bit (insn2, 14);
int exchange = link && !bit (insn2, 12);
/* Copy B Thumb instructions. */
static int
thumb_copy_b (struct gdbarch *gdbarch, uint16_t insn,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int cond = 0;
int offset = 0;
static void
install_bx_blx_reg (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc, int link,
+ arm_displaced_step_closure *dsc, int link,
unsigned int cond, unsigned int rm)
{
/* Implement {BX,BLX}<cond> <reg>" as:
static int
arm_copy_bx_blx_reg (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
unsigned int cond = bits (insn, 28, 31);
/* BX: x12xxx1x
static int
thumb_copy_bx_blx_reg (struct gdbarch *gdbarch, uint16_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int link = bit (insn, 7);
unsigned int rm = bits (insn, 3, 6);
static void
cleanup_alu_imm (struct gdbarch *gdbarch,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
displaced_write_reg (regs, dsc, 0, dsc->tmp[0], CANNOT_WRITE_PC);
static int
arm_copy_alu_imm (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rn = bits (insn, 16, 19);
unsigned int rd = bits (insn, 12, 15);
static int
thumb2_copy_alu_imm (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int op = bits (insn1, 5, 8);
unsigned int rn, rm, rd;
static void
cleanup_alu_reg (struct gdbarch *gdbarch,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
ULONGEST rd_val;
int i;
static void
install_alu_reg (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
unsigned int rd, unsigned int rn, unsigned int rm)
{
ULONGEST rd_val, rn_val, rm_val;
static int
arm_copy_alu_reg (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int op = bits (insn, 21, 24);
int is_mov = (op == 0xd);
static int
thumb_copy_alu_reg (struct gdbarch *gdbarch, uint16_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned rm, rd;
static void
cleanup_alu_shifted_reg (struct gdbarch *gdbarch,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
ULONGEST rd_val = displaced_read_reg (regs, dsc, 0);
int i;
static void
install_alu_shifted_reg (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
unsigned int rd, unsigned int rn, unsigned int rm,
unsigned rs)
{
static int
arm_copy_alu_shifted_reg (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int op = bits (insn, 21, 24);
int is_mov = (op == 0xd);
static void
cleanup_load (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
ULONGEST rt_val, rt_val2 = 0, rn_val;
static void
cleanup_store (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
ULONGEST rn_val = displaced_read_reg (regs, dsc, 2);
static int
arm_copy_extra_ld_st (struct gdbarch *gdbarch, uint32_t insn, int unprivileged,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
unsigned int op1 = bits (insn, 20, 24);
unsigned int op2 = bits (insn, 5, 6);
static void
install_load_store (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc, int load,
+ arm_displaced_step_closure *dsc, int load,
int immed, int writeback, int size, int usermode,
int rt, int rm, int rn)
{
static int
thumb2_copy_load_literal (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc, int size)
+ arm_displaced_step_closure *dsc, int size)
{
unsigned int u_bit = bit (insn1, 7);
unsigned int rt = bits (insn2, 12, 15);
static int
thumb2_copy_load_reg_imm (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
int writeback, int immed)
{
unsigned int rt = bits (insn2, 12, 15);
static int
arm_copy_ldr_str_ldrb_strb (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
int load, int size, int usermode)
{
int immed = !bit (insn, 25);
static void
cleanup_block_load_all (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int inc = dsc->u.block.increment;
int bump_before = dsc->u.block.before ? (inc ? 4 : -4) : 0;
static void
cleanup_block_store_pc (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
int store_executed = condition_true (dsc->u.block.cond, status);
static void
cleanup_block_load_pc (struct gdbarch *gdbarch,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
uint32_t status = displaced_read_reg (regs, dsc, ARM_PS_REGNUM);
int load_executed = condition_true (dsc->u.block.cond, status);
static int
arm_copy_block_xfer (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int load = bit (insn, 20);
int user = bit (insn, 22);
static int
thumb2_copy_block_xfer (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int rn = bits (insn1, 0, 3);
int load = bit (insn1, 4);
arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
CORE_ADDR val)
{
- return gdbarch_addr_bits_remove (get_regcache_arch (self->regcache), val);
+ return gdbarch_addr_bits_remove (self->regcache->arch (), val);
}
/* Wrapper over syscall_next_pc for use in get_next_pcs. */
single-step support. We find the target of the coming instructions
and breakpoint them. */
-int
-arm_software_single_step (struct frame_info *frame)
+std::vector<CORE_ADDR>
+arm_software_single_step (struct regcache *regcache)
{
- struct regcache *regcache = get_current_regcache ();
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
- struct address_space *aspace = get_regcache_aspace (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
-
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
- arm_insert_single_step_breakpoint (gdbarch, aspace, pc);
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
- do_cleanups (old_chain);
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
- return 1;
+ return next_pcs;
}
/* Cleanup/copy SVC (SWI) instructions. These two functions are overridden
static void
cleanup_svc (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
CORE_ADDR resume_addr = dsc->insn_addr + dsc->insn_size;
static int
install_svc (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
/* Preparation: none.
Insn: unmodified svc.
static int
arm_copy_svc (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
if (debug_displaced)
static int
thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
if (debug_displaced)
static int
arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog,
static int
thumb_32bit_copy_undef (struct gdbarch *gdbarch, uint16_t insn1, uint16_t insn2,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (debug_displaced)
static int
arm_copy_unpred (struct gdbarch *gdbarch, uint32_t insn,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (debug_displaced)
fprintf_unfiltered (gdb_stdlog, "displaced: copying unpredictable insn "
static int
arm_decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int op1 = bits (insn, 20, 26), op2 = bits (insn, 4, 7);
unsigned int rn = bits (insn, 16, 19);
- if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0xe) == 0x0)
+ if (op1 == 0x10 && (op2 & 0x2) == 0x0 && (rn & 0x1) == 0x0)
return arm_copy_unmodified (gdbarch, insn, "cps", dsc);
- else if (op1 == 0x10 && op2 == 0x0 && (rn & 0xe) == 0x1)
+ else if (op1 == 0x10 && op2 == 0x0 && (rn & 0x1) == 0x1)
return arm_copy_unmodified (gdbarch, insn, "setend", dsc);
else if ((op1 & 0x60) == 0x20)
return arm_copy_unmodified (gdbarch, insn, "neon dataproc", dsc);
static int
arm_decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (bit (insn, 27) == 0)
return arm_decode_misc_memhint_neon (gdbarch, insn, regs, dsc);
static int
arm_decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int op2 = bits (insn, 4, 6);
unsigned int op = bits (insn, 21, 22);
else if (op == 0x3)
/* Not really supported. */
return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
+ /* Fall through. */
default:
return arm_copy_undef (gdbarch, insn, dsc);
static int
arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (bit (insn, 25))
switch (bits (insn, 20, 24))
static int
arm_decode_ld_st_word_ubyte (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int a = bit (insn, 25), b = bit (insn, 4);
uint32_t op1 = bits (insn, 20, 24);
static int
arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
switch (bits (insn, 20, 24))
{
static int
arm_decode_b_bl_ldmstm (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
if (bit (insn, 25))
return arm_copy_b_bl_blx (gdbarch, insn, regs, dsc);
static int
arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int opcode = bits (insn, 20, 24);
static int
thumb2_decode_dp_shift_reg (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
/* PC is only allowed to be used in instruction MOV. */
static int
thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int opcode = bits (insn1, 4, 8);
static int
arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn,
- struct regcache *regs, struct displaced_step_closure *dsc)
+ struct regcache *regs, arm_displaced_step_closure *dsc)
{
unsigned int op1 = bits (insn, 20, 25);
int op = bit (insn, 4);
static int
thumb2_decode_svc_copro (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int coproc = bits (insn2, 8, 11);
unsigned int bit_5_8 = bits (insn1, 5, 8);
static void
install_pc_relative (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc, int rd)
+ arm_displaced_step_closure *dsc, int rd)
{
/* ADR Rd, #imm
static int
thumb_copy_pc_relative_16bit (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc,
+ arm_displaced_step_closure *dsc,
int rd, unsigned int imm)
{
static int
thumb_decode_pc_relative_16bit (struct gdbarch *gdbarch, uint16_t insn,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rd = bits (insn, 8, 10);
unsigned int imm8 = bits (insn, 0, 7);
static int
thumb_copy_pc_relative_32bit (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rd = bits (insn2, 8, 11);
/* Since immediate has the same encoding in ADR ADD and SUB, so we simply
static int
thumb_copy_16bit_ldr_literal (struct gdbarch *gdbarch, uint16_t insn1,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned int rt = bits (insn1, 8, 10);
unsigned int pc;
static int
thumb_copy_cbnz_cbz (struct gdbarch *gdbarch, uint16_t insn1,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int non_zero = bit (insn1, 11);
unsigned int imm5 = (bit (insn1, 9) << 6) | (bits (insn1, 3, 7) << 1);
static int
thumb2_copy_table_branch (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
ULONGEST rn_val, rm_val;
int is_tbh = bit (insn2, 4);
static void
cleanup_pop_pc_16bit_all (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
/* PC <- r7 */
int val = displaced_read_reg (regs, dsc, 7);
static int
thumb_copy_pop_pc_16bit (struct gdbarch *gdbarch, uint16_t insn1,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
dsc->u.block.regmask = insn1 & 0x00ff;
static void
thumb_process_displaced_16bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
unsigned short op_bit_12_15 = bits (insn1, 12, 15);
unsigned short op_bit_10_11 = bits (insn1, 10, 11);
decode_thumb_32bit_ld_mem_hints (struct gdbarch *gdbarch,
uint16_t insn1, uint16_t insn2,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int rt = bits (insn2, 12, 15);
int rn = bits (insn1, 0, 3);
static void
thumb_process_displaced_32bit_insn (struct gdbarch *gdbarch, uint16_t insn1,
uint16_t insn2, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int err = 0;
unsigned short op = bit (insn2, 15);
{
if (bit (insn1, 9)) /* Data processing (plain binary imm). */
{
- int op = bits (insn1, 4, 8);
+ int dp_op = bits (insn1, 4, 8);
int rn = bits (insn1, 0, 3);
- if ((op == 0 || op == 0xa) && rn == 0xf)
+ if ((dp_op == 0 || dp_op == 0xa) && rn == 0xf)
err = thumb_copy_pc_relative_32bit (gdbarch, insn1, insn2,
regs, dsc);
else
static void
thumb_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
uint16_t insn1
void
arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
CORE_ADDR to, struct regcache *regs,
- struct displaced_step_closure *dsc)
+ arm_displaced_step_closure *dsc)
{
int err = 0;
enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
void
arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
- CORE_ADDR to, struct displaced_step_closure *dsc)
+ CORE_ADDR to, arm_displaced_step_closure *dsc)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
unsigned int i, len, offset;
void
arm_displaced_step_fixup (struct gdbarch *gdbarch,
- struct displaced_step_closure *dsc,
+ struct displaced_step_closure *dsc_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
+ arm_displaced_step_closure *dsc = (arm_displaced_step_closure *) dsc_;
+
if (dsc->cleanup)
dsc->cleanup (gdbarch, regs, dsc);
static int
gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info)
{
- struct gdbarch *gdbarch = (struct gdbarch *) info->application_data;
+ gdb_disassembler *di
+ = static_cast<gdb_disassembler *>(info->application_data);
+ struct gdbarch *gdbarch = di->arch ();
if (arm_pc_is_thumb (gdbarch, memaddr))
{
else
info->symbols = NULL;
- if (info->endian == BFD_ENDIAN_BIG)
- return print_insn_big_arm (memaddr, info);
- else
- return print_insn_little_arm (memaddr, info);
+ /* GDB is able to get bfd_mach from the exe_bfd, info->mach is
+ accurate, so mark USER_SPECIFIED_MACHINE_TYPE bit. Otherwise,
+ opcodes/arm-dis.c:print_insn reset info->mach, and it will trigger
+ the assert on the mismatch of info->mach and bfd_get_mach (exec_bfd)
+ in default_print_insn. */
+ if (exec_bfd != NULL)
+ info->flags |= USER_SPECIFIED_MACHINE_TYPE;
+
+ return default_print_insn (memaddr, info);
}
/* The following define instruction sequences that will cause ARM
static const gdb_byte arm_default_thumb_le_breakpoint[] = THUMB_LE_BREAKPOINT;
static const gdb_byte arm_default_thumb_be_breakpoint[] = THUMB_BE_BREAKPOINT;
+/* Implement the breakpoint_kind_from_pc gdbarch method. */
+
static int
arm_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
{
}
+/* Implement the sw_breakpoint_from_kind gdbarch method. */
+
static const gdb_byte *
arm_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
{
}
}
-/* Determine the type and size of breakpoint to insert at PCPTR. Uses
- the program counter value to determine whether a 16-bit or 32-bit
- breakpoint should be used. It returns a pointer to a string of
- bytes that encode a breakpoint instruction, stores the length of
- the string to *lenptr, and adjusts the program counter (if
- necessary) to point to the actual memory location where the
- breakpoint should be inserted. */
-
-GDBARCH_BREAKPOINT_FROM_PC (arm)
+/* Implement the breakpoint_kind_from_current_state gdbarch method. */
-static void
-arm_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
- int *kindptr)
+static int
+arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
+ struct regcache *regcache,
+ CORE_ADDR *pcptr)
{
+ gdb_byte buf[4];
- *kindptr = arm_breakpoint_kind_from_pc (gdbarch, pcptr);
+ /* Check the memory pointed by PC is readable. */
+ if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
+ {
+ struct arm_get_next_pcs next_pcs_ctx;
+
+ arm_get_next_pcs_ctor (&next_pcs_ctx,
+ &arm_get_next_pcs_ops,
+ gdbarch_byte_order (gdbarch),
+ gdbarch_byte_order_for_code (gdbarch),
+ 0,
+ regcache);
+
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
+
+ /* If MEMADDR is the next instruction of current pc, do the
+ software single step computation, and get the thumb mode by
+ the destination address. */
+ for (CORE_ADDR pc : next_pcs)
+ {
+ if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
+ {
+ if (IS_THUMB_ADDR (pc))
+ {
+ *pcptr = MAKE_THUMB_ADDR (*pcptr);
+ return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
+ }
+ else
+ return ARM_BP_KIND_ARM;
+ }
+ }
+ }
+
+ return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
}
/* Extract from an array REGBUF containing the (raw) register state a
arm_extract_return_value (struct type *type, struct regcache *regs,
gdb_byte *valbuf)
{
- struct gdbarch *gdbarch = get_regcache_arch (regs);
+ struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
if (TYPE_CODE_FLT == TYPE_CODE (type))
internal type. */
bfd_byte tmpbuf[FP_REGISTER_SIZE];
- regcache_cooked_read (regs, ARM_F0_REGNUM, tmpbuf);
- convert_from_extended (floatformat_from_type (type), tmpbuf,
- valbuf, gdbarch_byte_order (gdbarch));
+ regs->cooked_read (ARM_F0_REGNUM, tmpbuf);
+ target_float_convert (tmpbuf, arm_ext_type (gdbarch),
+ valbuf, type);
}
break;
/* ARM_FLOAT_VFP can arise if this is a variadic function so
not using the VFP ABI code. */
case ARM_FLOAT_VFP:
- regcache_cooked_read (regs, ARM_A1_REGNUM, valbuf);
+ regs->cooked_read (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regcache_cooked_read (regs, ARM_A1_REGNUM + 1,
- valbuf + INT_REGISTER_SIZE);
+ regs->cooked_read (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
break;
default:
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
/* If the type is a plain integer, then the access is
while (len > 0)
{
- regcache_cooked_read (regs, regno++, tmpbuf);
+ regs->cooked_read (regno++, tmpbuf);
memcpy (valbuf, tmpbuf,
len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
len -= INT_REGISTER_SIZE;
arm_store_return_value (struct type *type, struct regcache *regs,
const gdb_byte *valbuf)
{
- struct gdbarch *gdbarch = get_regcache_arch (regs);
+ struct gdbarch *gdbarch = regs->arch ();
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
if (TYPE_CODE (type) == TYPE_CODE_FLT)
{
- gdb_byte buf[MAX_REGISTER_SIZE];
+ gdb_byte buf[FP_REGISTER_SIZE];
switch (gdbarch_tdep (gdbarch)->fp_model)
{
case ARM_FLOAT_FPA:
- convert_to_extended (floatformat_from_type (type), buf, valbuf,
- gdbarch_byte_order (gdbarch));
- regcache_cooked_write (regs, ARM_F0_REGNUM, buf);
+ target_float_convert (valbuf, type, buf, arm_ext_type (gdbarch));
+ regs->cooked_write (ARM_F0_REGNUM, buf);
break;
case ARM_FLOAT_SOFT_FPA:
/* ARM_FLOAT_VFP can arise if this is a variadic function so
not using the VFP ABI code. */
case ARM_FLOAT_VFP:
- regcache_cooked_write (regs, ARM_A1_REGNUM, valbuf);
+ regs->cooked_write (ARM_A1_REGNUM, valbuf);
if (TYPE_LENGTH (type) > 4)
- regcache_cooked_write (regs, ARM_A1_REGNUM + 1,
- valbuf + INT_REGISTER_SIZE);
+ regs->cooked_write (ARM_A1_REGNUM + 1, valbuf + INT_REGISTER_SIZE);
break;
default:
|| TYPE_CODE (type) == TYPE_CODE_CHAR
|| TYPE_CODE (type) == TYPE_CODE_BOOL
|| TYPE_CODE (type) == TYPE_CODE_PTR
- || TYPE_CODE (type) == TYPE_CODE_REF
+ || TYPE_IS_REFERENCE (type)
|| TYPE_CODE (type) == TYPE_CODE_ENUM)
{
if (TYPE_LENGTH (type) <= 4)
LONGEST val = unpack_long (type, valbuf);
store_signed_integer (tmpbuf, INT_REGISTER_SIZE, byte_order, val);
- regcache_cooked_write (regs, ARM_A1_REGNUM, tmpbuf);
+ regs->cooked_write (ARM_A1_REGNUM, tmpbuf);
}
else
{
while (len > 0)
{
- regcache_cooked_write (regs, regno++, valbuf);
+ regs->cooked_write (regno++, valbuf);
len -= INT_REGISTER_SIZE;
valbuf += INT_REGISTER_SIZE;
}
{
memcpy (tmpbuf, valbuf,
len > INT_REGISTER_SIZE ? INT_REGISTER_SIZE : len);
- regcache_cooked_write (regs, regno++, tmpbuf);
+ regs->cooked_write (regno++, tmpbuf);
len -= INT_REGISTER_SIZE;
valbuf += INT_REGISTER_SIZE;
}
regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
strlen (name_buf));
if (writebuf)
- regcache_cooked_write (regcache, regnum,
- writebuf + i * unit_length);
+ regcache->cooked_write (regnum, writebuf + i * unit_length);
if (readbuf)
- regcache_cooked_read (regcache, regnum,
- readbuf + i * unit_length);
+ regcache->cooked_read (regnum, readbuf + i * unit_length);
}
}
return RETURN_VALUE_REGISTER_CONVENTION;
{
/* Use the name suffix to determine which register contains the
target PC. */
- static char *table[15] =
+ static const char *table[15] =
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "sl", "fp", "ip", "sp", "lr"
};
}
static void
-set_arm_command (char *args, int from_tty)
+set_arm_command (const char *args, int from_tty)
{
printf_unfiltered (_("\
\"set arm\" must be followed by an apporpriate subcommand.\n"));
}
static void
-show_arm_command (char *args, int from_tty)
+show_arm_command (const char *args, int from_tty)
{
cmd_show_list (showarmcmdlist, from_tty, "");
}
}
static void
-set_fp_model_sfunc (char *args, int from_tty,
+set_fp_model_sfunc (const char *args, int from_tty,
struct cmd_list_element *c)
{
int fp_model;
}
static void
-arm_set_abi (char *args, int from_tty,
+arm_set_abi (const char *args, int from_tty,
struct cmd_list_element *c)
{
int arm_abi;
arm disassembly" command, and does that. */
static void
-set_disassembly_style_sfunc (char *args, int from_tty,
- struct cmd_list_element *c)
+set_disassembly_style_sfunc (const char *args, int from_tty,
+ struct cmd_list_element *c)
+{
+ /* Convert the short style name into the long style name (eg, reg-names-*)
+ before calling the generic set_disassembler_options() function. */
+ std::string long_name = std::string ("reg-names-") + disassembly_style;
+ set_disassembler_options (&long_name[0]);
+}
+
+static void
+show_disassembly_style_sfunc (struct ui_file *file, int from_tty,
+ struct cmd_list_element *c, const char *value)
{
- set_disassembly_style ();
+ struct gdbarch *gdbarch = get_current_arch ();
+ char *options = get_disassembler_options (gdbarch);
+ const char *style = "";
+ int len = 0;
+ const char *opt;
+
+ FOR_EACH_DISASSEMBLER_OPTION (opt, options)
+ if (CONST_STRNEQ (opt, "reg-names-"))
+ {
+ style = &opt[strlen ("reg-names-")];
+ len = strcspn (style, ",");
+ }
+
+ fprintf_unfiltered (file, "The disassembly style is \"%.*s\".\n", len, style);
}
\f
/* Return the ARM register name corresponding to register I. */
return arm_register_names[i];
}
-static void
-set_disassembly_style (void)
-{
- int current;
-
- /* Find the style that the user wants. */
- for (current = 0; current < num_disassembly_options; current++)
- if (disassembly_style == valid_disassembly_styles[current])
- break;
- gdb_assert (current < num_disassembly_options);
-
- /* Synchronize the disassembler. */
- set_arm_regname_option (current);
-}
-
/* Test whether the coff symbol specific value corresponds to a Thumb
function. */
static void
arm_write_pc (struct regcache *regcache, CORE_ADDR pc)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
regcache_cooked_write_unsigned (regcache, ARM_PC_REGNUM, pc);
/* If necessary, set the T bit. */
the quad register, in [0, 15]. */
static enum register_status
-arm_neon_quad_read (struct gdbarch *gdbarch, struct regcache *regcache,
+arm_neon_quad_read (struct gdbarch *gdbarch, readable_regcache *regcache,
int regnum, gdb_byte *buf)
{
char name_buf[4];
else
offset = 0;
- status = regcache_raw_read (regcache, double_regnum, reg_buf);
+ status = regcache->raw_read (double_regnum, reg_buf);
if (status != REG_VALID)
return status;
memcpy (buf + offset, reg_buf, 8);
offset = 8 - offset;
- status = regcache_raw_read (regcache, double_regnum + 1, reg_buf);
+ status = regcache->raw_read (double_regnum + 1, reg_buf);
if (status != REG_VALID)
return status;
memcpy (buf + offset, reg_buf, 8);
}
static enum register_status
-arm_pseudo_read (struct gdbarch *gdbarch, struct regcache *regcache,
+arm_pseudo_read (struct gdbarch *gdbarch, readable_regcache *regcache,
int regnum, gdb_byte *buf)
{
const int num_regs = gdbarch_num_regs (gdbarch);
double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
strlen (name_buf));
- status = regcache_raw_read (regcache, double_regnum, reg_buf);
+ status = regcache->raw_read (double_regnum, reg_buf);
if (status == REG_VALID)
memcpy (buf, reg_buf + offset, 4);
return status;
else
offset = 0;
- regcache_raw_write (regcache, double_regnum, buf + offset);
+ regcache->raw_write (double_regnum, buf + offset);
offset = 8 - offset;
- regcache_raw_write (regcache, double_regnum + 1, buf + offset);
+ regcache->raw_write (double_regnum + 1, buf + offset);
}
static void
double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf,
strlen (name_buf));
- regcache_raw_read (regcache, double_regnum, reg_buf);
+ regcache->raw_read (double_regnum, reg_buf);
memcpy (reg_buf + offset, buf, 4);
- regcache_raw_write (regcache, double_regnum, reg_buf);
+ regcache->raw_write (double_regnum, reg_buf);
}
}
switch (bfd_get_flavour (info.abfd))
{
- case bfd_target_aout_flavour:
- /* Assume it's an old APCS-style ABI. */
- arm_abi = ARM_ABI_APCS;
- break;
-
case bfd_target_coff_flavour:
/* Assume it's an old APCS-style ABI. */
/* XXX WinCE? */
else if (ei_osabi == ELFOSABI_NONE || ei_osabi == ELFOSABI_GNU)
{
int eabi_ver = EF_ARM_EABI_VERSION (e_flags);
- int attr_arch, attr_profile;
switch (eabi_ver)
{
executable file includes build attributes; GCC does
copy them to the executable, but e.g. RealView does
not. */
- attr_arch = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
- Tag_CPU_arch);
- attr_profile = bfd_elf_get_obj_attr_int (info.abfd,
- OBJ_ATTR_PROC,
- Tag_CPU_arch_profile);
+ int attr_arch
+ = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
+ Tag_CPU_arch);
+ int attr_profile
+ = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_PROC,
+ Tag_CPU_arch_profile);
+
/* GCC specifies the profile for v6-M; RealView only
specifies the profile for architectures starting with
V7 (as opposed to architectures with a tag
if (fp_model == ARM_FLOAT_AUTO)
{
- int e_flags = elf_elfheader (info.abfd)->e_flags;
-
switch (e_flags & (EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT))
{
case 0:
/* On ARM targets char defaults to unsigned. */
set_gdbarch_char_signed (gdbarch, 0);
+ /* wchar_t is unsigned under the AAPCS. */
+ if (tdep->arm_abi == ARM_ABI_AAPCS)
+ set_gdbarch_wchar_signed (gdbarch, 0);
+ else
+ set_gdbarch_wchar_signed (gdbarch, 1);
+
/* Note: for displaced stepping, this includes the breakpoint, and one word
of additional scratch space. This setting isn't used for anything beside
displaced stepping at present. */
set_gdbarch_write_pc (gdbarch, arm_write_pc);
- /* Frame handling. */
- set_gdbarch_dummy_id (gdbarch, arm_dummy_id);
- set_gdbarch_unwind_pc (gdbarch, arm_unwind_pc);
- set_gdbarch_unwind_sp (gdbarch, arm_unwind_sp);
-
frame_base_set_default (gdbarch, &arm_normal_base);
/* Address manipulation. */
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
/* Breakpoint manipulation. */
- SET_GDBARCH_BREAKPOINT_MANIPULATION (arm);
- set_gdbarch_remote_breakpoint_from_pc (gdbarch,
- arm_remote_breakpoint_from_pc);
+ set_gdbarch_breakpoint_kind_from_pc (gdbarch, arm_breakpoint_kind_from_pc);
+ set_gdbarch_sw_breakpoint_from_kind (gdbarch, arm_sw_breakpoint_from_kind);
+ set_gdbarch_breakpoint_kind_from_current_state (gdbarch,
+ arm_breakpoint_kind_from_current_state);
/* Information about registers, etc. */
set_gdbarch_sp_regnum (gdbarch, ARM_SP_REGNUM);
user_reg_add (gdbarch, arm_register_aliases[i].name,
value_of_arm_user_reg, &arm_register_aliases[i].regnum);
+ set_gdbarch_disassembler_options (gdbarch, &arm_disassembler_options);
+ set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_arm ());
+
return gdbarch;
}
(unsigned long) tdep->lowest_pc);
}
-extern initialize_file_ftype _initialize_arm_tdep; /* -Wmissing-prototypes */
+#if GDB_SELF_TEST
+namespace selftests
+{
+static void arm_record_test (void);
+}
+#endif
void
_initialize_arm_tdep (void)
{
- struct ui_file *stb;
long length;
- const char *setname;
- const char *setdesc;
- const char *const *regnames;
- int i;
- static char *helptext;
+ int i, j;
char regdesc[1024], *rdptr = regdesc;
size_t rest = sizeof (regdesc);
= register_objfile_data_with_cleanup (NULL, arm_objfile_data_free);
/* Add ourselves to objfile event chain. */
- observer_attach_new_objfile (arm_exidx_new_objfile);
+ gdb::observers::new_objfile.attach (arm_exidx_new_objfile);
arm_exidx_data_key
= register_objfile_data_with_cleanup (NULL, arm_exidx_data_free);
initialize_tdesc_arm_with_vfpv3 ();
initialize_tdesc_arm_with_neon ();
- /* Get the number of possible sets of register names defined in opcodes. */
- num_disassembly_options = get_arm_regname_num_options ();
-
/* Add root prefix command for all "set arm"/"show arm" commands. */
add_prefix_cmd ("arm", no_class, set_arm_command,
_("Various ARM-specific commands."),
_("Various ARM-specific commands."),
&showarmcmdlist, "show arm ", 0, &showlist);
- /* Sync the opcode insn printer with our register viewer. */
- parse_arm_disassembler_option ("reg-names-std");
- /* Initialize the array that will be passed to
- add_setshow_enum_cmd(). */
+ arm_disassembler_options = xstrdup ("reg-names-std");
+ const disasm_options_t *disasm_options
+ = &disassembler_options_arm ()->options;
+ int num_disassembly_styles = 0;
+ for (i = 0; disasm_options->name[i] != NULL; i++)
+ if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
+ num_disassembly_styles++;
+
+ /* Initialize the array that will be passed to add_setshow_enum_cmd(). */
valid_disassembly_styles = XNEWVEC (const char *,
- num_disassembly_options + 1);
- for (i = 0; i < num_disassembly_options; i++)
- {
- get_arm_regnames (i, &setname, &setdesc, ®names);
- valid_disassembly_styles[i] = setname;
- length = snprintf (rdptr, rest, "%s - %s\n", setname, setdesc);
- rdptr += length;
- rest -= length;
- /* When we find the default names, tell the disassembler to use
- them. */
- if (!strcmp (setname, "std"))
- {
- disassembly_style = setname;
- set_arm_regname_option (i);
- }
- }
+ num_disassembly_styles + 1);
+ for (i = j = 0; disasm_options->name[i] != NULL; i++)
+ if (CONST_STRNEQ (disasm_options->name[i], "reg-names-"))
+ {
+ size_t offset = strlen ("reg-names-");
+ const char *style = disasm_options->name[i];
+ valid_disassembly_styles[j++] = &style[offset];
+ length = snprintf (rdptr, rest, "%s - %s\n", &style[offset],
+ disasm_options->description[i]);
+ rdptr += length;
+ rest -= length;
+ }
/* Mark the end of valid options. */
- valid_disassembly_styles[num_disassembly_options] = NULL;
+ valid_disassembly_styles[num_disassembly_styles] = NULL;
/* Create the help text. */
- stb = mem_fileopen ();
- fprintf_unfiltered (stb, "%s%s%s",
- _("The valid values are:\n"),
- regdesc,
- _("The default is \"std\"."));
- helptext = ui_file_xstrdup (stb, NULL);
- ui_file_delete (stb);
+ std::string helptext = string_printf ("%s%s%s",
+ _("The valid values are:\n"),
+ regdesc,
+ _("The default is \"std\"."));
add_setshow_enum_cmd("disassembler", no_class,
valid_disassembly_styles, &disassembly_style,
_("Set the disassembly style."),
_("Show the disassembly style."),
- helptext,
+ helptext.c_str (),
set_disassembly_style_sfunc,
- NULL, /* FIXME: i18n: The disassembly style is
- \"%s\". */
+ show_disassembly_style_sfunc,
&setarmcmdlist, &showarmcmdlist);
add_setshow_boolean_cmd ("apcs32", no_class, &arm_apcs_32,
NULL,
NULL, /* FIXME: i18n: "ARM debugging is %s. */
&setdebuglist, &showdebuglist);
+
+#if GDB_SELF_TEST
+ selftests::register_test ("arm-record", selftests::arm_record_test);
+#endif
+
}
/* ARM-reversible process record data structures. */
static int
arm_record_extension_space (insn_decode_record *arm_insn_r)
{
- uint32_t ret = 0; /* Return value: -1:record failure ; 0:success */
+ int ret = 0; /* Return value: -1:record failure ; 0:success */
uint32_t opcode1 = 0, opcode2 = 0, insn_op1 = 0;
uint32_t record_buf[8], record_buf_mem[8];
uint32_t reg_src1 = 0;
&& !INSN_RECORDED(arm_insn_r))
{
/* Handle MLA(S) and MUL(S). */
- if (0 <= insn_op1 && 3 >= insn_op1)
+ if (in_inclusive_range (insn_op1, 0U, 3U))
{
record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
record_buf[1] = ARM_PS_REGNUM;
arm_insn_r->reg_rec_count = 2;
}
- else if (4 <= insn_op1 && 15 >= insn_op1)
+ else if (in_inclusive_range (insn_op1, 4U, 15U))
{
/* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
uint32_t record_buf[8], record_buf_mem[8];
ULONGEST u_regval[2] = {0};
- uint32_t reg_src1 = 0, reg_dest = 0;
+ uint32_t reg_src1 = 0;
uint32_t opcode1 = 0;
arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24);
arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7);
opcode1 = bits (arm_insn_r->arm_insn, 20, 24);
- /* Data processing insn /multiply insn. */
- if (9 == arm_insn_r->decode
- && ((4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
- || (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)))
+ if (!((opcode1 & 0x19) == 0x10))
{
- /* Handle multiply instructions. */
- /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
- if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
- {
- /* Handle MLA and MUL. */
- record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
- record_buf[1] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 2;
- }
- else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
- {
- /* Handle SMLAL, SMULL, UMLAL, UMULL. */
- record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
- record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
- record_buf[2] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 3;
- }
+ /* Data-processing (register) and Data-processing (register-shifted
+ register */
+ /* Out of 11 shifter operands mode, all the insn modifies destination
+ register, which is specified by 13-16 decode. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[1] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
}
- else if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
- && (11 == arm_insn_r->decode || 13 == arm_insn_r->decode))
+ else if ((arm_insn_r->decode < 8) && ((opcode1 & 0x19) == 0x10))
{
- /* Handle misc load insns, as 20th bit (L = 1). */
- /* LDR insn has a capability to do branching, if
- MOV LR, PC is precceded by LDR insn having Rn as R15
- in that case, it emulates branch and link insn, and hence we
- need to save CSPR and PC as well. I am not sure this is right
- place; as opcode = 010 LDR insn make this happen, if R15 was
- used. */
- reg_dest = bits (arm_insn_r->arm_insn, 12, 15);
- if (15 != reg_dest)
- {
- record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
- arm_insn_r->reg_rec_count = 1;
- }
- else
- {
- record_buf[0] = reg_dest;
- record_buf[1] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 2;
- }
+ /* Miscellaneous instructions */
+
+ if (3 == arm_insn_r->decode && 0x12 == opcode1
+ && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
+ {
+ /* Handle BLX, branch and link/exchange. */
+ if (9 == arm_insn_r->opcode)
+ {
+ /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
+ and R14 stores the return address. */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ }
+ else if (7 == arm_insn_r->decode && 0x12 == opcode1)
+ {
+ /* Handle enhanced software breakpoint insn, BKPT. */
+ /* CPSR is changed to be executed in ARM state, disabling normal
+ interrupts, entering abort mode. */
+ /* According to high vector configuration PC is set. */
+ /* user hit breakpoint and type reverse, in
+ that case, we need to go back with previous CPSR and
+ Program Counter. */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+
+ /* Save SPSR also; how? */
+ return -1;
+ }
+ else if (1 == arm_insn_r->decode && 0x12 == opcode1
+ && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
+ {
+ /* Handle BX, branch and link/exchange. */
+ /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
+ record_buf[0] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 1;
+ }
+ else if (1 == arm_insn_r->decode && 0x16 == opcode1
+ && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
+ && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
+ {
+ /* Count leading zeros: CLZ. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+ }
+ else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
+ && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
+ && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
+ && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0))
+ {
+ /* Handle MRS insn. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+ }
}
- else if ((9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode)
- && sbo_sbz (arm_insn_r->arm_insn, 5, 12, 0)
- && sbo_sbz (arm_insn_r->arm_insn, 13, 4, 1)
- && 2 == bits (arm_insn_r->arm_insn, 20, 21))
+ else if (9 == arm_insn_r->decode && opcode1 < 0x10)
{
- /* Handle MSR insn. */
- if (9 == arm_insn_r->opcode)
- {
- /* CSPR is going to be changed. */
- record_buf[0] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 1;
- }
- else
- {
- /* SPSR is going to be changed. */
- /* How to read SPSR value? */
- return -1;
- }
+ /* Multiply and multiply-accumulate */
+
+ /* Handle multiply instructions. */
+ /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */
+ if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode)
+ {
+ /* Handle MLA and MUL. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
+ record_buf[1] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 2;
+ }
+ else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode)
+ {
+ /* Handle SMLAL, SMULL, UMLAL, UMULL. */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19);
+ record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[2] = ARM_PS_REGNUM;
+ arm_insn_r->reg_rec_count = 3;
+ }
}
- else if (9 == arm_insn_r->decode
- && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
- && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+ else if (9 == arm_insn_r->decode && opcode1 > 0x10)
{
+ /* Synchronization primitives */
+
/* Handling SWP, SWPB. */
/* These insn, changes register and memory as well. */
/* SWP or SWPB insn. */
regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
/* SWP insn ?, swaps word. */
if (8 == arm_insn_r->opcode)
- {
- record_buf_mem[0] = 4;
- }
- else
- {
- /* SWPB insn, swaps only byte. */
- record_buf_mem[0] = 1;
- }
+ {
+ record_buf_mem[0] = 4;
+ }
+ else
+ {
+ /* SWPB insn, swaps only byte. */
+ record_buf_mem[0] = 1;
+ }
record_buf_mem[1] = u_regval[0];
arm_insn_r->mem_rec_count = 1;
record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
arm_insn_r->reg_rec_count = 1;
}
- else if (3 == arm_insn_r->decode && 0x12 == opcode1
- && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
+ else if (11 == arm_insn_r->decode || 13 == arm_insn_r->decode
+ || 15 == arm_insn_r->decode)
{
- /* Handle BLX, branch and link/exchange. */
- if (9 == arm_insn_r->opcode)
- {
- /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm,
- and R14 stores the return address. */
- record_buf[0] = ARM_PS_REGNUM;
- record_buf[1] = ARM_LR_REGNUM;
- arm_insn_r->reg_rec_count = 2;
- }
- }
- else if (7 == arm_insn_r->decode && 0x12 == opcode1)
- {
- /* Handle enhanced software breakpoint insn, BKPT. */
- /* CPSR is changed to be executed in ARM state, disabling normal
- interrupts, entering abort mode. */
- /* According to high vector configuration PC is set. */
- /* user hit breakpoint and type reverse, in
- that case, we need to go back with previous CPSR and
- Program Counter. */
- record_buf[0] = ARM_PS_REGNUM;
- record_buf[1] = ARM_LR_REGNUM;
- arm_insn_r->reg_rec_count = 2;
+ if ((opcode1 & 0x12) == 2)
+ {
+ /* Extra load/store (unprivileged) */
+ return -1;
+ }
+ else
+ {
+ /* Extra load/store */
+ switch (bits (arm_insn_r->arm_insn, 5, 6))
+ {
+ case 1:
+ if ((opcode1 & 0x05) == 0x0 || (opcode1 & 0x05) == 0x4)
+ {
+ /* STRH (register), STRH (immediate) */
+ arm_record_strx (arm_insn_r, &record_buf[0],
+ &record_buf_mem[0], ARM_RECORD_STRH);
+ }
+ else if ((opcode1 & 0x05) == 0x1)
+ {
+ /* LDRH (register) */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
- /* Save SPSR also; how? */
- return -1;
- }
- else if (11 == arm_insn_r->decode
- && !bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM))
- {
- /* Handle enhanced store insns and DSP insns (e.g. LDRD). */
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++]
+ = bits (arm_insn_r->arm_insn, 16, 19);
+ }
+ }
+ else if ((opcode1 & 0x05) == 0x5)
+ {
+ /* LDRH (immediate), LDRH (literal) */
+ int rn = bits (arm_insn_r->arm_insn, 16, 19);
- /* Handle str(x) insn */
- arm_record_strx(arm_insn_r, &record_buf[0], &record_buf_mem[0],
- ARM_RECORD_STRH);
- }
- else if (1 == arm_insn_r->decode && 0x12 == opcode1
- && sbo_sbz (arm_insn_r->arm_insn, 9, 12, 1))
- {
- /* Handle BX, branch and link/exchange. */
- /* Branch is chosen by setting T bit of CSPR, bitp[0] of Rm. */
- record_buf[0] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 1;
- }
- else if (1 == arm_insn_r->decode && 0x16 == opcode1
- && sbo_sbz (arm_insn_r->arm_insn, 9, 4, 1)
- && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1))
- {
- /* Count leading zeros: CLZ. */
- record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
- arm_insn_r->reg_rec_count = 1;
- }
- else if (!bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)
- && (8 == arm_insn_r->opcode || 10 == arm_insn_r->opcode)
- && sbo_sbz (arm_insn_r->arm_insn, 17, 4, 1)
- && sbo_sbz (arm_insn_r->arm_insn, 1, 12, 0)
- )
- {
- /* Handle MRS insn. */
- record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
- arm_insn_r->reg_rec_count = 1;
- }
- else if (arm_insn_r->opcode <= 15)
- {
- /* Normal data processing insns. */
- /* Out of 11 shifter operands mode, all the insn modifies destination
- register, which is specified by 13-16 decode. */
- record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
- record_buf[1] = ARM_PS_REGNUM;
- arm_insn_r->reg_rec_count = 2;
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+
+ if (rn != 15)
+ {
+ /*LDRH (immediate) */
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++] = rn;
+ }
+ }
+ }
+ else
+ return -1;
+ break;
+ case 2:
+ if ((opcode1 & 0x05) == 0x0)
+ {
+ /* LDRD (register) */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ record_buf[1] = record_buf[0] + 1;
+ arm_insn_r->reg_rec_count = 2;
+
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++]
+ = bits (arm_insn_r->arm_insn, 16, 19);
+ }
+ }
+ else if ((opcode1 & 0x05) == 0x1)
+ {
+ /* LDRSB (register) */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++]
+ = bits (arm_insn_r->arm_insn, 16, 19);
+ }
+ }
+ else if ((opcode1 & 0x05) == 0x4 || (opcode1 & 0x05) == 0x5)
+ {
+ /* LDRD (immediate), LDRD (literal), LDRSB (immediate),
+ LDRSB (literal) */
+ int rn = bits (arm_insn_r->arm_insn, 16, 19);
+
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+
+ if (rn != 15)
+ {
+ /*LDRD (immediate), LDRSB (immediate) */
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++] = rn;
+ }
+ }
+ }
+ else
+ return -1;
+ break;
+ case 3:
+ if ((opcode1 & 0x05) == 0x0)
+ {
+ /* STRD (register) */
+ arm_record_strx (arm_insn_r, &record_buf[0],
+ &record_buf_mem[0], ARM_RECORD_STRD);
+ }
+ else if ((opcode1 & 0x05) == 0x1)
+ {
+ /* LDRSH (register) */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++]
+ = bits (arm_insn_r->arm_insn, 16, 19);
+ }
+ }
+ else if ((opcode1 & 0x05) == 0x4)
+ {
+ /* STRD (immediate) */
+ arm_record_strx (arm_insn_r, &record_buf[0],
+ &record_buf_mem[0], ARM_RECORD_STRD);
+ }
+ else if ((opcode1 & 0x05) == 0x5)
+ {
+ /* LDRSH (immediate), LDRSH (literal) */
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ arm_insn_r->reg_rec_count = 1;
+
+ if (bit (arm_insn_r->arm_insn, 21))
+ {
+ /* Write back to Rn. */
+ record_buf[arm_insn_r->reg_rec_count++]
+ = bits (arm_insn_r->arm_insn, 16, 19);
+ }
+ }
+ else
+ return -1;
+ break;
+ default:
+ return -1;
+ }
+ }
}
else
{
opc3 = bits (arm_insn_r->arm_insn, 6, 7);
dp_op_sz = bit (arm_insn_r->arm_insn, 8);
bit_d = bit (arm_insn_r->arm_insn, 22);
- opc1 = opc1 & 0x04;
+ /* Mask off the "D" bit. */
+ opc1 = opc1 & ~0x04;
/* Handle VMLA, VMLS. */
if (opc1 == 0x00)
}
}
/* Handle VDIV. */
- else if (opc1 == 0x0b)
+ else if (opc1 == 0x08)
{
if (dp_op_sz)
curr_insn_type = INSN_T1;
static int
arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
{
- uint32_t op, op1_sbit, op1_ebit, coproc;
+ uint32_t op, op1_ebit, coproc, bits_24_25;
struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
struct regcache *reg_cache = arm_insn_r->regcache;
arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
coproc = bits (arm_insn_r->arm_insn, 8, 11);
- op1_sbit = bit (arm_insn_r->arm_insn, 24);
op1_ebit = bit (arm_insn_r->arm_insn, 20);
op = bit (arm_insn_r->arm_insn, 4);
+ bits_24_25 = bits (arm_insn_r->arm_insn, 24, 25);
/* Handle arm SWI/SVC system call instructions. */
- if (op1_sbit)
+ if (bits_24_25 == 0x3)
{
if (tdep->arm_syscall_record != NULL)
{
return -1;
}
}
-
- if ((coproc & 0x0e) == 0x0a)
+ else if (bits_24_25 == 0x02)
{
- /* VFP data-processing instructions. */
- if (!op1_sbit && !op)
- return arm_record_vfp_data_proc_insn (arm_insn_r);
+ if (op)
+ {
+ if ((coproc & 0x0e) == 0x0a)
+ {
+ /* 8, 16, and 32-bit transfer */
+ return arm_record_vdata_transfer_insn (arm_insn_r);
+ }
+ else
+ {
+ if (op1_ebit)
+ {
+ /* MRC, MRC2 */
+ uint32_t record_buf[1];
+
+ record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
+ if (record_buf[0] == 15)
+ record_buf[0] = ARM_PS_REGNUM;
- /* Advanced SIMD, VFP instructions. */
- if (!op1_sbit && op)
- return arm_record_vdata_transfer_insn (arm_insn_r);
+ arm_insn_r->reg_rec_count = 1;
+ REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
+ record_buf);
+ return 0;
+ }
+ else
+ {
+ /* MCR, MCR2 */
+ return -1;
+ }
+ }
+ }
+ else
+ {
+ if ((coproc & 0x0e) == 0x0a)
+ {
+ /* VFP data-processing instructions. */
+ return arm_record_vfp_data_proc_insn (arm_insn_r);
+ }
+ else
+ {
+ /* CDP, CDP2 */
+ return -1;
+ }
+ }
}
else
{
- /* Coprocessor data operations. */
- if (!op1_sbit && !op)
- return arm_record_unsupported_insn (arm_insn_r);
-
- /* Move to Coprocessor from ARM core register. */
- if (!op1_sbit && !op1_ebit && op)
- return arm_record_unsupported_insn (arm_insn_r);
-
- /* Move to arm core register from coprocessor. */
- if (!op1_sbit && op1_ebit && op)
- {
- uint32_t record_buf[1];
-
- record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15);
- if (record_buf[0] == 15)
- record_buf[0] = ARM_PS_REGNUM;
+ unsigned int op1 = bits (arm_insn_r->arm_insn, 20, 25);
- arm_insn_r->reg_rec_count = 1;
- REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count,
- record_buf);
- return 0;
- }
+ if (op1 == 5)
+ {
+ if ((coproc & 0x0e) != 0x0a)
+ {
+ /* MRRC, MRRC2 */
+ return -1;
+ }
+ }
+ else if (op1 == 4 || op1 == 5)
+ {
+ if ((coproc & 0x0e) == 0x0a)
+ {
+ /* 64-bit transfers between ARM core and extension */
+ return -1;
+ }
+ else if (op1 == 4)
+ {
+ /* MCRR, MCRR2 */
+ return -1;
+ }
+ }
+ else if (op1 == 0 || op1 == 1)
+ {
+ /* UNDEFINED */
+ return -1;
+ }
+ else
+ {
+ if ((coproc & 0x0e) == 0x0a)
+ {
+ /* Extension register load/store */
+ }
+ else
+ {
+ /* STC, STC2, LDC, LDC2 */
+ }
+ return -1;
+ }
}
- return arm_record_unsupported_insn (arm_insn_r);
+ return -1;
}
/* Handling opcode 000 insns. */
if (bit (thumb_insn_r->arm_insn, 12))
{
/* Handle load/store register offset. */
- opcode2 = bits (thumb_insn_r->arm_insn, 9, 10);
- if (opcode2 >= 12 && opcode2 <= 15)
+ uint32_t opB = bits (thumb_insn_r->arm_insn, 9, 11);
+
+ if (in_inclusive_range (opB, 4U, 7U))
{
/* LDR(2), LDRB(2) , LDRH(2), LDRSB, LDRSH. */
reg_src1 = bits (thumb_insn_r->arm_insn,0, 2);
record_buf[0] = reg_src1;
thumb_insn_r->reg_rec_count = 1;
}
- else if (opcode2 >= 8 && opcode2 <= 10)
+ else if (in_inclusive_range (opB, 0U, 2U))
{
/* STR(2), STRB(2), STRH(2) . */
reg_src1 = bits (thumb_insn_r->arm_insn, 3, 5);
reg_src2 = bits (thumb_insn_r->arm_insn, 6, 8);
regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]);
regcache_raw_read_unsigned (reg_cache, reg_src2, &u_regval[1]);
- if (8 == opcode2)
+ if (0 == opB)
record_buf_mem[0] = 4; /* STR (2). */
- else if (10 == opcode2)
+ else if (2 == opB)
record_buf_mem[0] = 1; /* STRB (2). */
- else if (9 == opcode2)
+ else if (1 == opB)
record_buf_mem[0] = 2; /* STRH (2). */
record_buf_mem[1] = u_regval[0] + u_regval[1];
thumb_insn_r->mem_rec_count = 1;
}
else if (opcode1)
{
+ /* Special data instructions and branch and exchange */
opcode2 = bits (thumb_insn_r->arm_insn, 8, 9);
opcode3 = bits (thumb_insn_r->arm_insn, 0, 2);
if ((3 == opcode2) && (!opcode3))
{
struct regcache *reg_cache = thumb_insn_r->regcache;
- uint32_t opcode = 0, opcode1 = 0, opcode2 = 0;
+ uint32_t opcode = 0;
uint32_t register_bits = 0, register_count = 0;
uint32_t index = 0, start_address = 0;
uint32_t record_buf[24], record_buf_mem[48];
ULONGEST u_regval = 0;
opcode = bits (thumb_insn_r->arm_insn, 11, 12);
- opcode1 = bits (thumb_insn_r->arm_insn, 8, 12);
- opcode2 = bits (thumb_insn_r->arm_insn, 9, 12);
- if (14 == opcode2)
- {
- /* POP. */
- register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
- while (register_bits)
- {
- if (register_bits & 0x00000001)
- record_buf[index++] = register_count;
- register_bits = register_bits >> 1;
- register_count++;
- }
- record_buf[index++] = ARM_PS_REGNUM;
- record_buf[index++] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = index;
- }
- else if (10 == opcode2)
- {
- /* PUSH. */
- register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
- regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
- while (register_bits)
- {
- if (register_bits & 0x00000001)
- register_count++;
- register_bits = register_bits >> 1;
- }
- start_address = u_regval - \
- (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
- thumb_insn_r->mem_rec_count = register_count;
- while (register_count)
- {
- record_buf_mem[(register_count * 2) - 1] = start_address;
- record_buf_mem[(register_count * 2) - 2] = 4;
- start_address = start_address + 4;
- register_count--;
- }
- record_buf[0] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = 1;
- }
- else if (0x1E == opcode1)
+ if (opcode == 0 || opcode == 1)
{
- /* BKPT insn. */
- /* Handle enhanced software breakpoint insn, BKPT. */
- /* CPSR is changed to be executed in ARM state, disabling normal
- interrupts, entering abort mode. */
- /* According to high vector configuration PC is set. */
- /* User hits breakpoint and type reverse, in that case, we need to go back with
- previous CPSR and Program Counter. */
- record_buf[0] = ARM_PS_REGNUM;
- record_buf[1] = ARM_LR_REGNUM;
- thumb_insn_r->reg_rec_count = 2;
- /* We need to save SPSR value, which is not yet done. */
- printf_unfiltered (_("Process record does not support instruction "
- "0x%0x at address %s.\n"),
- thumb_insn_r->arm_insn,
- paddress (thumb_insn_r->gdbarch,
- thumb_insn_r->this_addr));
- return -1;
- }
- else if ((0 == opcode) || (1 == opcode))
- {
- /* ADD(5), ADD(6). */
+ /* ADR and ADD (SP plus immediate) */
+
reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
record_buf[0] = reg_src1;
thumb_insn_r->reg_rec_count = 1;
}
- else if (2 == opcode)
+ else
{
- /* ADD(7), SUB(4). */
- reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
- record_buf[0] = ARM_SP_REGNUM;
- thumb_insn_r->reg_rec_count = 1;
+ /* Miscellaneous 16-bit instructions */
+ uint32_t opcode2 = bits (thumb_insn_r->arm_insn, 8, 11);
+
+ switch (opcode2)
+ {
+ case 6:
+ /* SETEND and CPS */
+ break;
+ case 0:
+ /* ADD/SUB (SP plus immediate) */
+ reg_src1 = bits (thumb_insn_r->arm_insn, 8, 10);
+ record_buf[0] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 1: /* fall through */
+ case 3: /* fall through */
+ case 9: /* fall through */
+ case 11:
+ /* CBNZ, CBZ */
+ break;
+ case 2:
+ /* SXTH, SXTB, UXTH, UXTB */
+ record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 4: /* fall through */
+ case 5:
+ /* PUSH. */
+ register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
+ while (register_bits)
+ {
+ if (register_bits & 0x00000001)
+ register_count++;
+ register_bits = register_bits >> 1;
+ }
+ start_address = u_regval - \
+ (4 * (bit (thumb_insn_r->arm_insn, 8) + register_count));
+ thumb_insn_r->mem_rec_count = register_count;
+ while (register_count)
+ {
+ record_buf_mem[(register_count * 2) - 1] = start_address;
+ record_buf_mem[(register_count * 2) - 2] = 4;
+ start_address = start_address + 4;
+ register_count--;
+ }
+ record_buf[0] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 10:
+ /* REV, REV16, REVSH */
+ record_buf[0] = bits (thumb_insn_r->arm_insn, 0, 2);
+ thumb_insn_r->reg_rec_count = 1;
+ break;
+ case 12: /* fall through */
+ case 13:
+ /* POP. */
+ register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
+ while (register_bits)
+ {
+ if (register_bits & 0x00000001)
+ record_buf[index++] = register_count;
+ register_bits = register_bits >> 1;
+ register_count++;
+ }
+ record_buf[index++] = ARM_PS_REGNUM;
+ record_buf[index++] = ARM_SP_REGNUM;
+ thumb_insn_r->reg_rec_count = index;
+ break;
+ case 0xe:
+ /* BKPT insn. */
+ /* Handle enhanced software breakpoint insn, BKPT. */
+ /* CPSR is changed to be executed in ARM state, disabling normal
+ interrupts, entering abort mode. */
+ /* According to high vector configuration PC is set. */
+ /* User hits breakpoint and type reverse, in that case, we need to go back with
+ previous CPSR and Program Counter. */
+ record_buf[0] = ARM_PS_REGNUM;
+ record_buf[1] = ARM_LR_REGNUM;
+ thumb_insn_r->reg_rec_count = 2;
+ /* We need to save SPSR value, which is not yet done. */
+ printf_unfiltered (_("Process record does not support instruction "
+ "0x%0x at address %s.\n"),
+ thumb_insn_r->arm_insn,
+ paddress (thumb_insn_r->gdbarch,
+ thumb_insn_r->this_addr));
+ return -1;
+
+ case 0xf:
+ /* If-Then, and hints */
+ break;
+ default:
+ return -1;
+ };
}
REG_ALLOC (thumb_insn_r->arm_regs, thumb_insn_r->reg_rec_count, record_buf);
/* Load/store multiple instruction. */
return thumb2_record_ld_st_multiple (thumb2_insn_r);
}
- else if (!((op2 & 0x64) ^ 0x04))
+ else if ((op2 & 0x64) == 0x4)
{
/* Load/store (dual/exclusive) and table branch instruction. */
return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
}
- else if (!((op2 & 0x20) ^ 0x20))
+ else if ((op2 & 0x60) == 0x20)
{
/* Data-processing (shifted register). */
return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
return -1;
}
+namespace {
+/* Abstract memory reader. */
+
+class abstract_memory_reader
+{
+public:
+ /* Read LEN bytes of target memory at address MEMADDR, placing the
+ results in GDB's memory at BUF. Return true on success. */
+
+ virtual bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) = 0;
+};
+
+/* Instruction reader from real target. */
+
+class instruction_reader : public abstract_memory_reader
+{
+ public:
+ bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override
+ {
+ if (target_read_memory (memaddr, buf, len))
+ return false;
+ else
+ return true;
+ }
+};
+
+} // namespace
+
/* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
and positive val on fauilure. */
static int
-extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size)
+extract_arm_insn (abstract_memory_reader& reader,
+ insn_decode_record *insn_record, uint32_t insn_size)
{
gdb_byte buf[insn_size];
memset (&buf[0], 0, insn_size);
- if (target_read_memory (insn_record->this_addr, &buf[0], insn_size))
+ if (!reader.read (insn_record->this_addr, buf, insn_size))
return 1;
insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0],
insn_size,
dispatch it. */
static int
-decode_insn (insn_decode_record *arm_record, record_type_t record_type,
- uint32_t insn_size)
+decode_insn (abstract_memory_reader &reader, insn_decode_record *arm_record,
+ record_type_t record_type, uint32_t insn_size)
{
/* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
uint32_t ret = 0; /* return value: negative:failure 0:success. */
uint32_t insn_id = 0;
- if (extract_arm_insn (arm_record, insn_size))
+ if (extract_arm_insn (reader, arm_record, insn_size))
{
if (record_debug)
{
return ret;
}
+#if GDB_SELF_TEST
+namespace selftests {
+
+/* Provide both 16-bit and 32-bit thumb instructions. */
+
+class instruction_reader_thumb : public abstract_memory_reader
+{
+public:
+ template<size_t SIZE>
+ instruction_reader_thumb (enum bfd_endian endian,
+ const uint16_t (&insns)[SIZE])
+ : m_endian (endian), m_insns (insns), m_insns_size (SIZE)
+ {}
+
+ bool read (CORE_ADDR memaddr, gdb_byte *buf, const size_t len) override
+ {
+ SELF_CHECK (len == 4 || len == 2);
+ SELF_CHECK (memaddr % 2 == 0);
+ SELF_CHECK ((memaddr / 2) < m_insns_size);
+
+ store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]);
+ if (len == 4)
+ {
+ store_unsigned_integer (&buf[2], 2, m_endian,
+ m_insns[memaddr / 2 + 1]);
+ }
+ return true;
+ }
+
+private:
+ enum bfd_endian m_endian;
+ const uint16_t *m_insns;
+ size_t m_insns_size;
+};
+
+static void
+arm_record_test (void)
+{
+ struct gdbarch_info info;
+ gdbarch_info_init (&info);
+ info.bfd_arch_info = bfd_scan_arch ("arm");
+
+ struct gdbarch *gdbarch = gdbarch_find_by_info (info);
+
+ SELF_CHECK (gdbarch != NULL);
+
+ /* 16-bit Thumb instructions. */
+ {
+ insn_decode_record arm_record;
+
+ memset (&arm_record, 0, sizeof (insn_decode_record));
+ arm_record.gdbarch = gdbarch;
+
+ static const uint16_t insns[] = {
+ /* db b2 uxtb r3, r3 */
+ 0xb2db,
+ /* cd 58 ldr r5, [r1, r3] */
+ 0x58cd,
+ };
+
+ enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
+ instruction_reader_thumb reader (endian, insns);
+ int ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 3);
+
+ arm_record.this_addr += 2;
+ ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 5);
+ }
+
+ /* 32-bit Thumb-2 instructions. */
+ {
+ insn_decode_record arm_record;
+
+ memset (&arm_record, 0, sizeof (insn_decode_record));
+ arm_record.gdbarch = gdbarch;
+
+ static const uint16_t insns[] = {
+ /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */
+ 0xee1d, 0x7f70,
+ };
+
+ enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch);
+ instruction_reader_thumb reader (endian, insns);
+ int ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
+ THUMB2_INSN_SIZE_BYTES);
+
+ SELF_CHECK (ret == 0);
+ SELF_CHECK (arm_record.mem_rec_count == 0);
+ SELF_CHECK (arm_record.reg_rec_count == 1);
+ SELF_CHECK (arm_record.arm_regs[0] == 7);
+ }
+}
+} // namespace selftests
+#endif /* GDB_SELF_TEST */
/* Cleans up local record registers and memory allocations. */
paddress (gdbarch, arm_record.this_addr));
}
- if (extract_arm_insn (&arm_record, 2))
+ instruction_reader reader;
+ if (extract_arm_insn (reader, &arm_record, 2))
{
if (record_debug)
{
if (!(u_regval & t_bit))
{
/* We are decoding arm insn. */
- ret = decode_insn (&arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
+ ret = decode_insn (reader, &arm_record, ARM_RECORD, ARM_INSN_SIZE_BYTES);
}
else
{
/* is it thumb2 insn? */
if ((0x1D == insn_id) || (0x1E == insn_id) || (0x1F == insn_id))
{
- ret = decode_insn (&arm_record, THUMB2_RECORD,
+ ret = decode_insn (reader, &arm_record, THUMB2_RECORD,
THUMB2_INSN_SIZE_BYTES);
}
else
{
/* We are decoding thumb insn. */
- ret = decode_insn (&arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES);
+ ret = decode_insn (reader, &arm_record, THUMB_RECORD,
+ THUMB_INSN_SIZE_BYTES);
}
}
projects / thirdparty / binutils-gdb.git / blobdiff