/* Target-dependent code for GDB, the GNU debugger.
- Copyright (C) 1986-2022 Free Software Foundation, Inc.
+ Copyright (C) 1986-2023 Free Software Foundation, Inc.
This file is part of GDB.
#include "osabi.h"
#include "infcall.h"
#include "sim-regno.h"
-#include "gdb/sim-ppc.h"
+#include "sim/sim-ppc.h"
#include "reggroups.h"
#include "dwarf2/frame.h"
#include "target-descriptions.h"
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
- size_t len = gdbarch_max_insn_length (gdbarch);
+ size_t len = gdbarch_displaced_step_buffer_length (gdbarch);
+ gdb_assert (len > PPC_INSN_SIZE);
std::unique_ptr<ppc_displaced_step_copy_insn_closure> closure
(new ppc_displaced_step_copy_insn_closure (len));
gdb_byte *buf = closure->buf.data ();
displaced_debug_printf ("copy %s->%s: %s",
paddress (gdbarch, from), paddress (gdbarch, to),
- displaced_step_dump_bytes (buf, len).c_str ());
+ bytes_to_string (buf, len).c_str ());
/* This is a work around for a problem with g++ 4.8. */
return displaced_step_copy_insn_closure_up (closure.release ());
ppc_displaced_step_fixup (struct gdbarch *gdbarch,
struct displaced_step_copy_insn_closure *closure_,
CORE_ADDR from, CORE_ADDR to,
- struct regcache *regs)
+ struct regcache *regs, bool completed_p)
{
+ /* If the displaced instruction didn't complete successfully then all we
+ need to do is restore the program counter. */
+ if (!completed_p)
+ {
+ CORE_ADDR pc = regcache_read_pc (regs);
+ pc = from + (pc - to);
+ regcache_write_pc (regs, pc);
+ return;
+ }
+
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* Our closure is a copy of the instruction. */
ppc_displaced_step_copy_insn_closure *closure
else
{
/* Handle any other instructions that do not fit in the categories
- above. */
+ above. */
regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
from + offset);
}
static displaced_step_finish_status
ppc_displaced_step_finish (gdbarch *arch, thread_info *thread,
- gdb_signal sig)
+ const target_waitstatus &status)
{
ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf);
gdb_assert (per_inferior->disp_step_buf.has_value ());
- return per_inferior->disp_step_buf->finish (arch, thread, sig);
+ return per_inferior->disp_step_buf->finish (arch, thread, status);
}
/* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */
address at runtime, can appear to save more than one link
register vis:
- *INDENT-OFF*
stwu r1,-304(r1)
mflr r3
bl 0xff570d0 (blrl)
stw r31,300(r1)
stw r3,308(r1);
...
- *INDENT-ON*
remember just the first one, but skip over additional
ones. */
*/
/* PPC specific type for IEEE 128-bit float field */
+ type_allocator alloc (gdbarch);
struct type *t_float128
- = arch_float_type (gdbarch, 128, "float128_t", floatformats_ieee_quad);
+ = init_float_type (alloc, 128, "float128_t", floatformats_ieee_quad);
struct type *t;
/* POWER7 Extended FP pseudo-registers. */
return builtin_type (gdbarch)->builtin_double;
else
- internal_error (__FILE__, __LINE__,
- _("rs6000_pseudo_register_type: "
+ internal_error (_("rs6000_pseudo_register_type: "
"called on unexpected register '%s' (%d)"),
gdbarch_register_name (gdbarch, regnum), regnum);
}
|| IS_CEFP_PSEUDOREG (tdep, reg_nr))
return efp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
else
- internal_error (__FILE__, __LINE__,
- _("rs6000_pseudo_register_read: "
+ internal_error (_("rs6000_pseudo_register_read: "
"called on unexpected register '%s' (%d)"),
gdbarch_register_name (gdbarch, reg_nr), reg_nr);
}
|| IS_CEFP_PSEUDOREG (tdep, reg_nr))
efp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
else
- internal_error (__FILE__, __LINE__,
- _("rs6000_pseudo_register_write: "
+ internal_error (_("rs6000_pseudo_register_write: "
"called on unexpected register '%s' (%d)"),
gdbarch_register_name (gdbarch, reg_nr), reg_nr);
}
efp_ax_pseudo_register_collect (gdbarch, ax, reg_nr);
}
else
- internal_error (__FILE__, __LINE__,
- _("rs6000_pseudo_register_collect: "
+ internal_error (_("rs6000_pseudo_register_collect: "
"called on unexpected register '%s' (%d)"),
gdbarch_register_name (gdbarch, reg_nr), reg_nr);
return 0;
entry consist of four 128-bit rows.
The ACC rows map to specific VSR registers.
- ACC[0][0] -> VSR[0]
- ACC[0][1] -> VSR[1]
- ACC[0][2] -> VSR[2]
- ACC[0][3] -> VSR[3]
- ...
- ACC[7][0] -> VSR[28]
- ACC[7][1] -> VSR[29]
- ACC[7][2] -> VSR[30]
- ACC[7][3] -> VSR[31]
+ ACC[0][0] -> VSR[0]
+ ACC[0][1] -> VSR[1]
+ ACC[0][2] -> VSR[2]
+ ACC[0][3] -> VSR[3]
+ ...
+ ACC[7][0] -> VSR[28]
+ ACC[7][1] -> VSR[29]
+ ACC[7][2] -> VSR[30]
+ ACC[7][3] -> VSR[31]
NOTE:
In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31].
int ext = PPC_EXTOP (insn);
int at = PPC_FIELD (insn, 6, 3);
+ /* Note the mnemonics for the pmxvf64ger* instructions were officially
+ changed to pmdmxvf64ger*. The old mnemonics are still supported as
+ extended mnemonics. */
+
switch (ext & 0x1f)
{
case 18: /* Floating Divide */
case 218: /* VSX Vector 32-bit Floating-Point GER Negative multiply,
Negative accumulate, xvf32gernn */
- case 59: /* VSX Vector 64-bit Floating-Point GER, pmxvf64ger */
+ case 59: /* VSX Vector 64-bit Floating-Point GER, pmdmxvf64ger
+ (pmxvf64ger) */
case 58: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
Positive accumulate, xvf64gerpp */
case 186: /* VSX Vector 64-bit Floating-Point GER Positive multiply,
case 122: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
Positive accumulate, xvf64gernp */
case 250: /* VSX Vector 64-bit Floating-Point GER Negative multiply,
- Negative accumulate, pmxvf64gernn */
+ Negative accumulate, pmdmxvf64gernn (pmxvf64gernn) */
case 51: /* VSX Vector bfloat16 GER, xvbf16ger2 */
case 50: /* VSX Vector bfloat16 GER Positive multiply,
int at = PPC_FIELD (insn_suffix, 6, 3);
ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch);
+ /* Note, the mnemonics for the pmxvf16ger*, pmxvf32ger*,pmxvf64ger*,
+ pmxvi4ger8*, pmxvi8ger4* pmxvi16ger2* instructions were officially
+ changed to pmdmxbf16ger*, pmdmxvf32ger*, pmdmxvf64ger*, pmdmxvi4ger8*,
+ pmdmxvi8ger4*, pmdmxvi16ger* respectively. The old mnemonics are still
+ supported by the assembler as extended mnemonics. The disassembler
+ generates the new mnemonics. */
if (type == 3)
{
if (ST4 == 9)
switch (opcode)
{
case 35: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
- MMIRR, pmxvi4ger8 */
+ MMIRR, pmdmxvi4ger8 (pmxvi4ger8) */
case 34: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER
- MMIRR, pmxvi4ger8pp */
+ MMIRR, pmdmxvi4ger8pp (pmxvi4ger8pp) */
case 99: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
Integer GER with Saturate Positive multiply,
Positive accumulate, xvi8ger4spp */
case 3: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
- Integer GER MMIRR, pmxvi8ger4 */
+ Integer GER MMIRR, pmdmxvi8ger4 (pmxvi8ger4) */
case 2: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned
Integer GER Positive multiply, Positive accumulate
- MMIRR, pmxvi8ger4pp */
+ MMIRR, pmdmxvi8ger4pp (pmxvi8ger4pp) */
case 75: /* Prefixed Masked VSX Vector 16-bit Signed Integer
- GER MMIRR, pmxvi16ger2 */
+ GER MMIRR, pmdmxvi16ger2 (pmxvi16ger2) */
case 107: /* Prefixed Masked VSX Vector 16-bit Signed Integer
GER Positive multiply, Positive accumulate,
- pmxvi16ger2pp */
+ pmdmxvi16ger2pp (pmxvi16ger2pp) */
case 43: /* Prefixed Masked VSX Vector 16-bit Signed Integer
- GER with Saturation MMIRR, pmxvi16ger2s */
+ GER with Saturation MMIRR, pmdmxvi16ger2s
+ (pmxvi16ger2s) */
case 42: /* Prefixed Masked VSX Vector 16-bit Signed Integer
GER with Saturation Positive multiply, Positive
- accumulate MMIRR, pmxvi16ger2spp */
+ accumulate MMIRR, pmdmxvi16ger2spp (pmxvi16ger2spp)
+ */
ppc_record_ACC_fpscr (regcache, tdep, at, false);
return 0;
case 19: /* Prefixed Masked VSX Vector 16-bit Floating-Point
- GER MMIRR, pmxvf16ger2 */
+ GER MMIRR, pmdmxvf16ger2 (pmxvf16ger2) */
case 18: /* Prefixed Masked VSX Vector 16-bit Floating-Point
GER Positive multiply, Positive accumulate MMIRR,
- pmxvf16ger2pp */
+ pmdmxvf16ger2pp (pmxvf16ger2pp) */
case 146: /* Prefixed Masked VSX Vector 16-bit Floating-Point
GER Positive multiply, Negative accumulate MMIRR,
- pmxvf16ger2pn */
+ pmdmxvf16ger2pn (pmxvf16ger2pn) */
case 82: /* Prefixed Masked VSX Vector 16-bit Floating-Point
GER Negative multiply, Positive accumulate MMIRR,
- pmxvf16ger2np */
+ pmdmxvf16ger2np (pmxvf16ger2np) */
case 210: /* Prefixed Masked VSX Vector 16-bit Floating-Point
GER Negative multiply, Negative accumulate MMIRR,
- pmxvf16ger2nn */
+ pmdmxvf16ger2nn (pmxvf16ger2nn) */
case 27: /* Prefixed Masked VSX Vector 32-bit Floating-Point
- GER MMIRR, pmxvf32ger */
+ GER MMIRR, pmdmxvf32ger (pmxvf32ger) */
case 26: /* Prefixed Masked VSX Vector 32-bit Floating-Point
GER Positive multiply, Positive accumulate MMIRR,
- pmxvf32gerpp */
+ pmdmxvf32gerpp (pmxvf32gerpp) */
case 154: /* Prefixed Masked VSX Vector 32-bit Floating-Point
GER Positive multiply, Negative accumulate MMIRR,
- pmxvf32gerpn */
+ pmdmxvf32gerpn (pmxvf32gerpn) */
case 90: /* Prefixed Masked VSX Vector 32-bit Floating-Point
GER Negative multiply, Positive accumulate MMIRR,
- pmxvf32gernp */
+ pmdmxvf32gernp (pmxvf32gernp )*/
case 218: /* Prefixed Masked VSX Vector 32-bit Floating-Point
GER Negative multiply, Negative accumulate MMIRR,
- pmxvf32gernn */
+ pmdmxvf32gernn (pmxvf32gernn) */
case 59: /* Prefixed Masked VSX Vector 64-bit Floating-Point
- GER MMIRR, pmxvf64ger */
+ GER MMIRR, pmdmxvf64ger (pmxvf64ger) */
case 58: /* Floating-Point GER Positive multiply, Positive
- accumulate MMIRR, pmxvf64gerpp */
+ accumulate MMIRR, pmdmxvf64gerpp (pmxvf64gerpp) */
case 186: /* Prefixed Masked VSX Vector 64-bit Floating-Point
GER Positive multiply, Negative accumulate MMIRR,
- pmxvf64gerpn */
+ pmdmxvf64gerpn (pmxvf64gerpn) */
case 122: /* Prefixed Masked VSX Vector 64-bit Floating-Point
GER Negative multiply, Positive accumulate MMIRR,
- pmxvf64gernp */
+ pmdmxvf64gernp (pmxvf64gernp) */
case 250: /* Prefixed Masked VSX Vector 64-bit Floating-Point
GER Negative multiply, Negative accumulate MMIRR,
- pmxvf64gernn */
+ pmdmxvf64gernn (pmxvf64gernn) */
case 51: /* Prefixed Masked VSX Vector bfloat16 GER MMIRR,
- pmxvbf16ger2 */
+ pmdmxvbf16ger2 (pmxvbf16ger2) */
case 50: /* Prefixed Masked VSX Vector bfloat16 GER Positive
multiply, Positive accumulate MMIRR,
- pmxvbf16ger2pp */
+ pmdmxvbf16ger2pp (pmxvbf16ger2pp) */
case 178: /* Prefixed Masked VSX Vector bfloat16 GER Positive
multiply, Negative accumulate MMIRR,
- pmxvbf16ger2pn */
+ pmdmxvbf16ger2pn (pmxvbf16ger2pn) */
case 114: /* Prefixed Masked VSX Vector bfloat16 GER Negative
multiply, Positive accumulate MMIRR,
- pmxvbf16ger2np */
+ pmdmxvbf16ger2np (pmxvbf16ger2np) */
case 242: /* Prefixed Masked VSX Vector bfloat16 GER Negative
multiply, Negative accumulate MMIRR,
- pmxvbf16ger2nn */
+ pmdmxvbf16ger2nn (pmxvbf16ger2nn) */
ppc_record_ACC_fpscr (regcache, tdep, at, true);
return 0;
}
if (target_read_memory (address, target_mem, PPC_INSN_SIZE) == 0)
{
uint32_t insn = (uint32_t) extract_unsigned_integer
- (target_mem, PPC_INSN_SIZE, gdbarch_byte_order_for_code (gdbarch));
+ (target_mem, PPC_INSN_SIZE, gdbarch_byte_order_for_code (gdbarch));
/* Check if INSN is a TW, TWI, TD or TDI instruction. There
- are multiple choices of such instructions with different registers
- and / or immediate values but they all cause a break. */
+ are multiple choices of such instructions with different registers
+ and / or immediate values but they all cause a break. */
if (is_tw_insn (insn) || is_twi_insn (insn) || is_td_insn (insn)
- || is_tdi_insn (insn))
- return true;
+ || is_tdi_insn (insn))
+ return true;
}
return false;
}
+/* Implement the update_call_site_pc arch hook. */
+
+static CORE_ADDR
+ppc64_update_call_site_pc (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ /* Some versions of GCC emit:
+
+ . bl function
+ . nop
+ . ...
+
+ but emit DWARF where the DW_AT_call_return_pc points to
+ instruction after the 'nop'. Note that while the compiler emits
+ a 'nop', the linker might put some other instruction there -- so
+ we just unconditionally check the next instruction. */
+ return pc + 4;
+}
+
/* Initialize the current architecture based on INFO. If possible, re-use an
architecture from ARCHES, which is a list of architectures already created
during this debugging session.
static struct gdbarch *
rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
- struct gdbarch *gdbarch;
int wordsize, from_xcoff_exec, from_elf_exec;
enum bfd_architecture arch;
unsigned long mach;
valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
PPC_XER_REGNUM, "xer");
- /* Allow alternate names for these registers, to accomodate GDB's
+ /* Allow alternate names for these registers, to accommodate GDB's
historic naming. */
valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (),
PPC_MSR_REGNUM, msr_names);
- "set arch" trust blindly
- GDB startup useless but harmless */
- ppc_gdbarch_tdep *tdep = new ppc_gdbarch_tdep;
+ gdbarch *gdbarch
+ = gdbarch_alloc (&info, gdbarch_tdep_up (new ppc_gdbarch_tdep));
+ ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch);
+
tdep->wordsize = wordsize;
tdep->elf_abi = elf_abi;
tdep->soft_float = soft_float;
tdep->long_double_abi = long_double_abi;
tdep->vector_abi = vector_abi;
- gdbarch = gdbarch_alloc (&info, tdep);
-
tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
if (wordsize == 8)
- set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
+ {
+ set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
+ set_gdbarch_update_call_site_pc (gdbarch, ppc64_update_call_site_pc);
+ }
else
set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
+ set_gdbarch_get_return_buf_addr (gdbarch, ppc_sysv_get_return_buf_addr);
/* Set lr_frame_offset. */
if (wordsize == 8)
set_gdbarch_sw_breakpoint_from_kind (gdbarch,
rs6000_breakpoint::bp_from_kind);
set_gdbarch_program_breakpoint_here_p (gdbarch,
- rs6000_program_breakpoint_here_p);
+ rs6000_program_breakpoint_here_p);
/* The value of symbols of type N_SO and N_FUN maybe null when
it shouldn't be. */
set_gdbarch_displaced_step_finish (gdbarch, ppc_displaced_step_finish);
set_gdbarch_displaced_step_restore_all_in_ptid
(gdbarch, ppc_displaced_step_restore_all_in_ptid);
+ set_gdbarch_displaced_step_buffer_length (gdbarch, 2 * PPC_INSN_SIZE);
- set_gdbarch_max_insn_length (gdbarch, 2 * PPC_INSN_SIZE);
+ set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
/* Hook in ABI-specific overrides, if they have been registered. */
info.target_desc = tdesc;
/* Update the architecture. */
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, _("could not update architecture"));
+ internal_error (_("could not update architecture"));
}
static void
}
if (vector_abi == POWERPC_VEC_LAST)
- internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
+ internal_error (_("Invalid vector ABI accepted: %s."),
powerpc_vector_abi_string);
/* Update the architecture. */
gdbarch_info info;
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, _("could not update architecture"));
+ internal_error (_("could not update architecture"));
}
/* Show the current setting of the exact watchpoints flag. */
projects / thirdparty / binutils-gdb.git / blobdiff