unsigned saved_register
= (unsigned) reverse_frame[operands[1]].value;
- /* realreg >= 0 and addr != -1 indicates that the
- value of saved_register is in memory location
- saved_address. The value of realreg is not
- meaningful in this case but it must be >= 0.
- See trad-frame.h. */
- cache->saved_regs[saved_register].set_realreg (saved_register);
cache->saved_regs[saved_register].set_addr (saved_address);
}
else if (cache
new_reverse_frame[i].state = REVERSE_STATE_VALUE;
new_reverse_frame[i].value
= cache->saved_regs[hopefully_sp].addr ();
- trad_frame_set_value (cache->saved_regs,
- hopefully_sp, prev_sp_value);
+ cache->saved_regs[hopefully_sp].set_value (prev_sp_value);
}
else
{
unsigned saved_register = (unsigned) reverse_frame[i].value;
cache->saved_regs[saved_register].set_realreg (i);
- cache->saved_regs[saved_register].set_addr ((LONGEST) -1);
}
}
}
if (lr_saved_on_stack_p)
{
- cache->saved_regs[TILEGX_LR_REGNUM].set_realreg (TILEGX_LR_REGNUM);
- cache->saved_regs[TILEGX_LR_REGNUM].set_addr (cache->saved_regs[TILEGX_SP_REGNUM].addr ());
+ CORE_ADDR addr = cache->saved_regs[TILEGX_SP_REGNUM].addr ();
+ cache->saved_regs[TILEGX_LR_REGNUM].set_addr (addr);
}
return prolog_end;
current_pc = get_frame_pc (this_frame);
cache->base = get_frame_register_unsigned (this_frame, TILEGX_SP_REGNUM);
- trad_frame_set_value (cache->saved_regs, TILEGX_SP_REGNUM, cache->base);
+ cache->saved_regs[TILEGX_SP_REGNUM].set_value (cache->base);
if (cache->start_pc)
tilegx_analyze_prologue (gdbarch, cache->start_pc, current_pc,