cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 688764e6b746f06336f223a36d995b9e387aa4d1..1a3b87fc2c35c2f836b6530f3328f801f39ddc96 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,116 @@
+2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerated.
+
+2019-07-17  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (static_assert): Define.
+       (main): Use it.
+       * i386-opc.h (Opcode_Modifier_Max): Rename to ...
+       (Opcode_Modifier_Num): ... this.
+       (Mem): Delete.
+
+2019-07-16  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_types): Move RegMem ...
+       (opcode_modifiers): ... here.
+       * i386-opc.h (RegMem): Move to opcode modifer enum.
+       (union i386_operand_type): Move regmem field ...
+       (struct i386_opcode_modifier): ... here.
+       * i386-opc.tbl (RegMem): Define.
+       (mov, movq): Move RegMem on segment, control, debug, and test
+       register flavors.
+       (pextrb): Move RegMem on register only flavors. Add IgnoreSize
+       to non-SSE2AVX flavor.
+       (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
+       Move RegMem on register only flavors. Drop IgnoreSize from
+       legacy encoding flavors.
+       (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
+       flavors.
+       (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
+       register only flavors.
+       (vmovd): Move RegMem and drop IgnoreSize on register only
+       flavor. Change opcode and operand order to store form.
+       * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-16  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_type_init, operand_types): Replace SReg
+       entries.
+       * i386-opc.h (SReg2, SReg3): Replace by ...
+       (SReg): ... this.
+       (union i386_operand_type): Replace sreg fields.
+       * i386-opc.tbl (mov, ): Use SReg.
+       (push, pop): Likewies. Drop i386 and x86-64 specific segment
+       register flavors.
+       * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
+       * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-opc.c: Likewise.
+       * bpf-opc.h: Likewise.
+
+2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-opc.c: Likewise.
+
+2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       * arm-dis.c (print_insn_coprocessor): Rename index to
+       index_operand.
+
+2019-07-05  Kito Cheng <kito.cheng@sifive.com>
+
+       * riscv-opc.c (riscv_insn_types): Add r4 type.
+
+       * riscv-opc.c (riscv_insn_types): Add b and j type.
+
+       * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
+       format for sb type and correct s type.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
+       SVE FMOV alias of FCPY.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
+       to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
+       registers in an instruction prefixed by MOVPRFX.
+
+2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
+       sve_size_13 icode to account for variant behaviour of
+       pmull{t,b}.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
+       sve_size_13 icode to account for variant behaviour of
+       pmull{t,b}.
+       * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
+       (OP_SVE_VVV_Q_D): Add new qualifier.
+       (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
+       (struct aarch64_opcode): Split pmull{t,b} into those requiring
+       AES and those not.
+
+2019-07-01  Jan Beulich  <jbeulich@suse.com>
+
+       * opcodes/i386-gen.c (operand_type_init): Remove
+       OPERAND_TYPE_VEC_IMM4 entry.
+       (operand_types): Remove Vec_Imm4.
+       * opcodes/i386-opc.h (Vec_Imm4): Delete.
+       (union i386_operand_type): Remove vec_imm4.
+       * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
+       * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,