cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 85a2842e30b9efe0408a4c7f7579133f2191acc5..1a3b87fc2c35c2f836b6530f3328f801f39ddc96 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,67 @@
+2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerated.
+
+2019-07-17  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (static_assert): Define.
+       (main): Use it.
+       * i386-opc.h (Opcode_Modifier_Max): Rename to ...
+       (Opcode_Modifier_Num): ... this.
+       (Mem): Delete.
+
+2019-07-16  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_types): Move RegMem ...
+       (opcode_modifiers): ... here.
+       * i386-opc.h (RegMem): Move to opcode modifer enum.
+       (union i386_operand_type): Move regmem field ...
+       (struct i386_opcode_modifier): ... here.
+       * i386-opc.tbl (RegMem): Define.
+       (mov, movq): Move RegMem on segment, control, debug, and test
+       register flavors.
+       (pextrb): Move RegMem on register only flavors. Add IgnoreSize
+       to non-SSE2AVX flavor.
+       (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
+       Move RegMem on register only flavors. Drop IgnoreSize from
+       legacy encoding flavors.
+       (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
+       flavors.
+       (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
+       register only flavors.
+       (vmovd): Move RegMem and drop IgnoreSize on register only
+       flavor. Change opcode and operand order to store form.
+       * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-16  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-gen.c (operand_type_init, operand_types): Replace SReg
+       entries.
+       * i386-opc.h (SReg2, SReg3): Replace by ...
+       (SReg): ... this.
+       (union i386_operand_type): Replace sreg fields.
+       * i386-opc.tbl (mov, ): Use SReg.
+       (push, pop): Likewies. Drop i386 and x86-64 specific segment
+       register flavors.
+       * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
+       * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-opc.c: Likewise.
+       * bpf-opc.h: Likewise.
+
+2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-opc.c: Likewise.
+
+2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       * arm-dis.c (print_insn_coprocessor): Rename index to
+       index_operand.
+
 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 
        * riscv-opc.c (riscv_insn_types): Add r4 type.