Eliminate mi_run_to_main, introduce mi_clean_restart

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 957c694c71ca34e896e58b19882be9fcffa185cf..22250b0d9db08887bc8236f4fbd774b437417ae1 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,7 +1,60 @@
+2020-10-05  Samanta Navarro  <ferivoz@riseup.net>
+
+       * cgen-asm.c: Fix spelling mistakes.
+       * cgen-dis.c: Fix spelling mistakes.
+       * tic30-dis.c: Fix spelling mistakes.
+
+2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/26704
+       * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
+
+2020-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/26705
+       * i386-dis.c (print_insn): Clear modrm if not needed.
+       (putop): Check need_modrm for modrm.mod != 3.  Don't check
+       need_modrm for modrm.mod == 3.
+
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
+       TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
+       TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
+       TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
+       TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
+       TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
+       TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
+       TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
+       WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
+       TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
+       TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
+       TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR,  TRCTSCTLR, TRCVDARCCTLR,
+       TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
+       TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
+
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
+2020-09-28  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
+
+       * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
+       TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
+
+2020-09-26  Alan Modra  <amodra@gmail.com>
+
+       * csky-opc.h: Formatting.
+       (GENERAL_REG_BANK): Correct spelling.  Update use throughout file.
+       (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
+       and shift 1u.
+       (get_register_number): Likewise.
+       * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
+
 2020-09-24  Lili Cui  <lili.cui@intel.com>
 
        PR 26654
-       *i386-dis.c (enum): Put MOD_VEX_0F38* together.
+       * i386-dis.c (enum): Put MOD_VEX_0F38* together.
 
 2020-09-24  Andrew Burgess <andrew.burgess@embecosm.com>
 
@@ -28,7 +81,6 @@
 
 2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
 
-       opcodes/
        * csky-dis.c (using_abi): New.
        (parse_csky_dis_options): New function.
        (get_gr_name): New function.
@@ -36,7 +88,7 @@
        (csky_output_operand): Use get_gr_name and get_cr_name to
        disassemble and add handle of OPRND_TYPE_IMM5b_LS.
        (print_insn_csky): Parse disassembler options.
-       * opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
+       * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
        (GENARAL_REG_BANK): Define.
        (REG_SUPPORT_ALL): Define.
        (REG_SUPPORT_ALL): New.
@@ -872,7 +924,7 @@
        EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
        EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
        EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
-       respectively.
+       respectively.
        (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
        vex_w_table, mod_table): Replace / remove respective entries.
        (print_insn): Move up dp->prefix_requirement handling. Handle
@@ -2696,7 +2748,7 @@
 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
        PR 25376
-       * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+       * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
        (neon_opcodes): Likewise.
        (select_arm_features): Make sure we enable MVE bits when selecting
        armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
@@ -2750,13 +2802,13 @@
        * i386-dis.c (print_insn): Initialize the insn info fields, and
        detect jumps.
 
-2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
 
        * arc-opc.c (C_NE): Make it required.
 
-2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13  Claudiu Zissulescu <claziss@gmail.com>
 
-        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
+       * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
        reserved register name.
 
 2020-01-13  Alan Modra  <amodra@gmail.com>
@@ -2893,13 +2945,13 @@
 
        * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
        uzip{1,2}.
-       * opcodes/aarch64-dis-2.c: Re-generate.
+       * aarch64-dis-2.c: Re-generate.
 
 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 
        * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
        FMMLA encoding.
-       * opcodes/aarch64-dis-2.c: Re-generate.
+       * aarch64-dis-2.c: Re-generate.
 
 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>