+2020-10-05 Samanta Navarro <ferivoz@riseup.net>
+
+ * cgen-asm.c: Fix spelling mistakes.
+ * cgen-dis.c: Fix spelling mistakes.
+ * tic30-dis.c: Fix spelling mistakes.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26704
+ * i386-dis.c (putop): Always display suffix for %LQ in 64bit.
+
+2020-10-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/26705
+ * i386-dis.c (print_insn): Clear modrm if not needed.
+ (putop): Check need_modrm for modrm.mod != 3. Don't check
+ need_modrm for modrm.mod == 3.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Added ETMv4 system registers TRCACATRn, TRCACVRn,
+ TRCAUTHSTATUS, TRCAUXCTLR, TRCBBCTLR, TRCCCCTLR, TRCCIDCCTLR0, TRCCIDCCTLR1,
+ TRCCIDCVRn, TRCCIDR0, TRCCIDR1, TRCCIDR2, TRCCIDR3, TRCCLAIMCLR, TRCCLAIMSET,
+ TRCCNTCTLRn, TRCCNTRLDVRn, TRCCNTVRn, TRCCONFIGR, TRCDEVAFF0, TRCDEVAFF1,
+ TRCDEVARCH, TRCDEVID, TRCDEVTYPE, TRCDVCMRn, TRCDVCVRn, TRCEVENTCTL0R,
+ TRCEVENTCTL1R, TRCEXTINSELR, TRCIDR0, TRCIDR1, TRCIDR2, TRCIDR3, TRCIDR4,
+ TRCIDR5, TRCIDR6, TRCIDR7, TRCIDR8, TRCIDR9, TRCIDR10, TRCIDR11, TRCIDR12,
+ TRCIDR13, TRCIMSPEC0, TRCIMSPECn, TRCITCTRL, TRCLAR WOTRCLSR, TRCOSLAR
+ WOTRCOSLSR, TRCPDCR, TRCPDSR, TRCPIDR0, TRCPIDR1, TRCPIDR2, TRCPIDR3,
+ TRCPIDR4, TRCPIDR[5,6,7], TRCPRGCTLR, TRCP,CSELR, TRCQCTLR, TRCRSCTLRn,
+ TRCSEQEVRn, TRCSEQRSTEVR, TRCSEQSTR, TRCSSCCRn, TRCSSCSRn, TRCSSPCICRn,
+ TRCSTALLCTLR, TRCSTATR, TRCSYNCPR, TRCTRACEIDR, TRCTSCTLR, TRCVDARCCTLR,
+ TRCVDCTLR, TRCVDSACCTLR, TRCVICTLR, TRCVIIECTLR, TRCVIPCSSCTLR, TRCVISSCTLR,
+ TRCVMIDCCTLR0, TRCVMIDCCTLR1 and TRCVMIDCVRn.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
+
+2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
+ TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
+
+2020-09-26 Alan Modra <amodra@gmail.com>
+
+ * csky-opc.h: Formatting.
+ (GENERAL_REG_BANK): Correct spelling. Update use throughout file.
+ (get_register_name): Mask arch with CSKY_ARCH_MASK for shift,
+ and shift 1u.
+ (get_register_number): Likewise.
+ * csky-dis.c (get_gr_name, get_cr_name): Don't mask mach_flag.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ PR 26654
+ * i386-dis.c (enum): Put MOD_VEX_0F38* together.
+
+2020-09-24 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_output_operand): Enclose body of if in curly
+ braces.
+
+2020-09-24 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
+ PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
+ X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
+ X86_64_0F01_REG_1_RM_7_P_2.
+ (prefix_table): Likewise.
+ (x86_64_table): Likewise.
+ (rm_table): Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
+ and CPU_ANY_TDX_FLAGS.
+ (cpu_flags): Add CpuTDX.
+ * i386-opc.h (enum): Add CpuTDX.
+ (i386_cpu_flags): Add cputdx.
+ * i386-opc.tbl: Add TDX insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-17 Cooper Qu <<cooper.qu@linux.alibaba.com>>
+
+ * csky-dis.c (using_abi): New.
+ (parse_csky_dis_options): New function.
+ (get_gr_name): New function.
+ (get_cr_name): New function.
+ (csky_output_operand): Use get_gr_name and get_cr_name to
+ disassemble and add handle of OPRND_TYPE_IMM5b_LS.
+ (print_insn_csky): Parse disassembler options.
+ * csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
+ (GENARAL_REG_BANK): Define.
+ (REG_SUPPORT_ALL): Define.
+ (REG_SUPPORT_ALL): New.
+ (ASH): Define.
+ (REG_SUPPORT_A): Define.
+ (REG_SUPPORT_B): Define.
+ (REG_SUPPORT_C): Define.
+ (REG_SUPPORT_D): Define.
+ (REG_SUPPORT_E): Define.
+ (csky_abiv1_general_regs): New.
+ (csky_abiv1_control_regs): New.
+ (csky_abiv2_general_regs): New.
+ (csky_abiv2_control_regs): New.
+ (get_register_name): New function.
+ (get_register_number): New function.
+ (csky_get_general_reg_name): New function.
+ (csky_get_general_regno): New function.
+ (csky_get_control_reg_name): New function.
+ (csky_get_control_regno): New function.
+ (csky_v2_opcodes): Prefer two oprerans format for bclri and
+ bseti, strengthen the operands legality check of addc, zext
+ and sext.
+
+2020-09-23 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
+ MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
+ MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
+ MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
+ PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
+ (reg_table): New instructions (see prefixes above).
+ (prefix_table): Likewise.
+ (three_byte_table): Likewise.
+ (mod_table): Likewise
+ * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
+ CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
+ (cpu_flags): Likewise.
+ (operand_type_init): Likewise.
+ * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
+ (i386_cpu_flags): Add cpukl and cpuwide_kl.
+ * i386-opc.tbl: Add KL and WIDE_KL insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-09-21 Alan Modra <amodra@gmail.com>
+
+ * rx-dis.c (flag_names): Add missing comma.
+ (register_names, flag_names, double_register_names),
+ (double_register_high_names, double_register_low_names),
+ (double_control_register_names, double_condition_names): Remove
+ trailing commas.
+
+2020-09-18 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
+2020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * csky-dis.c (csky_get_disassembler): Don't return NULL when there
+ is no BFD.
+
+2020-09-16 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
+
+2020-09-10 Nick Clifton <nickc@redhat.com>
+
+ * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
+ for hidden, local, no-type symbols.
+ (disassemble_init_powerpc): Point the symbol_is_valid field in the
+ info structure at the new function.
+
+2020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
+ * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
+ opcode fixing.
+
+2020-09-10 Nick Clifton <nickc@redhat.com>
+
+ * csky-dis.c (csky_output_operand): Coerce the immediate values to
+ long before printing.
+
+2020-09-10 Alan Modra <amodra@gmail.com>
+
+ * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
+ ISA flag.
+
+2020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_output_operand): Add handlers for
+ OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+ OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
+ to support FPUV3 instructions.
+ * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
+ OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
+ OPRND_TYPE_DFLOAT_FMOVI.
+ (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
+ OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
+ OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
+ OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
+ OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
+ OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
+ OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
+ OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
+ OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
+ OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
+ OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
+ OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
+ OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
+ (csky_v2_opcodes): Add FPUV3 instructions.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-dis.c (print_operands): Pass CPU features to
+ aarch64_print_operand().
+ * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
+ preferred disassembly of system registers.
+ (SR_RNG): Refactor to use new SR_FEAT2 macro.
+ (SR_FEAT2): New.
+ (SR_V8_1_A): New.
+ (SR_V8_4_A): New.
+ (SR_V8_A): New.
+ (SR_V8_R): New.
+ (SR_EXPAND_ELx): New.
+ (SR_EXPAND_EL12): New.
+ (aarch64_sys_regs): Specify which registers are only on
+ A-profile, add R-profile system registers.
+ (ENC_BARLAR): New.
+ (PRBARn_ELx): New.
+ (PRLARn_ELx): New.
+ (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
+ Armv8-R AArch64.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_v8_r): New.
+ (ARMV8_R): New.
+ (V8_R_INSN): New.
+ (aarch64_opcode_table): Add dfb.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+
+2020-09-08 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-dis.c (arch_variant): New.
+ (determine_disassembling_preference): Disassemble according to
+ arch variant.
+ (select_aarch64_variant): New.
+ (print_insn_aarch64): Set feature set.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
+ (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
+ (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
+ (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
+ (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
+ (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
+ (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
+ for value parameter and update code to suit.
+ (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
+ (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * i386-dis.c (OP_E_memory): Don't cast to signed type when
+ negating.
+ (get32, get32s): Use unsigned types in shift expressions.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * csky-dis.c (print_insn_csky): Use unsigned type for "given".
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * crx-dis.c: Whitespace.
+ (print_arg): Use unsigned type for longdisp and mask variables,
+ and for left shift constant.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
+ * bpf-ibld.c: Regenerate.
+ * epiphany-ibld.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+
+2020-09-02 Alan Modra <amodra@gmail.com>
+
+ * bfin-dis.c (MASKBITS): Use SIGNBIT.
+
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Move divul and divsl
+ to CSKYV2_ISA_3E3R3 instruction set.
+
+2020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
+
+2020-09-01 Alan Modra <amodra@gmail.com>
+
+ * mep-ibld.c: Regenerate.
+
+2020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_output_operand): Assign dis_info.value for
+ OPRND_TYPE_VREG.
+
+2020-08-30 Alan Modra <amodra@gmail.com>
+
+ * cr16-dis.c: Formatting.
+ (parameter): Delete struct typedef. Use dwordU instead
+ throughout file.
+ (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
+ and tbitb.
+ (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
+
+2020-08-29 Alan Modra <amodra@gmail.com>
+
+ PR 26446
+ * csky-opc.h (MAX_OPRND_NUM): Define to 5.
+ (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
+
+2020-08-28 Alan Modra <amodra@gmail.com>
+
+ PR 26449
+ PR 26450
+ * cgen-ibld.in (insert_1): Use 1UL in forming mask.
+ (extract_normal): Likewise.
+ (insert_normal): Likewise, and move past zero length test.
+ (put_insn_int_value): Handle mask for zero length, use 1UL.
+ * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
+ * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
+ * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
+ * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
+
+2020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (CSKY_DEFAULT_ISA): Define.
+ (csky_dis_info): Add member isa.
+ (csky_find_inst_info): Skip instructions that do not belong to
+ current CPU.
+ (csky_get_disassembler): Get infomation from attribute section.
+ (print_insn_csky): Set defualt ISA flag.
+ * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
+ * csky-opc.h (struct csky_opcode): Change isa_flag16 and
+ isa_flag32'type to unsigned 64 bits.
+
+2020-08-26 Jose E. Marchesi <jemarch@gnu.org>
+
+ * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
+
+2020-08-26 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+ * disassemble.c (disassemble_init_for_target): Set bits for xBPF
+ ISA when appropriate.
+
+2020-08-25 Alan Modra <amodra@gmail.com>
+
+ PR 26504
+ * vax-dis.c (parse_disassembler_options): Always add at least one
+ to entry_addr_total_slots.
+
+2020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
+ in other CPUs to speed up disassembling.
+ * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
+ Change plsli.u16 to plsli.16, change sync's operand format.
+
+2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
+
+2020-08-21 Nick Clifton <nickc@redhat.com>
+
+ * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
+ symbols.
+
+2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
+
+ * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
+
+2020-08-19 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
+ vcmpuq and xvtlsbb.
+
+2020-08-18 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
+ <xvcvbf16spn>: ...to this.
+
+2020-08-12 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
+
+2020-08-12 Nick Clifton <nickc@redhat.com>
+
+ * po/sr.po: Updated Serbian translation.
+
+2020-08-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
+
+2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
+
+ * aarch64-opc.c (aarch64_print_operand):
+ (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
+ (aarch64_sys_reg_supported_p): Function removed.
+ (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
+ (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
+ into this function.
+
+2020-08-10 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
+ instructions.
+
+2020-08-10 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
+ Enable icbt for power5, miso for power8.
+
+2020-08-10 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
+ mtvsrd, and similarly for mfvsrd.
+
+2020-08-04 Christian Groessler <chris@groessler.org>
+ Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
+
+ * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
+ opcodes (special "out" to absolute address).
+ * z8k-opc.h: Regenerate.
+
+2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26305
+ * i386-opc.h (Prefix_Disp8): New.
+ (Prefix_Disp16): Likewise.
+ (Prefix_Disp32): Likewise.
+ (Prefix_Load): Likewise.
+ (Prefix_Store): Likewise.
+ (Prefix_VEX): Likewise.
+ (Prefix_VEX3): Likewise.
+ (Prefix_EVEX): Likewise.
+ (Prefix_REX): Likewise.
+ (Prefix_NoOptimize): Likewise.
+ * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
+ * i386-tbl.h: Regenerated.
+
+2020-07-29 Andreas Arnez <arnez@linux.ibm.com>
+
+ * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
+ default case with abort() instead of printing an error message and
+ continuing, to avoid a maybe-uninitialized warning.
+
+2020-07-24 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2020-07-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Revert previous change.
+
+2020-07-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26237
+ * i386-dis.c (OP_E_memory): Don't display eiz with no scale
+ without base nor index registers.
+
+2020-07-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (putop): Move 'V' and 'W' handling.
+
+2020-07-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (dis386): Adjust 'V' description. Use P-based
+ construct for push/pop of register.
+ (putop): Honor cond when handling 'P'. Drop handling of plain
+ 'V'.
+
+2020-07-15 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
+ description. Drop '&' description. Use P for push of immediate,
+ pushf/popf, enter, and leave. Use %LP for lret/retf.
+ (dis386_twobyte): Use P for push/pop of fs/gs.
+ (reg_table): Use P for push/pop. Use @ for near call/jmp.
+ (x86_64_table): Use P for far call/jmp.
+ (putop): Drop handling of 'U' and '&'. Move and adjust handling
+ of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
+ labels.
+ (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
+ and dqw_mode (unconditional).
+
+2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/26237
+ * i386-dis.c (OP_E_memory): Without base nor index registers,
+ 32-bit displacement to 64 bits.
+
+2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
+
+ * arc-dis.c (print_insn_arc): Detect and emit a warning when a
+ faulty double register pair is detected.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_R, Rm): Delete.
+ (MOD_0F24, MOD_0F26): Rename to ...
+ (X86_64_0F24, X86_64_0F26): ... respectively.
+ (dis386): Update 'L' and 'Z' comments.
+ (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
+ table references.
+ (mod_table): Move opcode 0F24 and 0F26 entries ...
+ (x86_64_table): ... here.
+ (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
+ 'Z' case block.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Rd, Rdq, MaskR): Delete.
+ (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
+ MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
+ MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
+ MOD_EVEX_0F387C): New enumerators.
+ (reg_table): Use Edq for rdssp.
+ (prefix_table): Use Edq for incssp.
+ (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
+ kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
+ ktest*, and kshift*. Use Edq / MaskE for kmov*.
+ * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
+ * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
+ 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
+ * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
+ 0F3828_P_1 and 0F3838_P_1.
+ * i386-dis-evex-w.h: Reference mod_table[] for opcodes
+ 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
+ PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
+ PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
+ PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
+ PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
+ PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
+ (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
+ VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
+ VEX_LEN_0F38F3_R_3_P_0): Rename to ...
+ (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
+ VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
+ (reg_table, prefix_table, three_byte_table, vex_table,
+ vex_len_table, mod_table, rm_table): Replace / remove respective
+ entries.
+ (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
+ of PREFIX_DATA in used_prefixes.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
+ MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
+ MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
+ MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
+ (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
+ MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
+ (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
+ VEX_W_0F3A33_L_0): Delete.
+ (dis386): Adjust "BW" description.
+ (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
+ 0F3A31, 0F3A32, and 0F3A33.
+ (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
+ entries.
+ (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
+ entries.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
+ PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
+ PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
+ PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
+ PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
+ PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
+ PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
+ PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
+ PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
+ PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
+ PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
+ PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
+ PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
+ PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
+ PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
+ PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
+ PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
+ PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
+ PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
+ PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
+ PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
+ PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
+ PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
+ PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
+ PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
+ PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
+ PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
+ PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
+ PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
+ PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
+ PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
+ PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
+ PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
+ PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
+ PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
+ PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
+ PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
+ PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
+ PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
+ PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
+ PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
+ PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
+ PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
+ PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
+ PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
+ PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
+ PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
+ PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
+ PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
+ PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
+ PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
+ PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
+ PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
+ PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
+ PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
+ PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
+ PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
+ PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
+ PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
+ PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
+ PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
+ PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
+ PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
+ PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
+ PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
+ PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
+ PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
+ PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
+ PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
+ PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
+ PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
+ PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
+ PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
+ PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
+ PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
+ PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
+ PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
+ PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
+ PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
+ PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
+ PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
+ PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
+ PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
+ PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
+ PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
+ PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
+ PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
+ PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
+ PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
+ PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
+ PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
+ PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
+ PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
+ PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
+ PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
+ PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
+ PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
+ PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
+ PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
+ PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
+ PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
+ PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
+ PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
+ PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
+ PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
+ PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
+ PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
+ PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
+ PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
+ PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
+ PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
+ PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
+ PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
+ PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
+ PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
+ PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
+ PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
+ PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
+ PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
+ PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
+ PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
+ PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
+ PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
+ PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
+ PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
+ PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
+ PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
+ PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
+ PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
+ PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
+ PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
+ PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
+ PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
+ PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
+ PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
+ PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
+ PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
+ PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
+ PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
+ PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
+ PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
+ PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
+ PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
+ PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
+ PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
+ PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
+ PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
+ PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
+ PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
+ PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
+ PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
+ PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
+ PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
+ PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
+ PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
+ PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
+ PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
+ (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
+ MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
+ MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
+ MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
+ MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
+ MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
+ MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
+ MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
+ MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
+ MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
+ MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
+ VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
+ VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
+ VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
+ VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
+ VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
+ VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
+ VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
+ VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
+ VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
+ VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
+ VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
+ VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
+ VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
+ EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
+ EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
+ EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
+ EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
+ EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
+ EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
+ EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
+ EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
+ EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
+ EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
+ EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
+ EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
+ EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
+ EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
+ EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
+ EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
+ EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
+ EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
+ EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
+ EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
+ EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
+ EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
+ EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
+ EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
+ EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
+ EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
+ VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
+ VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
+ VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
+ VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
+ VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
+ VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
+ VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
+ VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
+ VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
+ VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
+ VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
+ VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
+ VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
+ VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
+ VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
+ VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
+ VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
+ VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
+ EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
+ EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
+ EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
+ EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
+ EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
+ EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
+ EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
+ EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
+ EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
+ EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
+ EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
+ EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
+ EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
+ EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
+ EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
+ EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
+ EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
+ EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
+ EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
+ EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
+ EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
+ EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
+ EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
+ EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
+ EVEX_W_0F3A72_P_2): Rename to ...
+ (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
+ MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
+ MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
+ MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
+ MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
+ MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
+ MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
+ MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
+ MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
+ MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
+ MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
+ VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
+ VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
+ VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
+ VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
+ VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
+ VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
+ VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
+ VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
+ VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
+ EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
+ EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
+ EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
+ EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
+ EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
+ EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
+ EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
+ EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
+ EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
+ EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
+ EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
+ EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
+ EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
+ EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
+ EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
+ EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
+ EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
+ EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
+ EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
+ EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
+ EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
+ EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
+ EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
+ EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
+ EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
+ VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
+ VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
+ VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
+ VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
+ VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
+ VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
+ VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
+ VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
+ VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
+ VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
+ VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
+ VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
+ VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
+ EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
+ EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
+ EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
+ EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
+ EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
+ EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
+ EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
+ EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
+ EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
+ EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
+ EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
+ EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
+ EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
+ EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
+ respectively.
+ (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
+ vex_w_table, mod_table): Replace / remove respective entries.
+ (print_insn): Move up dp->prefix_requirement handling. Handle
+ PREFIX_DATA.
+ * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
+ i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
+ Replace / remove respective entries.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
+ PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
+ (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
+ vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
+ Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
+ the latter two.
+ * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
+ 0F2C, 0F2D, 0F2E, and 0F2F.
+ * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
+ 0F2F table entries.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_VexR, VexScalarR): New.
+ (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
+ XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
+ need_vex_reg): Delete.
+ (prefix_table): Replace VexScalar by VexScalarR and
+ XMVexScalar by XMScalar for vmovss and vmovsd. Replace
+ EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
+ (vex_len_table): Replace EXqVexScalarS by EXqS.
+ (get_valid_dis386): Don't set need_vex_reg.
+ (print_insn): Don't initialize need_vex_reg.
+ (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
+ q_scalar_swap_mode cases.
+ (OP_EX): Don't check for d_scalar_swap_mode and
+ q_scalar_swap_mode.
+ (OP_VEX): Done check need_vex_reg.
+ * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
+ XMVexScalar by XMScalar for vmovss and vmovsd. Replace
+ EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
+ (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
+ VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
+ VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
+ (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
+ VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
+ VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
+ VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
+ (vex_table): Replace Vex128 by Vex.
+ (vex_len_table): Likewise. Adjust referenced enum names.
+ (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
+ referenced enum names.
+ (OP_VEX): Drop vex128_mode and vex256_mode cases.
+ * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (dis386): "LW" description now applies to "DQ".
+ (putop): Handle "DQ". Don't handle "LW" anymore.
+ (prefix_table, mod_table): Replace %LW by %DQ.
+ * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
+ dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
+ d_scalar_swap_mode case handling. Move shift adjsutment into
+ the case its applicable to.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
+ (EXbScalar, EXwScalar): Fold to ...
+ (EXbwUnit): ... this.
+ (b_scalar_mode, w_scalar_mode): Fold to ...
+ (bw_unit_mode): ... this.
+ (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
+ w_scalar_mode handling by bw_unit_mode one.
+ * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
+ ...
+ * i386-dis-evex-prefix.h: ... here.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (PCMPESTR_Fixup): Delete.
+ (dis386): Adjust "LQ" description.
+ (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
+ cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
+ PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
+ vpcmpestrm, and vpcmpestri.
+ (putop): Honor "cond" when handling LQ.
+ * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
+ vcvtsi2ss and vcvtusi2ss.
+ * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
+ vcvtsi2sd and vcvtusi2sd.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (VCMP_Fixup, VCMP): Delete.
+ (simd_cmp_op): Add const.
+ (vex_cmp_op): Move up and drop initial 8 entries. Add const.
+ (CMP_Fixup): Handle VEX case.
+ (prefix_table): Replace VCMP by CMP.
+ * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOVBE_Fixup): Delete.
+ (Mv): Define.
+ (prefix_table): Use Mv for movbe entries.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (CRC32_Fixup): Delete.
+ (prefix_table): Use Eb/Ev for crc32 entries.
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
+ Conditionalize invocations of "USED_REX (0)".
+
+2020-07-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
+ CH, DH, BH, AX, DX): Delete.
+ (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
+ eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
+ dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
+
+2020-07-10 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (TMM): New.
+ (EXtmm): Likewise.
+ (VexTmm): Likewise.
+ (MVexSIBMEM): Likewise.
+ (tmm_mode): Likewise.
+ (vex_sibmem_mode): Likewise.
+ (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
+ (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
+ (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
+ (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
+ (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
+ (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
+ (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
+ (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
+ (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
+ (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
+ (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
+ (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
+ (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
+ (PREFIX_VEX_0F3849_X86_64): Likewise.
+ (PREFIX_VEX_0F384B_X86_64): Likewise.
+ (PREFIX_VEX_0F385C_X86_64): Likewise.
+ (PREFIX_VEX_0F385E_X86_64): Likewise.
+ (X86_64_VEX_0F3849): Likewise.
+ (X86_64_VEX_0F384B): Likewise.
+ (X86_64_VEX_0F385C): Likewise.
+ (X86_64_VEX_0F385E): Likewise.
+ (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
+ (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
+ (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
+ (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
+ (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
+ (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
+ (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
+ (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
+ (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
+ (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
+ (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
+ (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
+ (VEX_W_0F3849_X86_64_P_0): Likewise.
+ (VEX_W_0F3849_X86_64_P_2): Likewise.
+ (VEX_W_0F3849_X86_64_P_3): Likewise.
+ (VEX_W_0F384B_X86_64_P_1): Likewise.
+ (VEX_W_0F384B_X86_64_P_2): Likewise.
+ (VEX_W_0F384B_X86_64_P_3): Likewise.
+ (VEX_W_0F385C_X86_64_P_1): Likewise.
+ (VEX_W_0F385E_X86_64_P_0): Likewise.
+ (VEX_W_0F385E_X86_64_P_1): Likewise.
+ (VEX_W_0F385E_X86_64_P_2): Likewise.
+ (VEX_W_0F385E_X86_64_P_3): Likewise.
+ (names_tmm): Likewise.
+ (att_names_tmm): Likewise.
+ (intel_operand_size): Handle void_mode.
+ (OP_XMM): Handle tmm_mode.
+ (OP_EX): Likewise.
+ (OP_VEX): Likewise.
+ * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
+ CpuAMX_BF16 and CpuAMX_TILE.
+ (operand_type_shorthands): Add RegTMM.
+ (operand_type_init): Likewise.
+ (operand_types): Add Tmmword.
+ (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
+ (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
+ * i386-opc.h (CpuAMX_INT8): New.
+ (CpuAMX_BF16): Likewise.
+ (CpuAMX_TILE): Likewise.
+ (SIBMEM): Likewise.
+ (Tmmword): Likewise.
+ (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
+ (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
+ (i386_operand_type): Add tmmword.
+ * i386-opc.tbl: Add AMX instructions.
+ * i386-reg.tbl: Add AMX registers.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2020-07-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
+ (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
+ Rename to ...
+ (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
+ REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
+ respectively.
+ (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
+ VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
+ VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
+ VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
+ VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
+ VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
+ VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
+ VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
+ VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
+ VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
+ VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
+ VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
+ VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
+ VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
+ VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
+ VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
+ VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
+ VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
+ VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
+ VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
+ VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
+ VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
+ VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
+ VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
+ VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
+ VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
+ VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
+ VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
+ VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
+ VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
+ VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
+ VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
+ VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
+ VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
+ VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
+ VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
+ (reg_table): Re-order XOP entries. Adjust their operands.
+ (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
+ 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
+ 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
+ 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
+ 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
+ 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
+ entries by references ...
+ (vex_len_table): ... to resepctive new entries here. For several
+ new and existing entries reference ...
+ (vex_w_table): ... new entries here.
+ (mod_table): New MOD_VEX_0FXOP_09_12 entry.
+
+2020-07-08 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (XMVexScalarI4): Define.
+ (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
+ VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
+ VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
+ (vex_len_table): Move scalar FMA4 entries ...
+ (prefix_table): ... here.
+ (OP_REG_VexI4): Handle scalar_mode.
+ * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
+ * i386-tbl.h: Re-generate.
+
2020-07-08 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
- * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+ * arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
(neon_opcodes): Likewise.
(select_arm_features): Make sure we enable MVE bits when selecting
armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
* i386-dis.c (print_insn): Initialize the insn info fields, and
detect jumps.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
* arc-opc.c (C_NE): Make it required.
-2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
+2020-01-13 Claudiu Zissulescu <claziss@gmail.com>
- * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
+ * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
reserved register name.
2020-01-13 Alan Modra <amodra@gmail.com>
* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
uzip{1,2}.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-03 Jan Beulich <jbeulich@suse.com>
* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
FMMLA encoding.
- * opcodes/aarch64-dis-2.c: Re-generate.
+ * aarch64-dis-2.c: Re-generate.
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
projects / thirdparty / binutils-gdb.git / blobdiff