x86-64: Zero-extend lower 32 bits displacement to 64 bits

[thirdparty/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 46300b55acb02f433be415588d3a74e73923e750..5d4fbc68d1f5059379deafac41b652260686e499 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,37 @@
+2020-07-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/26237
+       * i386-dis.c (OP_E_memory): Without base nor index registers,
+       zero-extend lower 32-bit displacement to 64 bits.
+
+2020-07-06  Nick Clifton  <nickc@redhat.com>
+
+       * po/pt_BR.po: Updated Brazilian Portugugese translation.
+       * po/uk.po: Updated Ukranian translation.
+
+2020-07-04  Nick Clifton  <nickc@redhat.com>
+
+       * configure: Regenerate.
+       * po/opcodes.pot: Regenerate.
+
+2020-07-04  Nick Clifton  <nickc@redhat.com>
+
+       Binutils 2.35 branch created.
+
+2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (opcode_modifiers): Add VexSwapSources.
+       * i386-opc.h (VexSwapSources): New.
+       (i386_opcode_modifier): Add vexswapsources.
+       * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
+       with two source operands swapped.
+       * i386-tbl.h: Regenerated.
+
+2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
+       unprivileged CSR can also be initialized.
+
 2020-06-29  Alan Modra  <amodra@gmail.com>
 
        * arm-dis.c: Use C style comments.