+2019-09-09 Phil Blundell <pb@pbcl.net>
+
+ binutils 2.33 branch created.
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24961
+ * tic30-dis.c (get_indirect_operand): Check for bufcnt being
+ greater than zero before indexing via (bufcnt -1).
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24958
+ * mmix-dis.c (MAX_REG_NAME_LEN): Define.
+ (MAX_SPEC_REG_NAME_LEN): Define.
+ (struct mmix_dis_info): Use defined constants for array lengths.
+ (get_reg_name): New function.
+ (get_sprec_reg_name): New function.
+ (print_insn_mmix): Use new functions.
+
+2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
+ (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
+ (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
+
+2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
+ tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
+ (aarch64_sys_reg_supported_p): Update checks for the above.
+
+2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
+ cases MVE_SQRSHRL and MVE_UQRSHLL.
+ (print_insn_mve): Add case for specifier 'k' to check
+ specific bit of the instruction.
+
+2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
+
+ PR 24854
+ * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
+ encountering an unknown machine type.
+ (print_insn_arc): Handle arc_insn_length returning 0. In error
+ cases return -1 rather than calling abort.
+
+2019-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
+ (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
+ IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
+ instructions.
+
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
+ fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
+
+ * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
+ fscsr.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
+ and MPY class instructions.
+ (parse_option): Add nps400 option.
+ (print_arc_disassembler_options): Add nps400 info.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (bspeek): Remove it, added to main table.
+ (bspop): Likewise.
+ (modapp): Likewise.
+ * arc-opc.c (RAD_CHK): Add.
+ * arc-tbl.h: Regenerate.
+
+2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
+ (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
+
+2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
+ instructions as UNPREDICTABLE.
+
+2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerated.
+
+2019-07-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (static_assert): Define.
+ (main): Use it.
+ * i386-opc.h (Opcode_Modifier_Max): Rename to ...
+ (Opcode_Modifier_Num): ... this.
+ (Mem): Delete.
+
+2019-07-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_types): Move RegMem ...
+ (opcode_modifiers): ... here.
+ * i386-opc.h (RegMem): Move to opcode modifer enum.
+ (union i386_operand_type): Move regmem field ...
+ (struct i386_opcode_modifier): ... here.
+ * i386-opc.tbl (RegMem): Define.
+ (mov, movq): Move RegMem on segment, control, debug, and test
+ register flavors.
+ (pextrb): Move RegMem on register only flavors. Add IgnoreSize
+ to non-SSE2AVX flavor.
+ (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
+ Move RegMem on register only flavors. Drop IgnoreSize from
+ legacy encoding flavors.
+ (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
+ flavors.
+ (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
+ register only flavors.
+ (vmovd): Move RegMem and drop IgnoreSize on register only
+ flavor. Change opcode and operand order to store form.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init, operand_types): Replace SReg
+ entries.
+ * i386-opc.h (SReg2, SReg3): Replace by ...
+ (SReg): ... this.
+ (union i386_operand_type): Replace sreg fields.
+ * i386-opc.tbl (mov, ): Use SReg.
+ (push, pop): Likewies. Drop i386 and x86-64 specific segment
+ register flavors.
+ * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
+2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+
+2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * arm-dis.c (print_insn_coprocessor): Rename index to
+ index_operand.
+
+2019-07-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * riscv-opc.c (riscv_insn_types): Add r4 type.
+
+ * riscv-opc.c (riscv_insn_types): Add b and j type.
+
+ * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
+ format for sb type and correct s type.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
+ SVE FMOV alias of FCPY.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
+ to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
+ registers in an instruction prefixed by MOVPRFX.
+
+2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
+ sve_size_13 icode to account for variant behaviour of
+ pmull{t,b}.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
+ sve_size_13 icode to account for variant behaviour of
+ pmull{t,b}.
+ * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
+ (OP_SVE_VVV_Q_D): Add new qualifier.
+ (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
+ (struct aarch64_opcode): Split pmull{t,b} into those requiring
+ AES and those not.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_VEC_IMM4 entry.
+ (operand_types): Remove Vec_Imm4.
+ * opcodes/i386-opc.h (Vec_Imm4): Delete.
+ (union i386_operand_type): Remove vec_imm4.
+ * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
2019-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
projects / thirdparty / binutils-gdb.git / blobdiff