+2019-09-09 Phil Blundell <pb@pbcl.net>
+
+ binutils 2.33 branch created.
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24961
+ * tic30-dis.c (get_indirect_operand): Check for bufcnt being
+ greater than zero before indexing via (bufcnt -1).
+
+2019-09-03 Nick Clifton <nickc@redhat.com>
+
+ PR 24958
+ * mmix-dis.c (MAX_REG_NAME_LEN): Define.
+ (MAX_SPEC_REG_NAME_LEN): Define.
+ (struct mmix_dis_info): Use defined constants for array lengths.
+ (get_reg_name): New function.
+ (get_sprec_reg_name): New function.
+ (print_insn_mmix): Use new functions.
+
+2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
+ (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
+ (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
+
+2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
+ tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
+ (aarch64_sys_reg_supported_p): Update checks for the above.
+
+2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
+ cases MVE_SQRSHRL and MVE_UQRSHLL.
+ (print_insn_mve): Add case for specifier 'k' to check
+ specific bit of the instruction.
+
+2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
+
+ PR 24854
+ * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
+ encountering an unknown machine type.
+ (print_insn_arc): Handle arc_insn_length returning 0. In error
+ cases return -1 rather than calling abort.
+
+2019-08-07 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
+ (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
+ IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
+ instructions.
+
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
+ fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
+
+ * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
+ fscsr.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
+ and MPY class instructions.
+ (parse_option): Add nps400 option.
+ (print_arc_disassembler_options): Add nps400 info.
+
+2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (bspeek): Remove it, added to main table.
+ (bspop): Likewise.
+ (modapp): Likewise.
+ * arc-opc.c (RAD_CHK): Add.
+ * arc-tbl.h: Regenerate.
+
+2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
+ (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
+
+2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
+
+ * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
+ instructions as UNPREDICTABLE.
+
+2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerated.
+
+2019-07-17 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (static_assert): Define.
+ (main): Use it.
+ * i386-opc.h (Opcode_Modifier_Max): Rename to ...
+ (Opcode_Modifier_Num): ... this.
+ (Mem): Delete.
+
+2019-07-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_types): Move RegMem ...
+ (opcode_modifiers): ... here.
+ * i386-opc.h (RegMem): Move to opcode modifer enum.
+ (union i386_operand_type): Move regmem field ...
+ (struct i386_opcode_modifier): ... here.
+ * i386-opc.tbl (RegMem): Define.
+ (mov, movq): Move RegMem on segment, control, debug, and test
+ register flavors.
+ (pextrb): Move RegMem on register only flavors. Add IgnoreSize
+ to non-SSE2AVX flavor.
+ (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
+ Move RegMem on register only flavors. Drop IgnoreSize from
+ legacy encoding flavors.
+ (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
+ flavors.
+ (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
+ register only flavors.
+ (vmovd): Move RegMem and drop IgnoreSize on register only
+ flavor. Change opcode and operand order to store form.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init, operand_types): Replace SReg
+ entries.
+ * i386-opc.h (SReg2, SReg3): Replace by ...
+ (SReg): ... this.
+ (union i386_operand_type): Replace sreg fields.
+ * i386-opc.tbl (mov, ): Use SReg.
+ (push, pop): Likewies. Drop i386 and x86-64 specific segment
+ register flavors.
+ * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
+2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+
+2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * arm-dis.c (print_insn_coprocessor): Rename index to
+ index_operand.
+
+2019-07-05 Kito Cheng <kito.cheng@sifive.com>
+
+ * riscv-opc.c (riscv_insn_types): Add r4 type.
+
+ * riscv-opc.c (riscv_insn_types): Add b and j type.
+
+ * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
+ format for sb type and correct s type.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
+ SVE FMOV alias of FCPY.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
+ to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
+
+2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
+
+ * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
+ registers in an instruction prefixed by MOVPRFX.
+
+2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
+ sve_size_13 icode to account for variant behaviour of
+ pmull{t,b}.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
+ sve_size_13 icode to account for variant behaviour of
+ pmull{t,b}.
+ * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
+ (OP_SVE_VVV_Q_D): Add new qualifier.
+ (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
+ (struct aarch64_opcode): Split pmull{t,b} into those requiring
+ AES and those not.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * opcodes/i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_VEC_IMM4 entry.
+ (operand_types): Remove Vec_Imm4.
+ * opcodes/i386-opc.h (Vec_Imm4): Delete.
+ (union i386_operand_type): Remove vec_imm4.
+ * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
+ * opcodes/i386-init.h, i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
+ vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
+ rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
+ vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
+ xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
+ monitorx, mwaitx): Drop ImmExt from operand-less forms.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (and, or): Add Optimize to forms allowing two
+ register operands.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (C): New.
+ (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
+ pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
+ por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
+ cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
+ pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
+ cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
+ cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
+ vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
+ vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
+ vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
+ vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
+ vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
+ vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
+ vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
+ vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
+ vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
+ vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
+ vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
+ vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
+ vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
+ vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
+ vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
+ vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
+ vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
+ vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
+ vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
+ flavors.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (and, or): Add Optimize to forms allowing two
+ register operands.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
+ * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
+ vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
+ Disp8MemShift from register only templates.
+ * i386-tbl.h: Re-generate.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
+ MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
+ MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
+ EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
+ EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
+ EVEX_W_0F11_P_3_M_1): Delete.
+ (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
+ EVEX_W_0F11_P_3): New.
+ * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
+ MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
+ MOD_EVEX_0F11_PREFIX_3 table entries.
+ * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
+ PREFIX_EVEX_0F11 table entries.
+ * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
+ EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
+ EVEX_W_0F11_P_3_M_{0,1} table entries.
+
+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
+ Delete.
+
+2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24719
+ * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
+ EVEX_LEN_0F38C7_R_6_P_2_W_1.
+ * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
+ PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
+ PREFIX_EVEX_0F38C6_REG_6 entries.
+ * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
+ EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
+ EVEX_W_0F38C7_R_6_P_2 entries.
+ * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
+ EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
+
+2019-06-27 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
+ VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
+ VEX_LEN_0F2D_P_3): Delete.
+ (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
+ vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
+ (prefix_table): ... here.
+
+2019-06-27 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Iq): Delete.
+ (Id): New.
+ (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
+ TBM insns.
+ (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
+ vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
+ (OP_E_memory): Also honor needindex when deciding whether an
+ address size prefix needs printing.
+ (OP_I): Remove handling of q_mode. Add handling of d_mode.
+
+2019-06-26 Jim Wilson <jimw@sifive.com>
+
+ PR binutils/24739
+ * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
+ Set info->display_endian to info->endian_code.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
+ entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
+ OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
+ OPERAND_TYPE_ACC64 entries.
+ * i386-init.h: Re-generate.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
+ Delete.
+ (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
+ of dqa_mode.
+ * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
+ entries here.
+ * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
+ entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
+ variables.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
+ Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
+ movnti.
+ * i386-opc.tbl (movnti): Add IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (and): Mark Imm8S form for optimization.
+ * i386-tbl.h: Re-generate.
+
+2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis-evex.h: Break into ...
+ * i386-dis-evex-len.h: New file.
+ * i386-dis-evex-mod.h: Likewise.
+ * i386-dis-evex-prefix.h: Likewise.
+ * i386-dis-evex-reg.h: Likewise.
+ * i386-dis-evex-w.h: Likewise.
+ * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
+ i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
+ i386-dis-evex-mod.h.
+
+2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24700
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
+ EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
+ EVEX_W_0F385B_P_2.
+ (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
+ EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
+ EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
+ EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
+ EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
+ EVEX_LEN_0F385B_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
+ (EVEX_LEN_0F3819_P_2_W_1): Likewise.
+ (EVEX_LEN_0F381A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F381A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F381B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F381B_P_2_W_1): Likewise.
+ (EVEX_LEN_0F385A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F385A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F385B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F385B_P_2_W_1): Likewise.
+
+2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24691
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
+ EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
+ EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
+ (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
+ EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
+ EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
+ EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
+ EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
+ EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
+ EVEX_LEN_0F3A43_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
+ (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
+
+2019-06-14 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po; Updated French translation.
+
+2019-06-13 Stafford Horne <shorne@gmail.com>
+
+ * or1k-asm.c: Regenerated.
+ * or1k-desc.c: Regenerated.
+ * or1k-desc.h: Regenerated.
+ * or1k-dis.c: Regenerated.
+ * or1k-ibld.c: Regenerated.
+ * or1k-opc.c: Regenerated.
+ * or1k-opc.h: Regenerated.
+ * or1k-opinst.c: Regenerated.
+
+2019-06-12 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
+
+2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24633
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
+ EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
+ (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
+ EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
+ EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
+ EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
+ EVEX_LEN_0F3A1B_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
+ (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
+
+2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24626
+ * i386-dis.c (print_insn): Check for unused VEX.vvvv and
+ EVEX.vvvv when disassembling VEX and EVEX instructions.
+ (OP_VEX): Set vex.register_specifier to 0 after readding
+ vex.register_specifier.
+ (OP_Vex_2src_1): Likewise.
+ (OP_Vex_2src_2): Likewise.
+ (OP_LWP_E): Likewise.
+ (OP_EX_Vex): Don't check vex.register_specifier.
+ (OP_XMM_Vex): Likewise.
+
+2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
+ * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
+ instructions.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
+ CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
+ (cpu_flags): Add CpuAVX512_VP2INTERSECT.
+ * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
+ (i386_cpu_flags): Add cpuavx512_vp2intersect.
+ * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * doc/c-i386.texi: Document enqcmd.
+ * testsuite/gas/i386/enqcmd-intel.d: New file.
+ * testsuite/gas/i386/enqcmd-inval.l: Likewise.
+ * testsuite/gas/i386/enqcmd-inval.s: Likewise.
+ * testsuite/gas/i386/enqcmd.d: Likewise.
+ * testsuite/gas/i386/enqcmd.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
+ enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
+ and x86-64-enqcmd.
+
+2019-06-04 Alan Hayward <alan.hayward@arm.com>
+
+ * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
+
+2019-06-03 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (prefix_opcd_indices): Correct size.
+
+2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24625
+ * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
+ Disp8ShiftVL.
+ * i386-tbl.h: Regenerated.
+
+2019-05-24 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2019-05-24 Peter Bergner <bergner@linux.ibm.com>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
+ (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
+ (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
+ (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
+ XTOP>): Define and add entries.
+ (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
+ (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
+ pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
+ plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
+
+2019-05-24 Peter Bergner <bergner@linux.ibm.com>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add "future" entry.
+ (PREFIX_OPCD_SEGS): Define.
+ (prefix_opcd_indices): New array.
+ (disassemble_init_powerpc): Initialize prefix_opcd_indices.
+ (lookup_prefix): New function.
+ (print_insn_powerpc): Handle 64-bit prefix instructions.
+ * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
+ (PMRR, POWERXX): Define.
+ (prefix_opcodes): New instruction table.
+ (prefix_num_opcodes): New constant.
+
+2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
+ * configure: Regenerated.
+ * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
+ and cpu/bpf.opc.
+ (HFILES): Add bpf-desc.h and bpf-opc.h.
+ (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
+ bpf-ibld.c and bpf-opc.c.
+ (BPF_DEPS): Define.
+ * Makefile.in: Regenerated.
+ * disassemble.c (ARCH_bpf): Define.
+ (disassembler): Add case for bfd_arch_bpf.
+ (disassemble_init_for_target): Likewise.
+ (enum epbf_isa_attr): Define.
+ * disassemble.h: extern print_insn_bpf.
+ * bpf-asm.c: Generated.
+ * bpf-opc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-ibld.c: Likewise.
+ * bpf-dis.c: Likewise.
+ * bpf-desc.h: Likewise.
+ * bpf-desc.c: Likewise.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
+ and VMSR with the new operands.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (enum mve_instructions): New enum
+ for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
+ and cneg.
+ (mve_opcodes): New instructions as above.
+ (is_mve_encoding_conflict): Add cases for csinc, csinv,
+ csneg and csel.
+ (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (emun mve_instructions): Updated for new instructions.
+ (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
+ sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
+ uqshl, urshrl and urshr.
+ (is_mve_okay_in_it): Add new instructions to TRUE list.
+ (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
+ (print_insn_mve): Updated to accept new %j,
+ %<bitfield>m and %<bitfield>n patterns.
+
+2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Change source register
+ constraint for DAUI.
+
+2019-05-20 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (enum mve_undefined): Add new reasons.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Michael Collison <michael.collison@arm.com>
projects / thirdparty / binutils-gdb.git / blobdiff