CSKY: Add new arch CK860.

[thirdparty/binutils-gdb.git] / opcodes / csky-opc.h

diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h
index 30894033367a6bca5d9e1241bc962adbdd6cc230..796d3757024a13e0eb6bfcabd6dabdbbc551fb6f 100644 (file)
--- a/opcodes/csky-opc.h
+++ b/opcodes/csky-opc.h
@@ -3401,11 +3401,6 @@ const struct csky_opcode csky_v2_opcodes[] =
                        (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT),
                        (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)),
          CSKY_ISA_FLOAT_1E2),
-    DOP32 ("sync",
-          OPCODE_INFO1 (0xc0000420,
-                        (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
-          OPCODE_INFO0 (0xc0000420),
-          CSKYV2_ISA_E1),
     DOP32 ("idly",
           OPCODE_INFO1 (0xc0001c20,
                         (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)),
@@ -4681,6 +4676,117 @@ const struct csky_opcode csky_v2_opcodes[] =
 #undef _RELAX
 #define _RELAX      0
 
+  /* CK860 instructions.  */
+  OP32("sync.is",
+       OPCODE_INFO0(0xc2200420),
+       CSKYV2_ISA_10E60),
+  OP32("sync.i",
+       OPCODE_INFO0(0xc0200420),
+       CSKYV2_ISA_10E60),
+  OP32("sync.s",
+       OPCODE_INFO0(0xc2000420),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brwarw",
+       OPCODE_INFO0(0xc000842f),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brwarws",
+       OPCODE_INFO0(0xc200842f),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brar",
+       OPCODE_INFO0(0xc0008425),
+       CSKYV2_ISA_10E60),
+  OP32("bar.brars",
+       OPCODE_INFO0(0xc2008425),
+       CSKYV2_ISA_10E60),
+  OP32("bar.bwaw",
+       OPCODE_INFO0(0xc000842a),
+       CSKYV2_ISA_10E60),
+  OP32("bar.bwaws",
+       OPCODE_INFO0(0xc200842a),
+       CSKYV2_ISA_10E60),
+  OP32("icache.iall",
+       OPCODE_INFO0(0xc1009020),
+       CSKYV2_ISA_10E60),
+  OP32("icache.ialls",
+       OPCODE_INFO0(0xc3009020),
+       CSKYV2_ISA_10E60),
+  OP32("icache.iva",
+       OPCODE_INFO1(0xc0a09020,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.iall",
+       OPCODE_INFO0(0xc1009420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.iva",
+       OPCODE_INFO1(0xc1609420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.isw",
+       OPCODE_INFO1(0xc1409420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.call",
+       OPCODE_INFO0(0xc0809420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cva",
+       OPCODE_INFO1(0xc0e09420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cval1",
+       OPCODE_INFO1(0xc2e09420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.csw",
+       OPCODE_INFO1(0xc0c09420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.ciall",
+       OPCODE_INFO0(0xc1809420),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.civa",
+       OPCODE_INFO1(0xc1e09420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("dcache.cisw",
+       OPCODE_INFO1(0xc1c09420,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vaa",
+       OPCODE_INFO1(0xc0408820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vaas",
+       OPCODE_INFO1(0xc2408820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.asid",
+       OPCODE_INFO1(0xc0208820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.asids",
+       OPCODE_INFO1(0xc2208820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.va",
+       OPCODE_INFO1(0xc0608820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.vas",
+       OPCODE_INFO1(0xc2608820,
+                   (16_20, AREG, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.all",
+       OPCODE_INFO0(0xc0008820),
+       CSKYV2_ISA_10E60),
+  OP32("tlbi.alls",
+       OPCODE_INFO0(0xc2008820),
+       CSKYV2_ISA_10E60),
+  DOP32("sync",
+       OPCODE_INFO0(0xc0000420),
+       OPCODE_INFO1(0xc0000420,
+                   (21_25, IMM5b, OPRND_SHIFT_0_BIT)),
+       CSKYV2_ISA_E1),
+
     /* The followings are enhance DSP instructions.  */
     DOP32_WITH_WORK ("bloop",
                     OPCODE_INFO3 (0xe9c00000,
@@ -5325,7 +5431,7 @@ const struct csky_opcode csky_v2_opcodes[] =
                        (16_20, AREG, OPRND_SHIFT_0_BIT),
                        (21_25, AREG, OPRND_SHIFT_0_BIT)),
          CSKY_ISA_DSP_ENHANCE),
-    OP32 ("plsli.u16",
+    OP32 ("plsli.16",
          OPCODE_INFO3 (0xf800d400,
                        (0_4, AREG, OPRND_SHIFT_0_BIT),
                        (16_20, AREG, OPRND_SHIFT_0_BIT),