static bool OP_EX (instr_info *, int, int);
static bool OP_EMC (instr_info *, int,int);
static bool OP_MXC (instr_info *, int,int);
-static bool OP_R (instr_info *, int, int);
+static bool OP_MS (instr_info *, int, int);
+static bool OP_XS (instr_info *, int, int);
static bool OP_M (instr_info *, int, int);
static bool OP_VEX (instr_info *, int, int);
static bool OP_VexR (instr_info *, int, int);
uint8_t rex_used;
bool need_modrm;
- unsigned char need_vex;
+ bool need_vex;
bool has_sib;
/* Flags for ins->prefixes which we somehow handled when printing the
bool two_source_ops;
- /* Record whether EVEX masking is used incorrectly. */
- bool illegal_masking;
-
unsigned char op_ad;
signed char op_index[MAX_OPERANDS];
bool op_riprel[MAX_OPERANDS];
#define Mw { OP_M, w_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
-#define Mymm { OP_M, ymm_mode }
#define Gb { OP_G, b_mode }
#define Gbnd { OP_G, bnd_mode }
#define Gv { OP_G, v_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
#define EXymm { OP_EX, ymm_mode }
+#define EXtmm { OP_EX, tmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
#define EXymmq { OP_EX, ymmq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
-#define Rd { OP_R, d_mode }
-#define Rdq { OP_R, dq_mode }
-#define Nq { OP_R, q_mode }
-#define Ux { OP_R, x_mode }
-#define Uxmm { OP_R, xmm_mode }
-#define Rxmmq { OP_R, xmmq_mode }
-#define Rymm { OP_R, ymm_mode }
-#define Rtmm { OP_R, tmm_mode }
+#define MS { OP_MS, v_mode }
+#define XS { OP_XS, v_mode }
#define EMCq { OP_EMC, q_mode }
#define MXC { OP_MXC, 0 }
#define OPSUF { OP_3DNowSuffix, 0 }
#define MaskG { OP_G, mask_mode }
#define MaskE { OP_E, mask_mode }
-#define MaskR { OP_R, mask_mode }
#define MaskBDE { OP_E, mask_bd_mode }
#define MaskVex { OP_VEX, mask_mode }
#define FLOAT NULL, { { NULL, FLOATCODE } }, 0
#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
+#define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
-#define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
-#define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
-#define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
+#define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
+#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
+#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
+#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
-#define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
+#define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
enum
REG_0F1C_P_0_MOD_0,
REG_0F1E_P_1_MOD_3,
REG_0F38D8_PREFIX_1,
- REG_0F3A0F_P_1,
- REG_0F71,
- REG_0F72,
- REG_0F73,
+ REG_0F3A0F_PREFIX_1_MOD_3,
+ REG_0F71_MOD_0,
+ REG_0F72_MOD_0,
+ REG_0F73_MOD_0,
REG_0FA6,
REG_0FA7,
REG_0FAE,
REG_0FBA,
REG_0FC7,
- REG_VEX_0F71,
- REG_VEX_0F72,
- REG_VEX_0F73,
+ REG_VEX_0F71_M_0,
+ REG_VEX_0F72_M_0,
+ REG_VEX_0F73_M_0,
REG_VEX_0FAE,
REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
REG_VEX_0F38F3_L_0,
REG_XOP_09_01_L_0,
REG_XOP_09_02_L_0,
- REG_XOP_09_12_L_0,
+ REG_XOP_09_12_M_1_L_0,
REG_XOP_0A_12_L_0,
REG_EVEX_0F71,
REG_EVEX_0F72,
REG_EVEX_0F73,
- REG_EVEX_0F38C6_L_2,
- REG_EVEX_0F38C7_L_2
+ REG_EVEX_0F38C6_M_0_L_2,
+ REG_EVEX_0F38C7_M_0_L_2
};
enum
{
MOD_62_32BIT = 0,
+ MOD_8D,
MOD_C4_32BIT,
MOD_C5_32BIT,
+ MOD_C6_REG_7,
+ MOD_C7_REG_7,
+ MOD_FF_REG_3,
+ MOD_FF_REG_5,
MOD_0F01_REG_0,
MOD_0F01_REG_1,
MOD_0F01_REG_2,
MOD_0F01_REG_3,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
+ MOD_0F02,
+ MOD_0F03,
MOD_0F12_PREFIX_0,
+ MOD_0F12_PREFIX_2,
+ MOD_0F13,
MOD_0F16_PREFIX_0,
+ MOD_0F16_PREFIX_2,
+ MOD_0F17,
MOD_0F18_REG_0,
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F1B_PREFIX_1,
MOD_0F1C_PREFIX_0,
MOD_0F1E_PREFIX_1,
+ MOD_0F2B_PREFIX_0,
+ MOD_0F2B_PREFIX_1,
+ MOD_0F2B_PREFIX_2,
+ MOD_0F2B_PREFIX_3,
+ MOD_0F50,
+ MOD_0F71,
+ MOD_0F72,
+ MOD_0F73,
MOD_0FAE_REG_0,
MOD_0FAE_REG_1,
MOD_0FAE_REG_2,
MOD_0FAE_REG_5,
MOD_0FAE_REG_6,
MOD_0FAE_REG_7,
+ MOD_0FB2,
+ MOD_0FB4,
+ MOD_0FB5,
+ MOD_0FC3,
+ MOD_0FC7_REG_3,
+ MOD_0FC7_REG_4,
+ MOD_0FC7_REG_5,
MOD_0FC7_REG_6,
MOD_0FC7_REG_7,
+ MOD_0FD7,
+ MOD_0FE7_PREFIX_2,
+ MOD_0FF0_PREFIX_3,
+ MOD_0F382A,
MOD_0F38DC_PREFIX_1,
-
+ MOD_0F38DD_PREFIX_1,
+ MOD_0F38DE_PREFIX_1,
+ MOD_0F38DF_PREFIX_1,
+ MOD_0F38F5,
+ MOD_0F38F6_PREFIX_0,
+ MOD_0F38F8_PREFIX_1,
+ MOD_0F38F8_PREFIX_2,
+ MOD_0F38F8_PREFIX_3,
+ MOD_0F38F9,
+ MOD_0F38FA_PREFIX_1,
+ MOD_0F38FB_PREFIX_1,
+ MOD_0F3A0F_PREFIX_1,
+
+ MOD_VEX_0F12_PREFIX_0,
+ MOD_VEX_0F12_PREFIX_2,
+ MOD_VEX_0F13,
+ MOD_VEX_0F16_PREFIX_0,
+ MOD_VEX_0F16_PREFIX_2,
+ MOD_VEX_0F17,
+ MOD_VEX_0F2B,
+ MOD_VEX_0F41_L_1,
+ MOD_VEX_0F42_L_1,
+ MOD_VEX_0F44_L_0,
+ MOD_VEX_0F45_L_1,
+ MOD_VEX_0F46_L_1,
+ MOD_VEX_0F47_L_1,
+ MOD_VEX_0F4A_L_1,
+ MOD_VEX_0F4B_L_1,
+ MOD_VEX_0F50,
+ MOD_VEX_0F71,
+ MOD_VEX_0F72,
+ MOD_VEX_0F73,
+ MOD_VEX_0F91_L_0,
+ MOD_VEX_0F92_L_0,
+ MOD_VEX_0F93_L_0,
+ MOD_VEX_0F98_L_0,
+ MOD_VEX_0F99_L_0,
+ MOD_VEX_0FAE_REG_2,
+ MOD_VEX_0FAE_REG_3,
+ MOD_VEX_0FD7,
+ MOD_VEX_0FE7,
+ MOD_VEX_0FF0_PREFIX_3,
+ MOD_VEX_0F381A,
+ MOD_VEX_0F382A,
+ MOD_VEX_0F382C,
+ MOD_VEX_0F382D,
+ MOD_VEX_0F382E,
+ MOD_VEX_0F382F,
MOD_VEX_0F3849_X86_64_L_0_W_0,
+ MOD_VEX_0F384B_X86_64_L_0_W_0,
+ MOD_VEX_0F385A,
+ MOD_VEX_0F385C_X86_64,
+ MOD_VEX_0F385E_X86_64,
+ MOD_VEX_0F386C_X86_64,
+ MOD_VEX_0F388C,
+ MOD_VEX_0F388E,
+ MOD_VEX_0F3A30_L_0,
+ MOD_VEX_0F3A31_L_0,
+ MOD_VEX_0F3A32_L_0,
+ MOD_VEX_0F3A33_L_0,
+
+ MOD_XOP_09_12,
+
+ MOD_EVEX_0F381A,
+ MOD_EVEX_0F381B,
+ MOD_EVEX_0F3828_P_1,
+ MOD_EVEX_0F382A_P_1_W_1,
+ MOD_EVEX_0F3838_P_1,
+ MOD_EVEX_0F383A_P_1_W_0,
+ MOD_EVEX_0F385A,
+ MOD_EVEX_0F385B,
+ MOD_EVEX_0F387A_W_0,
+ MOD_EVEX_0F387B_W_0,
+ MOD_EVEX_0F387C,
+ MOD_EVEX_0F38C6,
+ MOD_EVEX_0F38C7,
};
enum
RM_0F1E_P_1_MOD_3_REG_7,
RM_0FAE_REG_6_MOD_3_P_0,
RM_0FAE_REG_7_MOD_3,
- RM_0F3A0F_P_1_R_0,
+ RM_0F3A0F_P_1_MOD_3_REG_0,
RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
PREFIX_0F38FB,
PREFIX_0F38FC,
PREFIX_0F3A0F,
+ PREFIX_VEX_0F10,
+ PREFIX_VEX_0F11,
PREFIX_VEX_0F12,
PREFIX_VEX_0F16,
PREFIX_VEX_0F2A,
PREFIX_VEX_0F2C,
PREFIX_VEX_0F2D,
- PREFIX_VEX_0F41_L_1_W_0,
- PREFIX_VEX_0F41_L_1_W_1,
- PREFIX_VEX_0F42_L_1_W_0,
- PREFIX_VEX_0F42_L_1_W_1,
- PREFIX_VEX_0F44_L_0_W_0,
- PREFIX_VEX_0F44_L_0_W_1,
- PREFIX_VEX_0F45_L_1_W_0,
- PREFIX_VEX_0F45_L_1_W_1,
- PREFIX_VEX_0F46_L_1_W_0,
- PREFIX_VEX_0F46_L_1_W_1,
- PREFIX_VEX_0F47_L_1_W_0,
- PREFIX_VEX_0F47_L_1_W_1,
- PREFIX_VEX_0F4A_L_1_W_0,
- PREFIX_VEX_0F4A_L_1_W_1,
- PREFIX_VEX_0F4B_L_1_W_0,
- PREFIX_VEX_0F4B_L_1_W_1,
+ PREFIX_VEX_0F2E,
+ PREFIX_VEX_0F2F,
+ PREFIX_VEX_0F41_L_1_M_1_W_0,
+ PREFIX_VEX_0F41_L_1_M_1_W_1,
+ PREFIX_VEX_0F42_L_1_M_1_W_0,
+ PREFIX_VEX_0F42_L_1_M_1_W_1,
+ PREFIX_VEX_0F44_L_0_M_1_W_0,
+ PREFIX_VEX_0F44_L_0_M_1_W_1,
+ PREFIX_VEX_0F45_L_1_M_1_W_0,
+ PREFIX_VEX_0F45_L_1_M_1_W_1,
+ PREFIX_VEX_0F46_L_1_M_1_W_0,
+ PREFIX_VEX_0F46_L_1_M_1_W_1,
+ PREFIX_VEX_0F47_L_1_M_1_W_0,
+ PREFIX_VEX_0F47_L_1_M_1_W_1,
+ PREFIX_VEX_0F4A_L_1_M_1_W_0,
+ PREFIX_VEX_0F4A_L_1_M_1_W_1,
+ PREFIX_VEX_0F4B_L_1_M_1_W_0,
+ PREFIX_VEX_0F4B_L_1_M_1_W_1,
+ PREFIX_VEX_0F51,
+ PREFIX_VEX_0F52,
+ PREFIX_VEX_0F53,
+ PREFIX_VEX_0F58,
+ PREFIX_VEX_0F59,
+ PREFIX_VEX_0F5A,
+ PREFIX_VEX_0F5B,
+ PREFIX_VEX_0F5C,
+ PREFIX_VEX_0F5D,
+ PREFIX_VEX_0F5E,
+ PREFIX_VEX_0F5F,
PREFIX_VEX_0F6F,
PREFIX_VEX_0F70,
+ PREFIX_VEX_0F7C,
+ PREFIX_VEX_0F7D,
PREFIX_VEX_0F7E,
PREFIX_VEX_0F7F,
PREFIX_VEX_0F90_L_0_W_0,
PREFIX_VEX_0F90_L_0_W_1,
- PREFIX_VEX_0F91_L_0_W_0,
- PREFIX_VEX_0F91_L_0_W_1,
- PREFIX_VEX_0F92_L_0_W_0,
- PREFIX_VEX_0F92_L_0_W_1,
- PREFIX_VEX_0F93_L_0_W_0,
- PREFIX_VEX_0F93_L_0_W_1,
- PREFIX_VEX_0F98_L_0_W_0,
- PREFIX_VEX_0F98_L_0_W_1,
- PREFIX_VEX_0F99_L_0_W_0,
- PREFIX_VEX_0F99_L_0_W_1,
+ PREFIX_VEX_0F91_L_0_M_0_W_0,
+ PREFIX_VEX_0F91_L_0_M_0_W_1,
+ PREFIX_VEX_0F92_L_0_M_1_W_0,
+ PREFIX_VEX_0F92_L_0_M_1_W_1,
+ PREFIX_VEX_0F93_L_0_M_1_W_0,
+ PREFIX_VEX_0F93_L_0_M_1_W_1,
+ PREFIX_VEX_0F98_L_0_M_1_W_0,
+ PREFIX_VEX_0F98_L_0_M_1_W_1,
+ PREFIX_VEX_0F99_L_0_M_1_W_0,
+ PREFIX_VEX_0F99_L_0_M_1_W_1,
+ PREFIX_VEX_0FC2,
+ PREFIX_VEX_0FD0,
+ PREFIX_VEX_0FE6,
+ PREFIX_VEX_0FF0,
PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
- PREFIX_VEX_0F384B_X86_64_L_0_W_0,
+ PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0,
PREFIX_VEX_0F3850_W_0,
PREFIX_VEX_0F3851_W_0,
- PREFIX_VEX_0F385C_X86_64_L_0_W_0,
- PREFIX_VEX_0F385E_X86_64_L_0_W_0,
- PREFIX_VEX_0F386C_X86_64_L_0_W_0,
+ PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0,
+ PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0,
+ PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0,
PREFIX_VEX_0F3872,
PREFIX_VEX_0F38B0_W_0,
PREFIX_VEX_0F38B1_W_0,
- PREFIX_VEX_0F38D2_W_0,
- PREFIX_VEX_0F38D3_W_0,
- PREFIX_VEX_0F38CB,
- PREFIX_VEX_0F38CC,
- PREFIX_VEX_0F38CD,
- PREFIX_VEX_0F38DA_W_0,
PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0,
PREFIX_VEX_0F38F7_L_0,
enum
{
- VEX_LEN_0F12_P_0 = 0,
- VEX_LEN_0F12_P_2,
- VEX_LEN_0F13,
- VEX_LEN_0F16_P_0,
- VEX_LEN_0F16_P_2,
- VEX_LEN_0F17,
+ VEX_LEN_0F12_P_0_M_0 = 0,
+ VEX_LEN_0F12_P_0_M_1,
+#define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
+ VEX_LEN_0F13_M_0,
+ VEX_LEN_0F16_P_0_M_0,
+ VEX_LEN_0F16_P_0_M_1,
+#define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
+ VEX_LEN_0F17_M_0,
VEX_LEN_0F41,
VEX_LEN_0F42,
VEX_LEN_0F44,
VEX_LEN_0F93,
VEX_LEN_0F98,
VEX_LEN_0F99,
- VEX_LEN_0FAE_R_2,
- VEX_LEN_0FAE_R_3,
+ VEX_LEN_0FAE_R_2_M_0,
+ VEX_LEN_0FAE_R_3_M_0,
VEX_LEN_0FC4,
+ VEX_LEN_0FC5,
VEX_LEN_0FD6,
+ VEX_LEN_0FF7,
VEX_LEN_0F3816,
VEX_LEN_0F3819,
- VEX_LEN_0F381A,
+ VEX_LEN_0F381A_M_0,
VEX_LEN_0F3836,
VEX_LEN_0F3841,
VEX_LEN_0F3849_X86_64,
VEX_LEN_0F384B_X86_64,
- VEX_LEN_0F385A,
- VEX_LEN_0F385C_X86_64,
- VEX_LEN_0F385E_X86_64,
- VEX_LEN_0F386C_X86_64,
- VEX_LEN_0F38CB_P_3_W_0,
- VEX_LEN_0F38CC_P_3_W_0,
- VEX_LEN_0F38CD_P_3_W_0,
- VEX_LEN_0F38DA_W_0_P_0,
- VEX_LEN_0F38DA_W_0_P_2,
+ VEX_LEN_0F385A_M_0,
+ VEX_LEN_0F385C_X86_64_M_1,
+ VEX_LEN_0F385E_X86_64_M_1,
+ VEX_LEN_0F386C_X86_64_M_1,
VEX_LEN_0F38DB,
VEX_LEN_0F38F2,
VEX_LEN_0F38F3,
VEX_LEN_0F3A61,
VEX_LEN_0F3A62,
VEX_LEN_0F3A63,
- VEX_LEN_0F3ADE_W_0,
VEX_LEN_0F3ADF,
VEX_LEN_0F3AF0,
- VEX_LEN_XOP_08_85,
- VEX_LEN_XOP_08_86,
- VEX_LEN_XOP_08_87,
- VEX_LEN_XOP_08_8E,
- VEX_LEN_XOP_08_8F,
- VEX_LEN_XOP_08_95,
- VEX_LEN_XOP_08_96,
- VEX_LEN_XOP_08_97,
- VEX_LEN_XOP_08_9E,
- VEX_LEN_XOP_08_9F,
- VEX_LEN_XOP_08_A3,
- VEX_LEN_XOP_08_A6,
- VEX_LEN_XOP_08_B6,
- VEX_LEN_XOP_08_C0,
- VEX_LEN_XOP_08_C1,
- VEX_LEN_XOP_08_C2,
- VEX_LEN_XOP_08_C3,
- VEX_LEN_XOP_08_CC,
- VEX_LEN_XOP_08_CD,
- VEX_LEN_XOP_08_CE,
- VEX_LEN_XOP_08_CF,
- VEX_LEN_XOP_08_EC,
- VEX_LEN_XOP_08_ED,
- VEX_LEN_XOP_08_EE,
- VEX_LEN_XOP_08_EF,
- VEX_LEN_XOP_09_01,
- VEX_LEN_XOP_09_02,
- VEX_LEN_XOP_09_12,
- VEX_LEN_XOP_09_82_W_0,
- VEX_LEN_XOP_09_83_W_0,
- VEX_LEN_XOP_09_90,
- VEX_LEN_XOP_09_91,
- VEX_LEN_XOP_09_92,
- VEX_LEN_XOP_09_93,
- VEX_LEN_XOP_09_94,
- VEX_LEN_XOP_09_95,
- VEX_LEN_XOP_09_96,
- VEX_LEN_XOP_09_97,
- VEX_LEN_XOP_09_98,
- VEX_LEN_XOP_09_99,
- VEX_LEN_XOP_09_9A,
- VEX_LEN_XOP_09_9B,
- VEX_LEN_XOP_09_C1,
- VEX_LEN_XOP_09_C2,
- VEX_LEN_XOP_09_C3,
- VEX_LEN_XOP_09_C6,
- VEX_LEN_XOP_09_C7,
- VEX_LEN_XOP_09_CB,
- VEX_LEN_XOP_09_D1,
- VEX_LEN_XOP_09_D2,
- VEX_LEN_XOP_09_D3,
- VEX_LEN_XOP_09_D6,
- VEX_LEN_XOP_09_D7,
- VEX_LEN_XOP_09_DB,
- VEX_LEN_XOP_09_E1,
- VEX_LEN_XOP_09_E2,
- VEX_LEN_XOP_09_E3,
- VEX_LEN_XOP_0A_12,
+ VEX_LEN_0FXOP_08_85,
+ VEX_LEN_0FXOP_08_86,
+ VEX_LEN_0FXOP_08_87,
+ VEX_LEN_0FXOP_08_8E,
+ VEX_LEN_0FXOP_08_8F,
+ VEX_LEN_0FXOP_08_95,
+ VEX_LEN_0FXOP_08_96,
+ VEX_LEN_0FXOP_08_97,
+ VEX_LEN_0FXOP_08_9E,
+ VEX_LEN_0FXOP_08_9F,
+ VEX_LEN_0FXOP_08_A3,
+ VEX_LEN_0FXOP_08_A6,
+ VEX_LEN_0FXOP_08_B6,
+ VEX_LEN_0FXOP_08_C0,
+ VEX_LEN_0FXOP_08_C1,
+ VEX_LEN_0FXOP_08_C2,
+ VEX_LEN_0FXOP_08_C3,
+ VEX_LEN_0FXOP_08_CC,
+ VEX_LEN_0FXOP_08_CD,
+ VEX_LEN_0FXOP_08_CE,
+ VEX_LEN_0FXOP_08_CF,
+ VEX_LEN_0FXOP_08_EC,
+ VEX_LEN_0FXOP_08_ED,
+ VEX_LEN_0FXOP_08_EE,
+ VEX_LEN_0FXOP_08_EF,
+ VEX_LEN_0FXOP_09_01,
+ VEX_LEN_0FXOP_09_02,
+ VEX_LEN_0FXOP_09_12_M_1,
+ VEX_LEN_0FXOP_09_82_W_0,
+ VEX_LEN_0FXOP_09_83_W_0,
+ VEX_LEN_0FXOP_09_90,
+ VEX_LEN_0FXOP_09_91,
+ VEX_LEN_0FXOP_09_92,
+ VEX_LEN_0FXOP_09_93,
+ VEX_LEN_0FXOP_09_94,
+ VEX_LEN_0FXOP_09_95,
+ VEX_LEN_0FXOP_09_96,
+ VEX_LEN_0FXOP_09_97,
+ VEX_LEN_0FXOP_09_98,
+ VEX_LEN_0FXOP_09_99,
+ VEX_LEN_0FXOP_09_9A,
+ VEX_LEN_0FXOP_09_9B,
+ VEX_LEN_0FXOP_09_C1,
+ VEX_LEN_0FXOP_09_C2,
+ VEX_LEN_0FXOP_09_C3,
+ VEX_LEN_0FXOP_09_C6,
+ VEX_LEN_0FXOP_09_C7,
+ VEX_LEN_0FXOP_09_CB,
+ VEX_LEN_0FXOP_09_D1,
+ VEX_LEN_0FXOP_09_D2,
+ VEX_LEN_0FXOP_09_D3,
+ VEX_LEN_0FXOP_09_D6,
+ VEX_LEN_0FXOP_09_D7,
+ VEX_LEN_0FXOP_09_DB,
+ VEX_LEN_0FXOP_09_E1,
+ VEX_LEN_0FXOP_09_E2,
+ VEX_LEN_0FXOP_09_E3,
+ VEX_LEN_0FXOP_0A_12,
};
enum
{
EVEX_LEN_0F3816 = 0,
EVEX_LEN_0F3819,
- EVEX_LEN_0F381A,
- EVEX_LEN_0F381B,
+ EVEX_LEN_0F381A_M_0,
+ EVEX_LEN_0F381B_M_0,
EVEX_LEN_0F3836,
- EVEX_LEN_0F385A,
- EVEX_LEN_0F385B,
- EVEX_LEN_0F38C6,
- EVEX_LEN_0F38C7,
+ EVEX_LEN_0F385A_M_0,
+ EVEX_LEN_0F385B_M_0,
+ EVEX_LEN_0F38C6_M_0,
+ EVEX_LEN_0F38C7_M_0,
EVEX_LEN_0F3A00,
EVEX_LEN_0F3A01,
EVEX_LEN_0F3A18,
enum
{
- VEX_W_0F41_L_1 = 0,
- VEX_W_0F42_L_1,
- VEX_W_0F44_L_0,
- VEX_W_0F45_L_1,
- VEX_W_0F46_L_1,
- VEX_W_0F47_L_1,
- VEX_W_0F4A_L_1,
- VEX_W_0F4B_L_1,
+ VEX_W_0F41_L_1_M_1 = 0,
+ VEX_W_0F42_L_1_M_1,
+ VEX_W_0F44_L_0_M_1,
+ VEX_W_0F45_L_1_M_1,
+ VEX_W_0F46_L_1_M_1,
+ VEX_W_0F47_L_1_M_1,
+ VEX_W_0F4A_L_1_M_1,
+ VEX_W_0F4B_L_1_M_1,
VEX_W_0F90_L_0,
- VEX_W_0F91_L_0,
- VEX_W_0F92_L_0,
- VEX_W_0F93_L_0,
- VEX_W_0F98_L_0,
- VEX_W_0F99_L_0,
+ VEX_W_0F91_L_0_M_0,
+ VEX_W_0F92_L_0_M_1,
+ VEX_W_0F93_L_0_M_1,
+ VEX_W_0F98_L_0_M_1,
+ VEX_W_0F99_L_0_M_1,
VEX_W_0F380C,
VEX_W_0F380D,
VEX_W_0F380E,
VEX_W_0F3816_L_1,
VEX_W_0F3818,
VEX_W_0F3819_L_1,
- VEX_W_0F381A_L_1,
- VEX_W_0F382C,
- VEX_W_0F382D,
- VEX_W_0F382E,
- VEX_W_0F382F,
+ VEX_W_0F381A_M_0_L_1,
+ VEX_W_0F382C_M_0,
+ VEX_W_0F382D_M_0,
+ VEX_W_0F382E_M_0,
+ VEX_W_0F382F_M_0,
VEX_W_0F3836,
VEX_W_0F3846,
VEX_W_0F3849_X86_64_L_0,
VEX_W_0F3853,
VEX_W_0F3858,
VEX_W_0F3859,
- VEX_W_0F385A_L_0,
- VEX_W_0F385C_X86_64_L_0,
- VEX_W_0F385E_X86_64_L_0,
- VEX_W_0F386C_X86_64_L_0,
+ VEX_W_0F385A_M_0_L_0,
+ VEX_W_0F385C_X86_64_M_1_L_0,
+ VEX_W_0F385E_X86_64_M_1_L_0,
+ VEX_W_0F386C_X86_64_M_1_L_0,
VEX_W_0F3872_P_1,
VEX_W_0F3878,
VEX_W_0F3879,
VEX_W_0F38B1,
VEX_W_0F38B4,
VEX_W_0F38B5,
- VEX_W_0F38CB_P_3,
- VEX_W_0F38CC_P_3,
- VEX_W_0F38CD_P_3,
VEX_W_0F38CF,
- VEX_W_0F38D2,
- VEX_W_0F38D3,
- VEX_W_0F38DA,
VEX_W_0F3A00_L_1,
VEX_W_0F3A01_L_1,
VEX_W_0F3A02,
VEX_W_0F3A4C,
VEX_W_0F3ACE,
VEX_W_0F3ACF,
- VEX_W_0F3ADE,
-
- VEX_W_XOP_08_85_L_0,
- VEX_W_XOP_08_86_L_0,
- VEX_W_XOP_08_87_L_0,
- VEX_W_XOP_08_8E_L_0,
- VEX_W_XOP_08_8F_L_0,
- VEX_W_XOP_08_95_L_0,
- VEX_W_XOP_08_96_L_0,
- VEX_W_XOP_08_97_L_0,
- VEX_W_XOP_08_9E_L_0,
- VEX_W_XOP_08_9F_L_0,
- VEX_W_XOP_08_A6_L_0,
- VEX_W_XOP_08_B6_L_0,
- VEX_W_XOP_08_C0_L_0,
- VEX_W_XOP_08_C1_L_0,
- VEX_W_XOP_08_C2_L_0,
- VEX_W_XOP_08_C3_L_0,
- VEX_W_XOP_08_CC_L_0,
- VEX_W_XOP_08_CD_L_0,
- VEX_W_XOP_08_CE_L_0,
- VEX_W_XOP_08_CF_L_0,
- VEX_W_XOP_08_EC_L_0,
- VEX_W_XOP_08_ED_L_0,
- VEX_W_XOP_08_EE_L_0,
- VEX_W_XOP_08_EF_L_0,
-
- VEX_W_XOP_09_80,
- VEX_W_XOP_09_81,
- VEX_W_XOP_09_82,
- VEX_W_XOP_09_83,
- VEX_W_XOP_09_C1_L_0,
- VEX_W_XOP_09_C2_L_0,
- VEX_W_XOP_09_C3_L_0,
- VEX_W_XOP_09_C6_L_0,
- VEX_W_XOP_09_C7_L_0,
- VEX_W_XOP_09_CB_L_0,
- VEX_W_XOP_09_D1_L_0,
- VEX_W_XOP_09_D2_L_0,
- VEX_W_XOP_09_D3_L_0,
- VEX_W_XOP_09_D6_L_0,
- VEX_W_XOP_09_D7_L_0,
- VEX_W_XOP_09_DB_L_0,
- VEX_W_XOP_09_E1_L_0,
- VEX_W_XOP_09_E2_L_0,
- VEX_W_XOP_09_E3_L_0,
+
+ VEX_W_0FXOP_08_85_L_0,
+ VEX_W_0FXOP_08_86_L_0,
+ VEX_W_0FXOP_08_87_L_0,
+ VEX_W_0FXOP_08_8E_L_0,
+ VEX_W_0FXOP_08_8F_L_0,
+ VEX_W_0FXOP_08_95_L_0,
+ VEX_W_0FXOP_08_96_L_0,
+ VEX_W_0FXOP_08_97_L_0,
+ VEX_W_0FXOP_08_9E_L_0,
+ VEX_W_0FXOP_08_9F_L_0,
+ VEX_W_0FXOP_08_A6_L_0,
+ VEX_W_0FXOP_08_B6_L_0,
+ VEX_W_0FXOP_08_C0_L_0,
+ VEX_W_0FXOP_08_C1_L_0,
+ VEX_W_0FXOP_08_C2_L_0,
+ VEX_W_0FXOP_08_C3_L_0,
+ VEX_W_0FXOP_08_CC_L_0,
+ VEX_W_0FXOP_08_CD_L_0,
+ VEX_W_0FXOP_08_CE_L_0,
+ VEX_W_0FXOP_08_CF_L_0,
+ VEX_W_0FXOP_08_EC_L_0,
+ VEX_W_0FXOP_08_ED_L_0,
+ VEX_W_0FXOP_08_EE_L_0,
+ VEX_W_0FXOP_08_EF_L_0,
+
+ VEX_W_0FXOP_09_80,
+ VEX_W_0FXOP_09_81,
+ VEX_W_0FXOP_09_82,
+ VEX_W_0FXOP_09_83,
+ VEX_W_0FXOP_09_C1_L_0,
+ VEX_W_0FXOP_09_C2_L_0,
+ VEX_W_0FXOP_09_C3_L_0,
+ VEX_W_0FXOP_09_C6_L_0,
+ VEX_W_0FXOP_09_C7_L_0,
+ VEX_W_0FXOP_09_CB_L_0,
+ VEX_W_0FXOP_09_D1_L_0,
+ VEX_W_0FXOP_09_D2_L_0,
+ VEX_W_0FXOP_09_D3_L_0,
+ VEX_W_0FXOP_09_D6_L_0,
+ VEX_W_0FXOP_09_D7_L_0,
+ VEX_W_0FXOP_09_DB_L_0,
+ VEX_W_0FXOP_09_E1_L_0,
+ VEX_W_0FXOP_09_E2_L_0,
+ VEX_W_0FXOP_09_E3_L_0,
EVEX_W_0F5B_P_0,
EVEX_W_0F62,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
EVEX_W_0F3819_L_n,
- EVEX_W_0F381A_L_n,
- EVEX_W_0F381B_L_2,
+ EVEX_W_0F381A_M_0_L_n,
+ EVEX_W_0F381B_M_0_L_2,
EVEX_W_0F381E,
EVEX_W_0F381F,
EVEX_W_0F3820_P_1,
EVEX_W_0F3837,
EVEX_W_0F383A_P_1,
EVEX_W_0F3859,
- EVEX_W_0F385A_L_n,
- EVEX_W_0F385B_L_2,
+ EVEX_W_0F385A_M_0_L_n,
+ EVEX_W_0F385B_M_0_L_2,
EVEX_W_0F3870,
EVEX_W_0F3872_P_2,
EVEX_W_0F387A,
'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
prefix or if suffix_always is true.
'U' unused.
- 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
+ 'V' unused.
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
- 'Y' => no output, mark EVEX.aaa != 0 as bad.
+ 'Y' unused.
'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
"XV" => print "{vex} " pseudo prefix
"XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
is used by an EVEX-encoded (AVX512VL) instruction.
- "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
- "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
being false, or no operand at all in 64bit mode, or if suffix_always
is true.
{ "movB", { Gb, EbS }, 0 },
{ "movS", { Gv, EvS }, 0 },
{ "movD", { Sv, Sw }, 0 },
- { "leaS", { Gv, M }, 0 },
+ { MOD_TABLE (MOD_8D) },
{ "movD", { Sw, Sv }, 0 },
{ REG_TABLE (REG_8F) },
/* 90 */
/* 00 */
{ REG_TABLE (REG_0F00 ) },
{ REG_TABLE (REG_0F01 ) },
- { "larS", { Gv, Sv }, 0 },
- { "lslS", { Gv, Sv }, 0 },
+ { MOD_TABLE (MOD_0F02) },
+ { MOD_TABLE (MOD_0F03) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
{ PREFIX_TABLE (PREFIX_0F10) },
{ PREFIX_TABLE (PREFIX_0F11) },
{ PREFIX_TABLE (PREFIX_0F12) },
- { "movlpX", { Mq, XM }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F13) },
{ "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
{ "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F16) },
- { "movhpX", { Mq, XM }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F17) },
/* 18 */
{ REG_TABLE (REG_0F18) },
{ "nopQ", { Ev }, 0 },
{ Bad_Opcode },
{ "getsec", { XX }, 0 },
/* 38 */
- { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
+ { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
{ Bad_Opcode },
- { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
+ { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "cmovleS", { Gv, Ev }, 0 },
{ "cmovgS", { Gv, Ev }, 0 },
/* 50 */
- { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F50) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
{ PREFIX_TABLE (PREFIX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_0F70) },
- { REG_TABLE (REG_0F71) },
- { REG_TABLE (REG_0F72) },
- { REG_TABLE (REG_0F73) },
+ { MOD_TABLE (MOD_0F71) },
+ { MOD_TABLE (MOD_0F72) },
+ { MOD_TABLE (MOD_0F73) },
{ "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
{ "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
{ "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
/* b0 */
{ "cmpxchgB", { Ebh1, Gb }, 0 },
{ "cmpxchgS", { Evh1, Gv }, 0 },
- { "lssS", { Gv, Mp }, 0 },
+ { MOD_TABLE (MOD_0FB2) },
{ "btrS", { Evh1, Gv }, 0 },
- { "lfsS", { Gv, Mp }, 0 },
- { "lgsS", { Gv, Mp }, 0 },
+ { MOD_TABLE (MOD_0FB4) },
+ { MOD_TABLE (MOD_0FB5) },
{ "movz{bR|x}", { Gv, Eb }, 0 },
{ "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
/* b8 */
{ "xaddB", { Ebh1, Gb }, 0 },
{ "xaddS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FC2) },
- { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0FC3) },
{ "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
- { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE },
+ { "pextrw", { Gd, MS, Ib }, PREFIX_OPCODE },
{ "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
{ REG_TABLE (REG_0FC7) },
/* c8 */
{ "paddq", { MX, EM }, PREFIX_OPCODE },
{ "pmullw", { MX, EM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0FD6) },
- { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0FD7) },
/* d8 */
{ "psubusb", { MX, EM }, PREFIX_OPCODE },
{ "psubusw", { MX, EM }, PREFIX_OPCODE },
/* REG_8F */
{
{ "pop{P|}", { stackEv }, 0 },
- { XOP_8F_TABLE () },
+ { XOP_8F_TABLE (XOP_09) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { XOP_8F_TABLE () },
+ { XOP_8F_TABLE (XOP_09) },
},
/* REG_C0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { RM_TABLE (RM_C6_REG_7) },
+ { MOD_TABLE (MOD_C6_REG_7) },
},
/* REG_C7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { RM_TABLE (RM_C7_REG_7) },
+ { MOD_TABLE (MOD_C7_REG_7) },
},
/* REG_D0 */
{
{ "incQ", { Evh1 }, 0 },
{ "decQ", { Evh1 }, 0 },
{ "call{@|}", { NOTRACK, indirEv, BND }, 0 },
- { "{l|}call^", { indirEp }, 0 },
+ { MOD_TABLE (MOD_FF_REG_3) },
{ "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
- { "{l|}jmp^", { indirEp }, 0 },
+ { MOD_TABLE (MOD_FF_REG_5) },
{ "push{P|}", { stackEv }, 0 },
{ Bad_Opcode },
},
{
{ "sldtD", { Sv }, 0 },
{ "strD", { Sv }, 0 },
- { "lldtD", { Sv }, 0 },
- { "ltrD", { Sv }, 0 },
- { "verrD", { Sv }, 0 },
- { "verwD", { Sv }, 0 },
+ { "lldt", { Ew }, 0 },
+ { "ltr", { Ew }, 0 },
+ { "verr", { Ew }, 0 },
+ { "verw", { Ew }, 0 },
{ X86_64_TABLE (X86_64_0F00_REG_6) },
{ Bad_Opcode },
},
{ "aesencwide256kl", { M }, 0 },
{ "aesdecwide256kl", { M }, 0 },
},
- /* REG_0F3A0F_P_1 */
+ /* REG_0F3A0F_PREFIX_1_MOD_3 */
{
- { RM_TABLE (RM_0F3A0F_P_1_R_0) },
+ { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
},
- /* REG_0F71 */
+ /* REG_0F71_MOD_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "psrlw", { Nq, Ib }, PREFIX_OPCODE },
+ { "psrlw", { MS, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "psraw", { Nq, Ib }, PREFIX_OPCODE },
+ { "psraw", { MS, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "psllw", { Nq, Ib }, PREFIX_OPCODE },
+ { "psllw", { MS, Ib }, PREFIX_OPCODE },
},
- /* REG_0F72 */
+ /* REG_0F72_MOD_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "psrld", { Nq, Ib }, PREFIX_OPCODE },
+ { "psrld", { MS, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "psrad", { Nq, Ib }, PREFIX_OPCODE },
+ { "psrad", { MS, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "pslld", { Nq, Ib }, PREFIX_OPCODE },
+ { "pslld", { MS, Ib }, PREFIX_OPCODE },
},
- /* REG_0F73 */
+ /* REG_0F73_MOD_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "psrlq", { Nq, Ib }, PREFIX_OPCODE },
- { "psrldq", { Ux, Ib }, PREFIX_DATA },
+ { "psrlq", { MS, Ib }, PREFIX_OPCODE },
+ { "psrldq", { XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- { "psllq", { Nq, Ib }, PREFIX_OPCODE },
- { "pslldq", { Ux, Ib }, PREFIX_DATA },
+ { "psllq", { MS, Ib }, PREFIX_OPCODE },
+ { "pslldq", { XS, Ib }, PREFIX_DATA },
},
/* REG_0FA6 */
{
{ Bad_Opcode },
{ "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
{ Bad_Opcode },
- { "xrstors", { FXSAVE }, 0 },
- { "xsavec", { FXSAVE }, 0 },
- { "xsaves", { FXSAVE }, 0 },
+ { MOD_TABLE (MOD_0FC7_REG_3) },
+ { MOD_TABLE (MOD_0FC7_REG_4) },
+ { MOD_TABLE (MOD_0FC7_REG_5) },
{ MOD_TABLE (MOD_0FC7_REG_6) },
{ MOD_TABLE (MOD_0FC7_REG_7) },
},
- /* REG_VEX_0F71 */
+ /* REG_VEX_0F71_M_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
},
- /* REG_VEX_0F72 */
+ /* REG_VEX_0F72_M_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
},
- /* REG_VEX_0F73 */
+ /* REG_VEX_0F73_M_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
- { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
+ { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
- { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
+ { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
+ { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
},
/* REG_VEX_0FAE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
- { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
+ { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
+ { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
},
/* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
{
{ Bad_Opcode },
{ "blci", { VexGdq, Edq }, 0 },
},
- /* REG_XOP_09_12_L_0 */
+ /* REG_XOP_09_12_M_1_L_0 */
{
- { "llwpcb", { Rdq }, 0 },
- { "slwpcb", { Rdq }, 0 },
+ { "llwpcb", { Edq }, 0 },
+ { "slwpcb", { Edq }, 0 },
},
/* REG_XOP_0A_12_L_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "lkgsD", { Sv }, 0 },
+ { "lkgs", { Ew }, 0 },
},
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
/* PREFIX_0F10 */
{
- { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
- { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
- { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
- { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
+ { "movups", { XM, EXx }, PREFIX_OPCODE },
+ { "movss", { XM, EXd }, PREFIX_OPCODE },
+ { "movupd", { XM, EXx }, PREFIX_OPCODE },
+ { "movsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F11 */
{
- { "%XEVmovupX", { EXxS, XM }, 0 },
- { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
- { "%XEVmovupX", { EXxS, XM }, 0 },
- { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
+ { "movups", { EXxS, XM }, PREFIX_OPCODE },
+ { "movss", { EXdS, XM }, PREFIX_OPCODE },
+ { "movupd", { EXxS, XM }, PREFIX_OPCODE },
+ { "movsd", { EXqS, XM }, PREFIX_OPCODE },
},
/* PREFIX_0F12 */
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
- { "movsldup", { XM, EXx }, 0 },
- { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
- { "movddup", { XM, EXq }, 0 },
+ { "movsldup", { XM, EXx }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F12_PREFIX_2) },
+ { "movddup", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F16 */
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
- { "movshdup", { XM, EXx }, 0 },
- { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
+ { "movshdup", { XM, EXx }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F18_REG_6_MOD_0_X86_64 */
/* PREFIX_0F2B */
{
- { "movntps", { Mx, XM }, 0 },
- { "movntss", { Md, XM }, 0 },
- { "movntpd", { Mx, XM }, 0 },
- { "movntsd", { Mq, XM }, 0 },
+ { MOD_TABLE (MOD_0F2B_PREFIX_0) },
+ { MOD_TABLE (MOD_0F2B_PREFIX_1) },
+ { MOD_TABLE (MOD_0F2B_PREFIX_2) },
+ { MOD_TABLE (MOD_0F2B_PREFIX_3) },
},
/* PREFIX_0F2C */
/* PREFIX_0F2E */
{
- { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
+ { "ucomiss",{ XM, EXd }, 0 },
{ Bad_Opcode },
- { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
+ { "ucomisd",{ XM, EXq }, 0 },
},
/* PREFIX_0F2F */
{
- { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
+ { "comiss", { XM, EXd }, 0 },
{ Bad_Opcode },
- { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
+ { "comisd", { XM, EXq }, 0 },
},
/* PREFIX_0F51 */
{
- { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
- { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
- { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
+ { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
+ { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
+ { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F52 */
{
- { "Vrsqrtps", { XM, EXx }, 0 },
- { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
+ { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
+ { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F53 */
{
- { "Vrcpps", { XM, EXx }, 0 },
- { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
+ { "rcpps", { XM, EXx }, PREFIX_OPCODE },
+ { "rcpss", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F58 */
{
- { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "addps", { XM, EXx }, PREFIX_OPCODE },
+ { "addss", { XM, EXd }, PREFIX_OPCODE },
+ { "addpd", { XM, EXx }, PREFIX_OPCODE },
+ { "addsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F59 */
{
- { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "mulps", { XM, EXx }, PREFIX_OPCODE },
+ { "mulss", { XM, EXd }, PREFIX_OPCODE },
+ { "mulpd", { XM, EXx }, PREFIX_OPCODE },
+ { "mulsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5A */
{
- { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
- { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
- { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
+ { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
+ { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5B */
{
- { "Vcvtdq2ps", { XM, EXx }, 0 },
- { "Vcvttps2dq", { XM, EXx }, 0 },
- { "Vcvtps2dq", { XM, EXx }, 0 },
+ { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
+ { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F5C */
{
- { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "subps", { XM, EXx }, PREFIX_OPCODE },
+ { "subss", { XM, EXd }, PREFIX_OPCODE },
+ { "subpd", { XM, EXx }, PREFIX_OPCODE },
+ { "subsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5D */
{
- { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
- { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
- { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+ { "minps", { XM, EXx }, PREFIX_OPCODE },
+ { "minss", { XM, EXd }, PREFIX_OPCODE },
+ { "minpd", { XM, EXx }, PREFIX_OPCODE },
+ { "minsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5E */
{
- { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
- { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
- { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ { "divps", { XM, EXx }, PREFIX_OPCODE },
+ { "divss", { XM, EXd }, PREFIX_OPCODE },
+ { "divpd", { XM, EXx }, PREFIX_OPCODE },
+ { "divsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5F */
{
- { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
- { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
- { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
- { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+ { "maxps", { XM, EXx }, PREFIX_OPCODE },
+ { "maxss", { XM, EXd }, PREFIX_OPCODE },
+ { "maxpd", { XM, EXx }, PREFIX_OPCODE },
+ { "maxsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F60 */
{
{"vmread", { Em, Gm }, 0 },
{ Bad_Opcode },
- {"extrq", { Uxmm, Ib, Ib }, 0 },
- {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
+ {"extrq", { XS, Ib, Ib }, 0 },
+ {"insertq", { XM, XS, Ib, Ib }, 0 },
},
/* PREFIX_0F79 */
{
{"vmwrite", { Gm, Em }, 0 },
{ Bad_Opcode },
- {"extrq", { XM, Uxmm }, 0 },
- {"insertq", { XM, Uxmm }, 0 },
+ {"extrq", { XM, XS }, 0 },
+ {"insertq", { XM, XS }, 0 },
},
/* PREFIX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "Vhaddpd", { XM, Vex, EXx }, 0 },
- { "Vhaddps", { XM, Vex, EXx }, 0 },
+ { "haddpd", { XM, EXx }, PREFIX_OPCODE },
+ { "haddps", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "Vhsubpd", { XM, Vex, EXx }, 0 },
- { "Vhsubps", { XM, Vex, EXx }, 0 },
+ { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
+ { "hsubps", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F7E */
/* PREFIX_0FC2 */
{
- { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
- { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
- { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
- { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
+ { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
+ { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
+ { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
+ { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
},
/* PREFIX_0FC7_REG_6_MOD_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "VaddsubpX", { XM, Vex, EXx }, 0 },
- { "VaddsubpX", { XM, Vex, EXx }, 0 },
+ { "addsubpd", { XM, EXx }, 0 },
+ { "addsubps", { XM, EXx }, 0 },
},
/* PREFIX_0FD6 */
{
{ Bad_Opcode },
- { "movq2dq",{ XM, Nq }, 0 },
+ { "movq2dq",{ XM, MS }, 0 },
{ "movq", { EXqS, XM }, 0 },
- { "movdq2q",{ MX, Ux }, 0 },
+ { "movdq2q",{ MX, XS }, 0 },
},
/* PREFIX_0FE6 */
{
{ Bad_Opcode },
- { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
- { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
- { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
+ { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
+ { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0FE7 */
{
- { "movntq", { Mq, MX }, 0 },
+ { "movntq", { Mq, MX }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movntdq", { Mx, XM }, 0 },
+ { MOD_TABLE (MOD_0FE7_PREFIX_2) },
},
/* PREFIX_0FF0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "Vlddqu", { XM, M }, 0 },
+ { MOD_TABLE (MOD_0FF0_PREFIX_3) },
},
/* PREFIX_0FF7 */
{
- { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
+ { "maskmovq", { MX, MS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
+ { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
},
/* PREFIX_0F38D8 */
/* PREFIX_0F38DD */
{
{ Bad_Opcode },
- { "aesdec128kl", { XM, M }, 0 },
+ { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
{ "aesenclast", { XM, EXx }, 0 },
},
/* PREFIX_0F38DE */
{
{ Bad_Opcode },
- { "aesenc256kl", { XM, M }, 0 },
+ { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
{ "aesdec", { XM, EXx }, 0 },
},
/* PREFIX_0F38DF */
{
{ Bad_Opcode },
- { "aesdec256kl", { XM, M }, 0 },
+ { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
{ "aesdeclast", { XM, EXx }, 0 },
},
/* PREFIX_0F38F6 */
{
- { "wrssK", { M, Gdq }, 0 },
- { "adoxS", { Gdq, Edq}, 0 },
- { "adcxS", { Gdq, Edq}, 0 },
+ { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
+ { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
+ { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
{ Bad_Opcode },
},
/* PREFIX_0F38F8 */
{
{ Bad_Opcode },
- { "enqcmds", { Gva, M }, 0 },
- { "movdir64b", { Gva, M }, 0 },
- { "enqcmd", { Gva, M }, 0 },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
},
/* PREFIX_0F38FA */
{
{ Bad_Opcode },
- { "encodekey128", { Gd, Rd }, 0 },
+ { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
},
/* PREFIX_0F38FB */
{
{ Bad_Opcode },
- { "encodekey256", { Gd, Rd }, 0 },
+ { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
/* PREFIX_0F38FC */
/* PREFIX_0F3A0F */
{
{ Bad_Opcode },
- { REG_TABLE (REG_0F3A0F_P_1) },
+ { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
+ },
+
+ /* PREFIX_VEX_0F10 */
+ {
+ { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
+ { "%XEvmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
+ { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
+ { "%XEvmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
+ },
+
+ /* PREFIX_VEX_0F11 */
+ {
+ { "%XEvmovupX", { EXxS, XM }, 0 },
+ { "%XEvmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
+ { "%XEvmovupX", { EXxS, XM }, 0 },
+ { "%XEvmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
},
/* PREFIX_VEX_0F12 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
{ "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
{ "%XEvmov%XDdup", { XM, EXymmq }, 0 },
},
/* PREFIX_VEX_0F16 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
{ "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
- { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+ { "%XEvcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
{ Bad_Opcode },
- { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
+ { "%XEvcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
{ "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
},
- /* PREFIX_VEX_0F41_L_1_W_0 */
+ /* PREFIX_VEX_0F2E */
{
- { "kandw", { MaskG, MaskVex, MaskR }, 0 },
+ { "%XEvucomisX", { XMScalar, EXd, EXxEVexS }, 0 },
{ Bad_Opcode },
- { "kandb", { MaskG, MaskVex, MaskR }, 0 },
+ { "%XEvucomisX", { XMScalar, EXq, EXxEVexS }, 0 },
},
- /* PREFIX_VEX_0F41_L_1_W_1 */
+ /* PREFIX_VEX_0F2F */
{
- { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ { "%XEvcomisX", { XMScalar, EXd, EXxEVexS }, 0 },
{ Bad_Opcode },
- { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ { "%XEvcomisX", { XMScalar, EXq, EXxEVexS }, 0 },
},
- /* PREFIX_VEX_0F42_L_1_W_0 */
+ /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
{
- { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandb", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F42_L_1_W_1 */
+ /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
{
- { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandq", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandd", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F44_L_0_W_0 */
+ /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
{
- { "knotw", { MaskG, MaskR }, 0 },
+ { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "knotb", { MaskG, MaskR }, 0 },
+ { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F44_L_0_W_1 */
+ /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
{
- { "knotq", { MaskG, MaskR }, 0 },
+ { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "knotd", { MaskG, MaskR }, 0 },
+ { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F45_L_1_W_0 */
+ /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
{
- { "korw", { MaskG, MaskVex, MaskR }, 0 },
+ { "knotw", { MaskG, MaskE }, 0 },
{ Bad_Opcode },
- { "korb", { MaskG, MaskVex, MaskR }, 0 },
+ { "knotb", { MaskG, MaskE }, 0 },
},
- /* PREFIX_VEX_0F45_L_1_W_1 */
+ /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
{
- { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ { "knotq", { MaskG, MaskE }, 0 },
{ Bad_Opcode },
- { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ { "knotd", { MaskG, MaskE }, 0 },
},
- /* PREFIX_VEX_0F46_L_1_W_0 */
+ /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
{
- { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
+ { "korw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
+ { "korb", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F46_L_1_W_1 */
+ /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
{
- { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ { "korq", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ { "kord", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F47_L_1_W_0 */
+ /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
{
- { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F47_L_1_W_1 */
+ /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
{
- { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F4A_L_1_W_0 */
+ /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
{
- { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F4A_L_1_W_1 */
+ /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
{
- { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxord", { MaskG, MaskVex, MaskE }, 0 },
},
- /* PREFIX_VEX_0F4B_L_1_W_0 */
+ /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
{
- { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
{ Bad_Opcode },
- { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
+ {
+ { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
+ { Bad_Opcode },
+ { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
+ {
+ { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
+ { Bad_Opcode },
+ { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
+ {
+ { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F51 */
+ {
+ { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
+ { "%XEvsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
+ { "%XEvsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F52 */
+ {
+ { "vrsqrtps", { XM, EXx }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
},
- /* PREFIX_VEX_0F4B_L_1_W_1 */
+ /* PREFIX_VEX_0F53 */
{
- { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ { "vrcpps", { XM, EXx }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXd }, 0 },
+ },
+
+ /* PREFIX_VEX_0F58 */
+ {
+ { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F59 */
+ {
+ { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5A */
+ {
+ { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+ { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+ { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5B */
+ {
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ { "vcvtps2dq", { XM, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5C */
+ {
+ { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5D */
+ {
+ { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
+ { "%XEvmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
+ { "%XEvmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5E */
+ {
+ { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+ { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
+ { "%XEvdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+ },
+
+ /* PREFIX_VEX_0F5F */
+ {
+ { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
+ { "%XEvmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+ { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
+ { "%XEvmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
},
/* PREFIX_VEX_0F6F */
{ "vpshuflw", { XM, EXx, Ib }, 0 },
},
+ /* PREFIX_VEX_0F7C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F7D */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
+ },
+
/* PREFIX_VEX_0F7E */
{
{ Bad_Opcode },
{ "kmovd", { MaskG, MaskBDE }, 0 },
},
- /* PREFIX_VEX_0F91_L_0_W_0 */
+ /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
{
- { "kmovw", { Mw, MaskG }, 0 },
+ { "kmovw", { Ew, MaskG }, 0 },
{ Bad_Opcode },
- { "kmovb", { Mb, MaskG }, 0 },
+ { "kmovb", { Eb, MaskG }, 0 },
},
- /* PREFIX_VEX_0F91_L_0_W_1 */
+ /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
{
- { "kmovq", { Mq, MaskG }, 0 },
+ { "kmovq", { Eq, MaskG }, 0 },
{ Bad_Opcode },
- { "kmovd", { Md, MaskG }, 0 },
+ { "kmovd", { Ed, MaskG }, 0 },
},
- /* PREFIX_VEX_0F92_L_0_W_0 */
+ /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
{
- { "kmovw", { MaskG, Rdq }, 0 },
+ { "kmovw", { MaskG, Edq }, 0 },
{ Bad_Opcode },
- { "kmovb", { MaskG, Rdq }, 0 },
- { "kmovd", { MaskG, Rdq }, 0 },
+ { "kmovb", { MaskG, Edq }, 0 },
+ { "kmovd", { MaskG, Edq }, 0 },
},
- /* PREFIX_VEX_0F92_L_0_W_1 */
+ /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "kmovK", { MaskG, Rdq }, 0 },
+ { "kmovK", { MaskG, Edq }, 0 },
},
- /* PREFIX_VEX_0F93_L_0_W_0 */
+ /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
{
- { "kmovw", { Gdq, MaskR }, 0 },
+ { "kmovw", { Gdq, MaskE }, 0 },
{ Bad_Opcode },
- { "kmovb", { Gdq, MaskR }, 0 },
- { "kmovd", { Gdq, MaskR }, 0 },
+ { "kmovb", { Gdq, MaskE }, 0 },
+ { "kmovd", { Gdq, MaskE }, 0 },
},
- /* PREFIX_VEX_0F93_L_0_W_1 */
+ /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "kmovK", { Gdq, MaskR }, 0 },
+ { "kmovK", { Gdq, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
+ {
+ { "kortestw", { MaskG, MaskE }, 0 },
+ { Bad_Opcode },
+ { "kortestb", { MaskG, MaskE }, 0 },
+ },
+
+ /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
+ {
+ { "kortestq", { MaskG, MaskE }, 0 },
+ { Bad_Opcode },
+ { "kortestd", { MaskG, MaskE }, 0 },
},
- /* PREFIX_VEX_0F98_L_0_W_0 */
+ /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
{
- { "kortestw", { MaskG, MaskR }, 0 },
+ { "ktestw", { MaskG, MaskE }, 0 },
{ Bad_Opcode },
- { "kortestb", { MaskG, MaskR }, 0 },
+ { "ktestb", { MaskG, MaskE }, 0 },
},
- /* PREFIX_VEX_0F98_L_0_W_1 */
+ /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
{
- { "kortestq", { MaskG, MaskR }, 0 },
+ { "ktestq", { MaskG, MaskE }, 0 },
{ Bad_Opcode },
- { "kortestd", { MaskG, MaskR }, 0 },
+ { "ktestd", { MaskG, MaskE }, 0 },
},
- /* PREFIX_VEX_0F99_L_0_W_0 */
+ /* PREFIX_VEX_0FC2 */
{
- { "ktestw", { MaskG, MaskR }, 0 },
+ { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
+ { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
+ },
+
+ /* PREFIX_VEX_0FD0 */
+ {
+ { Bad_Opcode },
{ Bad_Opcode },
- { "ktestb", { MaskG, MaskR }, 0 },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},
- /* PREFIX_VEX_0F99_L_0_W_1 */
+ /* PREFIX_VEX_0FE6 */
{
- { "ktestq", { MaskG, MaskR }, 0 },
{ Bad_Opcode },
- { "ktestd", { MaskG, MaskR }, 0 },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0FF0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
},
/* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
{ RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
},
- /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
+ /* PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0 */
{
{ Bad_Opcode },
{ "tilestored", { MVexSIBMEM, TMM }, 0 },
{ "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
{ "vpdpbssds", { XM, Vex, EXx }, 0 },
},
- /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
+ /* PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0 */
{
{ Bad_Opcode },
- { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
{ Bad_Opcode },
- { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tdpfp16ps", { TMM, EXtmm, VexTmm }, 0 },
},
- /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
+ /* PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0 */
{
- { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
- { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
- { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
- { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
+ { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
+ { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
+ { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
+ { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
},
- /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
+ /* PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0 */
{
- { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tcmmrlfp16ps", { TMM, EXtmm, VexTmm }, 0 },
{ Bad_Opcode },
- { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
+ { "tcmmimfp16ps", { TMM, EXtmm, VexTmm }, 0 },
},
/* PREFIX_VEX_0F3872 */
{ "vbcstnesh2ps", { XM, Mw }, 0 },
},
- /* PREFIX_VEX_0F38D2_W_0 */
- {
- { "vpdpwuud", { XM, Vex, EXx }, 0 },
- { "vpdpwsud", { XM, Vex, EXx }, 0 },
- { "vpdpwusd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38D3_W_0 */
- {
- { "vpdpwuuds", { XM, Vex, EXx }, 0 },
- { "vpdpwsuds", { XM, Vex, EXx }, 0 },
- { "vpdpwusds", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38CB */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
- },
-
- /* PREFIX_VEX_0F38CC */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
- },
-
- /* PREFIX_VEX_0F38CD */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
- },
-
- /* PREFIX_VEX_0F38DA_W_0 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
- { "vsm4key4", { XM, Vex, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
- { "vsm4rnds4", { XM, Vex, EXx }, 0 },
- },
-
/* PREFIX_VEX_0F38F5_L_0 */
{
{ "bzhiS", { Gdq, Edq, VexGdq }, 0 },
/* X86_64_62 */
{
{ MOD_TABLE (MOD_62_32BIT) },
- { EVEX_TABLE () },
+ { EVEX_TABLE (EVEX_0F) },
},
/* X86_64_63 */
{
- { "arplS", { Sv, Gv }, 0 },
+ { "arpl", { Ew, Gw }, 0 },
{ "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
/* X86_64_C4 */
{
{ MOD_TABLE (MOD_C4_32BIT) },
- { VEX_C4_TABLE () },
+ { VEX_C4_TABLE (VEX_0F) },
},
/* X86_64_C5 */
{
{ MOD_TABLE (MOD_C5_32BIT) },
- { VEX_C5_TABLE () },
+ { VEX_C5_TABLE (VEX_0F) },
},
/* X86_64_CE */
/* X86_64_VEX_0F385C */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
+ { MOD_TABLE (MOD_VEX_0F385C_X86_64) },
},
/* X86_64_VEX_0F385E */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64) },
},
/* X86_64_VEX_0F386C */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
+ { MOD_TABLE (MOD_VEX_0F386C_X86_64) },
},
/* X86_64_VEX_0F38E0 */
/* 28 */
{ "pmuldq", { XM, EXx }, PREFIX_DATA },
{ "pcmpeqq", { XM, EXx }, PREFIX_DATA },
- { "movntdqa", { XM, Mx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_0F382A) },
{ "packusdw", { XM, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "wrussK", { M, Gdq }, PREFIX_DATA },
+ { MOD_TABLE (MOD_0F38F5) },
{ PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
{ PREFIX_TABLE (PREFIX_0F38F8) },
- { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38F9) },
{ PREFIX_TABLE (PREFIX_0F38FA) },
{ PREFIX_TABLE (PREFIX_0F38FB) },
{ PREFIX_TABLE (PREFIX_0F38FC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{
/* 00 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
+ { MOD_TABLE (MOD_XOP_09_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { VEX_W_TABLE (VEX_W_XOP_09_80) },
- { VEX_W_TABLE (VEX_W_XOP_09_81) },
- { VEX_W_TABLE (VEX_W_XOP_09_82) },
- { VEX_W_TABLE (VEX_W_XOP_09_83) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
/* 98 */
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* d0 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* e0 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
{ "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { PREFIX_TABLE (PREFIX_0F10) },
- { PREFIX_TABLE (PREFIX_0F11) },
+ { PREFIX_TABLE (PREFIX_VEX_0F10) },
+ { PREFIX_TABLE (PREFIX_VEX_0F11) },
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
- { VEX_LEN_TABLE (VEX_LEN_0F13) },
+ { MOD_TABLE (MOD_VEX_0F13) },
{ "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
- { VEX_LEN_TABLE (VEX_LEN_0F17) },
+ { MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ "vmovapX", { XM, EXx }, PREFIX_OPCODE },
{ "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
- { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F2D) },
- { PREFIX_TABLE (PREFIX_0F2E) },
- { PREFIX_TABLE (PREFIX_0F2F) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2F) },
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
- { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE },
- { PREFIX_TABLE (PREFIX_0F51) },
- { PREFIX_TABLE (PREFIX_0F52) },
- { PREFIX_TABLE (PREFIX_0F53) },
+ { MOD_TABLE (MOD_VEX_0F50) },
+ { PREFIX_TABLE (PREFIX_VEX_0F51) },
+ { PREFIX_TABLE (PREFIX_VEX_0F52) },
+ { PREFIX_TABLE (PREFIX_VEX_0F53) },
{ "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
/* 58 */
- { PREFIX_TABLE (PREFIX_0F58) },
- { PREFIX_TABLE (PREFIX_0F59) },
- { PREFIX_TABLE (PREFIX_0F5A) },
- { PREFIX_TABLE (PREFIX_0F5B) },
- { PREFIX_TABLE (PREFIX_0F5C) },
- { PREFIX_TABLE (PREFIX_0F5D) },
- { PREFIX_TABLE (PREFIX_0F5E) },
- { PREFIX_TABLE (PREFIX_0F5F) },
+ { PREFIX_TABLE (PREFIX_VEX_0F58) },
+ { PREFIX_TABLE (PREFIX_VEX_0F59) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5F) },
/* 60 */
{ "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_VEX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_VEX_0F70) },
- { REG_TABLE (REG_VEX_0F71) },
- { REG_TABLE (REG_VEX_0F72) },
- { REG_TABLE (REG_VEX_0F73) },
+ { MOD_TABLE (MOD_VEX_0F71) },
+ { MOD_TABLE (MOD_VEX_0F72) },
+ { MOD_TABLE (MOD_VEX_0F73) },
{ "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F7C) },
- { PREFIX_TABLE (PREFIX_0F7D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7D) },
{ PREFIX_TABLE (PREFIX_VEX_0F7E) },
{ PREFIX_TABLE (PREFIX_VEX_0F7F) },
/* 80 */
/* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0FC2) },
+ { PREFIX_TABLE (PREFIX_VEX_0FC2) },
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0FC4) },
- { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0FC5) },
{ "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
/* d0 */
- { PREFIX_TABLE (PREFIX_0FD0) },
+ { PREFIX_TABLE (PREFIX_VEX_0FD0) },
{ "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
{ VEX_LEN_TABLE (VEX_LEN_0FD6) },
- { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0FD7) },
/* d8 */
{ "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
- { PREFIX_TABLE (PREFIX_0FE6) },
- { "vmovntdq", { Mx, XM }, PREFIX_DATA },
+ { PREFIX_TABLE (PREFIX_VEX_0FE6) },
+ { MOD_TABLE (MOD_VEX_0FE7) },
/* e8 */
{ "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
/* f0 */
- { PREFIX_TABLE (PREFIX_0FF0) },
+ { PREFIX_TABLE (PREFIX_VEX_0FF0) },
{ "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
{ "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
- { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0FF7) },
/* f8 */
{ "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
/* 18 */
{ VEX_W_TABLE (VEX_W_0F3818) },
{ VEX_LEN_TABLE (VEX_LEN_0F3819) },
- { VEX_LEN_TABLE (VEX_LEN_0F381A) },
+ { MOD_TABLE (MOD_VEX_0F381A) },
{ Bad_Opcode },
{ "vpabsb", { XM, EXx }, PREFIX_DATA },
{ "vpabsw", { XM, EXx }, PREFIX_DATA },
/* 28 */
{ "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
{ "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
- { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F382A) },
{ "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
- { VEX_W_TABLE (VEX_W_0F382C) },
- { VEX_W_TABLE (VEX_W_0F382D) },
- { VEX_W_TABLE (VEX_W_0F382E) },
- { VEX_W_TABLE (VEX_W_0F382F) },
+ { MOD_TABLE (MOD_VEX_0F382C) },
+ { MOD_TABLE (MOD_VEX_0F382D) },
+ { MOD_TABLE (MOD_VEX_0F382E) },
+ { MOD_TABLE (MOD_VEX_0F382F) },
/* 30 */
{ "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
{ "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
/* 58 */
{ VEX_W_TABLE (VEX_W_0F3858) },
{ VEX_W_TABLE (VEX_W_0F3859) },
- { VEX_LEN_TABLE (VEX_LEN_0F385A) },
+ { MOD_TABLE (MOD_VEX_0F385A) },
{ Bad_Opcode },
{ X86_64_TABLE (X86_64_VEX_0F385C) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F388C) },
{ Bad_Opcode },
- { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F388E) },
{ Bad_Opcode },
/* 90 */
{ "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
- { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
- { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F38CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38D2) },
- { VEX_W_TABLE (VEX_W_0F38D3) },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38DA) },
+ { Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0F38DB) },
{ "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
{ "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3ADE) },
+ { Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
/* e0 */
{ Bad_Opcode },
#include "i386-dis-evex.h"
static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F12_P_0 */
+ /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
{
- { MOD_TABLE (MOD_0F12_PREFIX_0) },
+ { "%XEvmovlpX", { XM, Vex, EXq }, 0 },
},
- /* VEX_LEN_0F12_P_2 */
+ /* VEX_LEN_0F12_P_0_M_1 */
{
- { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
+ { "%XEvmovhlp%XS", { XM, Vex, EXq }, 0 },
},
- /* VEX_LEN_0F13 */
+ /* VEX_LEN_0F13_M_0 */
{
- { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE },
+ { "%XEvmovlpX", { EXq, XM }, PREFIX_OPCODE },
},
- /* VEX_LEN_0F16_P_0 */
+ /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
{
- { MOD_TABLE (MOD_0F16_PREFIX_0) },
+ { "%XEvmovhpX", { XM, Vex, EXq }, 0 },
},
- /* VEX_LEN_0F16_P_2 */
+ /* VEX_LEN_0F16_P_0_M_1 */
{
- { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
+ { "%XEvmovlhp%XS", { XM, Vex, EXq }, 0 },
},
- /* VEX_LEN_0F17 */
+ /* VEX_LEN_0F17_M_0 */
{
- { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE },
+ { "%XEvmovhpX", { EXq, XM }, PREFIX_OPCODE },
},
/* VEX_LEN_0F41 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F41_L_1) },
+ { MOD_TABLE (MOD_VEX_0F41_L_1) },
},
/* VEX_LEN_0F42 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F42_L_1) },
+ { MOD_TABLE (MOD_VEX_0F42_L_1) },
},
/* VEX_LEN_0F44 */
{
- { VEX_W_TABLE (VEX_W_0F44_L_0) },
+ { MOD_TABLE (MOD_VEX_0F44_L_0) },
},
/* VEX_LEN_0F45 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F45_L_1) },
+ { MOD_TABLE (MOD_VEX_0F45_L_1) },
},
/* VEX_LEN_0F46 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F46_L_1) },
+ { MOD_TABLE (MOD_VEX_0F46_L_1) },
},
/* VEX_LEN_0F47 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F47_L_1) },
+ { MOD_TABLE (MOD_VEX_0F47_L_1) },
},
/* VEX_LEN_0F4A */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4A_L_1) },
+ { MOD_TABLE (MOD_VEX_0F4A_L_1) },
},
/* VEX_LEN_0F4B */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4B_L_1) },
+ { MOD_TABLE (MOD_VEX_0F4B_L_1) },
},
/* VEX_LEN_0F6E */
{
- { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
+ { "%XEvmovK", { XMScalar, Edq }, PREFIX_DATA },
},
/* VEX_LEN_0F77 */
/* VEX_LEN_0F7E_P_1 */
{
- { "%XEvmovqY", { XMScalar, EXq }, 0 },
+ { "%XEvmovq", { XMScalar, EXq }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
/* VEX_LEN_0F91 */
{
- { VEX_W_TABLE (VEX_W_0F91_L_0) },
+ { MOD_TABLE (MOD_VEX_0F91_L_0) },
},
/* VEX_LEN_0F92 */
{
- { VEX_W_TABLE (VEX_W_0F92_L_0) },
+ { MOD_TABLE (MOD_VEX_0F92_L_0) },
},
/* VEX_LEN_0F93 */
{
- { VEX_W_TABLE (VEX_W_0F93_L_0) },
+ { MOD_TABLE (MOD_VEX_0F93_L_0) },
},
/* VEX_LEN_0F98 */
{
- { VEX_W_TABLE (VEX_W_0F98_L_0) },
+ { MOD_TABLE (MOD_VEX_0F98_L_0) },
},
/* VEX_LEN_0F99 */
{
- { VEX_W_TABLE (VEX_W_0F99_L_0) },
+ { MOD_TABLE (MOD_VEX_0F99_L_0) },
},
- /* VEX_LEN_0FAE_R_2 */
+ /* VEX_LEN_0FAE_R_2_M_0 */
{
{ "vldmxcsr", { Md }, 0 },
},
- /* VEX_LEN_0FAE_R_3 */
+ /* VEX_LEN_0FAE_R_3_M_0 */
{
{ "vstmxcsr", { Md }, 0 },
},
/* VEX_LEN_0FC4 */
{
- { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
+ { "%XEvpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0FC5 */
+ {
+ { "%XEvpextrw", { Gd, XS, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0FD6 */
{
- { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
+ { "%XEvmovq", { EXqS, XMScalar }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0FF7 */
+ {
+ { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
},
/* VEX_LEN_0F3816 */
{ VEX_W_TABLE (VEX_W_0F3819_L_1) },
},
- /* VEX_LEN_0F381A */
+ /* VEX_LEN_0F381A_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381A_L_1) },
+ { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
},
/* VEX_LEN_0F3836 */
{ VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
},
- /* VEX_LEN_0F385A */
+ /* VEX_LEN_0F385A_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F385A_L_0) },
+ { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
},
- /* VEX_LEN_0F385C_X86_64 */
+ /* VEX_LEN_0F385C_X86_64_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
+ { VEX_W_TABLE (VEX_W_0F385C_X86_64_M_1_L_0) },
},
- /* VEX_LEN_0F385E_X86_64 */
+ /* VEX_LEN_0F385E_X86_64_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_M_1_L_0) },
},
- /* VEX_LEN_0F386C_X86_64 */
+ /* VEX_LEN_0F386C_X86_64_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
- },
-
- /* VEX_LEN_0F38CB_P_3_W_0 */
- {
- { Bad_Opcode },
- { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
- },
-
- /* VEX_LEN_0F38CC_P_3_W_0 */
- {
- { Bad_Opcode },
- { "vsha512msg1", { XM, Rxmmq }, 0 },
- },
-
- /* VEX_LEN_0F38CD_P_3_W_0 */
- {
- { Bad_Opcode },
- { "vsha512msg2", { XM, Rymm }, 0 },
- },
-
- /* VEX_LEN_0F38DA_W_0_P_0 */
- {
- { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
- },
-
- /* VEX_LEN_0F38DA_W_0_P_2 */
- {
- { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
+ { VEX_W_TABLE (VEX_W_0F386C_X86_64_M_1_L_0) },
},
/* VEX_LEN_0F38DB */
/* VEX_LEN_0F3A20 */
{
- { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
+ { "%XEvpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A21 */
{
- { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
+ { "%XEvinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A22 */
{
- { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
+ { "%XEvpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3A30 */
{
- { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
},
/* VEX_LEN_0F3A31 */
{
- { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
},
/* VEX_LEN_0F3A32 */
{
- { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
},
/* VEX_LEN_0F3A33 */
{
- { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
},
/* VEX_LEN_0F3A38 */
{ "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F3ADE_W_0 */
- {
- { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
- },
-
/* VEX_LEN_0F3ADF */
{
{ "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
{ PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
},
- /* VEX_LEN_XOP_08_85 */
+ /* VEX_LEN_0FXOP_08_85 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
},
- /* VEX_LEN_XOP_08_86 */
+ /* VEX_LEN_0FXOP_08_86 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
},
- /* VEX_LEN_XOP_08_87 */
+ /* VEX_LEN_0FXOP_08_87 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
},
- /* VEX_LEN_XOP_08_8E */
+ /* VEX_LEN_0FXOP_08_8E */
{
- { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
},
- /* VEX_LEN_XOP_08_8F */
+ /* VEX_LEN_0FXOP_08_8F */
{
- { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
},
- /* VEX_LEN_XOP_08_95 */
+ /* VEX_LEN_0FXOP_08_95 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
},
- /* VEX_LEN_XOP_08_96 */
+ /* VEX_LEN_0FXOP_08_96 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
},
- /* VEX_LEN_XOP_08_97 */
+ /* VEX_LEN_0FXOP_08_97 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
},
- /* VEX_LEN_XOP_08_9E */
+ /* VEX_LEN_0FXOP_08_9E */
{
- { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
},
- /* VEX_LEN_XOP_08_9F */
+ /* VEX_LEN_0FXOP_08_9F */
{
- { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
},
- /* VEX_LEN_XOP_08_A3 */
+ /* VEX_LEN_0FXOP_08_A3 */
{
{ "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_LEN_XOP_08_A6 */
+ /* VEX_LEN_0FXOP_08_A6 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
},
- /* VEX_LEN_XOP_08_B6 */
+ /* VEX_LEN_0FXOP_08_B6 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
},
- /* VEX_LEN_XOP_08_C0 */
+ /* VEX_LEN_0FXOP_08_C0 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
},
- /* VEX_LEN_XOP_08_C1 */
+ /* VEX_LEN_0FXOP_08_C1 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
},
- /* VEX_LEN_XOP_08_C2 */
+ /* VEX_LEN_0FXOP_08_C2 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
},
- /* VEX_LEN_XOP_08_C3 */
+ /* VEX_LEN_0FXOP_08_C3 */
{
- { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
},
- /* VEX_LEN_XOP_08_CC */
+ /* VEX_LEN_0FXOP_08_CC */
{
- { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
},
- /* VEX_LEN_XOP_08_CD */
+ /* VEX_LEN_0FXOP_08_CD */
{
- { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
},
- /* VEX_LEN_XOP_08_CE */
+ /* VEX_LEN_0FXOP_08_CE */
{
- { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
},
- /* VEX_LEN_XOP_08_CF */
+ /* VEX_LEN_0FXOP_08_CF */
{
- { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
},
- /* VEX_LEN_XOP_08_EC */
+ /* VEX_LEN_0FXOP_08_EC */
{
- { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
},
- /* VEX_LEN_XOP_08_ED */
+ /* VEX_LEN_0FXOP_08_ED */
{
- { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
},
- /* VEX_LEN_XOP_08_EE */
+ /* VEX_LEN_0FXOP_08_EE */
{
- { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
},
- /* VEX_LEN_XOP_08_EF */
+ /* VEX_LEN_0FXOP_08_EF */
{
- { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
},
- /* VEX_LEN_XOP_09_01 */
+ /* VEX_LEN_0FXOP_09_01 */
{
{ REG_TABLE (REG_XOP_09_01_L_0) },
},
- /* VEX_LEN_XOP_09_02 */
+ /* VEX_LEN_0FXOP_09_02 */
{
{ REG_TABLE (REG_XOP_09_02_L_0) },
},
- /* VEX_LEN_XOP_09_12 */
+ /* VEX_LEN_0FXOP_09_12_M_1 */
{
- { REG_TABLE (REG_XOP_09_12_L_0) },
+ { REG_TABLE (REG_XOP_09_12_M_1_L_0) },
},
- /* VEX_LEN_XOP_09_82_W_0 */
+ /* VEX_LEN_0FXOP_09_82_W_0 */
{
{ "vfrczss", { XM, EXd }, 0 },
},
- /* VEX_LEN_XOP_09_83_W_0 */
+ /* VEX_LEN_0FXOP_09_83_W_0 */
{
{ "vfrczsd", { XM, EXq }, 0 },
},
- /* VEX_LEN_XOP_09_90 */
+ /* VEX_LEN_0FXOP_09_90 */
{
{ "vprotb", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_91 */
+ /* VEX_LEN_0FXOP_09_91 */
{
{ "vprotw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_92 */
+ /* VEX_LEN_0FXOP_09_92 */
{
{ "vprotd", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_93 */
+ /* VEX_LEN_0FXOP_09_93 */
{
{ "vprotq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_94 */
+ /* VEX_LEN_0FXOP_09_94 */
{
{ "vpshlb", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_95 */
+ /* VEX_LEN_0FXOP_09_95 */
{
{ "vpshlw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_96 */
+ /* VEX_LEN_0FXOP_09_96 */
{
{ "vpshld", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_97 */
+ /* VEX_LEN_0FXOP_09_97 */
{
{ "vpshlq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_98 */
+ /* VEX_LEN_0FXOP_09_98 */
{
{ "vpshab", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_99 */
+ /* VEX_LEN_0FXOP_09_99 */
{
{ "vpshaw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_9A */
+ /* VEX_LEN_0FXOP_09_9A */
{
{ "vpshad", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_9B */
+ /* VEX_LEN_0FXOP_09_9B */
{
{ "vpshaq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_XOP_09_C1 */
+ /* VEX_LEN_0FXOP_09_C1 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
},
- /* VEX_LEN_XOP_09_C2 */
+ /* VEX_LEN_0FXOP_09_C2 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
},
- /* VEX_LEN_XOP_09_C3 */
+ /* VEX_LEN_0FXOP_09_C3 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
},
- /* VEX_LEN_XOP_09_C6 */
+ /* VEX_LEN_0FXOP_09_C6 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
},
- /* VEX_LEN_XOP_09_C7 */
+ /* VEX_LEN_0FXOP_09_C7 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
},
- /* VEX_LEN_XOP_09_CB */
+ /* VEX_LEN_0FXOP_09_CB */
{
- { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
},
- /* VEX_LEN_XOP_09_D1 */
+ /* VEX_LEN_0FXOP_09_D1 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
},
- /* VEX_LEN_XOP_09_D2 */
+ /* VEX_LEN_0FXOP_09_D2 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
},
- /* VEX_LEN_XOP_09_D3 */
+ /* VEX_LEN_0FXOP_09_D3 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
},
- /* VEX_LEN_XOP_09_D6 */
+ /* VEX_LEN_0FXOP_09_D6 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
},
- /* VEX_LEN_XOP_09_D7 */
+ /* VEX_LEN_0FXOP_09_D7 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
},
- /* VEX_LEN_XOP_09_DB */
+ /* VEX_LEN_0FXOP_09_DB */
{
- { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
},
- /* VEX_LEN_XOP_09_E1 */
+ /* VEX_LEN_0FXOP_09_E1 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
},
- /* VEX_LEN_XOP_09_E2 */
+ /* VEX_LEN_0FXOP_09_E2 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
},
- /* VEX_LEN_XOP_09_E3 */
+ /* VEX_LEN_0FXOP_09_E3 */
{
- { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
},
- /* VEX_LEN_XOP_0A_12 */
+ /* VEX_LEN_0FXOP_0A_12 */
{
{ REG_TABLE (REG_XOP_0A_12_L_0) },
},
static const struct dis386 vex_w_table[][2] = {
{
/* VEX_W_0F41_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
},
{
/* VEX_W_0F42_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
},
{
/* VEX_W_0F44_L_0_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
},
{
/* VEX_W_0F45_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
},
{
/* VEX_W_0F46_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
},
{
/* VEX_W_0F47_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
},
{
/* VEX_W_0F4A_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
},
{
/* VEX_W_0F4B_L_1_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
},
{
/* VEX_W_0F90_L_0 */
},
{
/* VEX_W_0F91_L_0_M_0 */
- { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
},
{
/* VEX_W_0F92_L_0_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
},
{
/* VEX_W_0F93_L_0_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
},
{
/* VEX_W_0F98_L_0_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
},
{
/* VEX_W_0F99_L_0_M_1 */
- { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
- { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
+ { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
},
{
/* VEX_W_0F380C */
{ "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
},
{
- /* VEX_W_0F381A_L_1 */
+ /* VEX_W_0F381A_M_0_L_1 */
{ "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
},
{
- /* VEX_W_0F382C */
+ /* VEX_W_0F382C_M_0 */
{ "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
},
{
- /* VEX_W_0F382D */
+ /* VEX_W_0F382D_M_0 */
{ "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
},
{
- /* VEX_W_0F382E */
+ /* VEX_W_0F382E_M_0 */
{ "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
},
{
- /* VEX_W_0F382F */
+ /* VEX_W_0F382F_M_0 */
{ "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
},
{
},
{
/* VEX_W_0F384B_X86_64_L_0 */
- { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_L_0_W_0) },
},
{
/* VEX_W_0F3850 */
{ "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
},
{
- /* VEX_W_0F385A_L_0 */
+ /* VEX_W_0F385A_M_0_L_0 */
{ "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
},
{
- /* VEX_W_0F385C_X86_64_L_0 */
- { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
+ /* VEX_W_0F385C_X86_64_M_1_L_0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_M_1_L_0_W_0) },
},
{
- /* VEX_W_0F385E_X86_64_L_0 */
- { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
+ /* VEX_W_0F385E_X86_64_M_1_L_0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_M_1_L_0_W_0) },
},
{
- /* VEX_W_0F386C_X86_64_L_0 */
- { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
+ /* VEX_W_0F386C_X86_64_M_1_L_0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_M_1_L_0_W_0) },
},
{
/* VEX_W_0F3872_P_1 */
{ Bad_Opcode },
{ "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
},
- {
- /* VEX_W_0F38CB_P_3 */
- { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
- },
- {
- /* VEX_W_0F38CC_P_3 */
- { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
- },
- {
- /* VEX_W_0F38CD_P_3 */
- { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
- },
{
/* VEX_W_0F38CF */
{ "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
},
- {
- /* VEX_W_0F38D2 */
- { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
- },
- {
- /* VEX_W_0F38D3 */
- { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
- },
- {
- /* VEX_W_0F38DA */
- { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
- },
{
/* VEX_W_0F3A00_L_1 */
{ Bad_Opcode },
{ Bad_Opcode },
{ "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
- {
- /* VEX_W_0F3ADE */
- { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
- },
- /* VEX_W_XOP_08_85_L_0 */
+ /* VEX_W_0FXOP_08_85_L_0 */
{
{ "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_86_L_0 */
+ /* VEX_W_0FXOP_08_86_L_0 */
{
{ "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_87_L_0 */
+ /* VEX_W_0FXOP_08_87_L_0 */
{
{ "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_8E_L_0 */
+ /* VEX_W_0FXOP_08_8E_L_0 */
{
{ "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_8F_L_0 */
+ /* VEX_W_0FXOP_08_8F_L_0 */
{
{ "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_95_L_0 */
+ /* VEX_W_0FXOP_08_95_L_0 */
{
{ "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_96_L_0 */
+ /* VEX_W_0FXOP_08_96_L_0 */
{
{ "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_97_L_0 */
+ /* VEX_W_0FXOP_08_97_L_0 */
{
{ "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_9E_L_0 */
+ /* VEX_W_0FXOP_08_9E_L_0 */
{
{ "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_9F_L_0 */
+ /* VEX_W_0FXOP_08_9F_L_0 */
{
{ "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_A6_L_0 */
+ /* VEX_W_0FXOP_08_A6_L_0 */
{
{ "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_B6_L_0 */
+ /* VEX_W_0FXOP_08_B6_L_0 */
{
{ "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_W_XOP_08_C0_L_0 */
+ /* VEX_W_0FXOP_08_C0_L_0 */
{
{ "vprotb", { XM, EXx, Ib }, 0 },
},
- /* VEX_W_XOP_08_C1_L_0 */
+ /* VEX_W_0FXOP_08_C1_L_0 */
{
{ "vprotw", { XM, EXx, Ib }, 0 },
},
- /* VEX_W_XOP_08_C2_L_0 */
+ /* VEX_W_0FXOP_08_C2_L_0 */
{
{ "vprotd", { XM, EXx, Ib }, 0 },
},
- /* VEX_W_XOP_08_C3_L_0 */
+ /* VEX_W_0FXOP_08_C3_L_0 */
{
{ "vprotq", { XM, EXx, Ib }, 0 },
},
- /* VEX_W_XOP_08_CC_L_0 */
+ /* VEX_W_0FXOP_08_CC_L_0 */
{
{ "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_CD_L_0 */
+ /* VEX_W_0FXOP_08_CD_L_0 */
{
{ "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_CE_L_0 */
+ /* VEX_W_0FXOP_08_CE_L_0 */
{
{ "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_CF_L_0 */
+ /* VEX_W_0FXOP_08_CF_L_0 */
{
{ "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_EC_L_0 */
+ /* VEX_W_0FXOP_08_EC_L_0 */
{
{ "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_ED_L_0 */
+ /* VEX_W_0FXOP_08_ED_L_0 */
{
{ "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_EE_L_0 */
+ /* VEX_W_0FXOP_08_EE_L_0 */
{
{ "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_08_EF_L_0 */
+ /* VEX_W_0FXOP_08_EF_L_0 */
{
{ "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
},
- /* VEX_W_XOP_09_80 */
+ /* VEX_W_0FXOP_09_80 */
{
{ "vfrczps", { XM, EXx }, 0 },
},
- /* VEX_W_XOP_09_81 */
+ /* VEX_W_0FXOP_09_81 */
{
{ "vfrczpd", { XM, EXx }, 0 },
},
- /* VEX_W_XOP_09_82 */
+ /* VEX_W_0FXOP_09_82 */
{
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
},
- /* VEX_W_XOP_09_83 */
+ /* VEX_W_0FXOP_09_83 */
{
- { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
},
- /* VEX_W_XOP_09_C1_L_0 */
+ /* VEX_W_0FXOP_09_C1_L_0 */
{
{ "vphaddbw", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_C2_L_0 */
+ /* VEX_W_0FXOP_09_C2_L_0 */
{
{ "vphaddbd", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_C3_L_0 */
+ /* VEX_W_0FXOP_09_C3_L_0 */
{
{ "vphaddbq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_C6_L_0 */
+ /* VEX_W_0FXOP_09_C6_L_0 */
{
{ "vphaddwd", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_C7_L_0 */
+ /* VEX_W_0FXOP_09_C7_L_0 */
{
{ "vphaddwq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_CB_L_0 */
+ /* VEX_W_0FXOP_09_CB_L_0 */
{
{ "vphadddq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_D1_L_0 */
+ /* VEX_W_0FXOP_09_D1_L_0 */
{
{ "vphaddubw", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_D2_L_0 */
+ /* VEX_W_0FXOP_09_D2_L_0 */
{
{ "vphaddubd", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_D3_L_0 */
+ /* VEX_W_0FXOP_09_D3_L_0 */
{
{ "vphaddubq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_D6_L_0 */
+ /* VEX_W_0FXOP_09_D6_L_0 */
{
{ "vphadduwd", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_D7_L_0 */
+ /* VEX_W_0FXOP_09_D7_L_0 */
{
{ "vphadduwq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_DB_L_0 */
+ /* VEX_W_0FXOP_09_DB_L_0 */
{
{ "vphaddudq", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_E1_L_0 */
+ /* VEX_W_0FXOP_09_E1_L_0 */
{
{ "vphsubbw", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_E2_L_0 */
+ /* VEX_W_0FXOP_09_E2_L_0 */
{
{ "vphsubwd", { XM, EXxmm }, 0 },
},
- /* VEX_W_XOP_09_E3_L_0 */
+ /* VEX_W_0FXOP_09_E3_L_0 */
{
{ "vphsubdq", { XM, EXxmm }, 0 },
},
{
/* MOD_62_32BIT */
{ "bound{S|}", { Gv, Ma }, 0 },
- { EVEX_TABLE () },
+ { EVEX_TABLE (EVEX_0F) },
+ },
+ {
+ /* MOD_8D */
+ { "leaS", { Gv, M }, 0 },
},
{
/* MOD_C4_32BIT */
{ "lesS", { Gv, Mp }, 0 },
- { VEX_C4_TABLE () },
+ { VEX_C4_TABLE (VEX_0F) },
},
{
/* MOD_C5_32BIT */
{ "ldsS", { Gv, Mp }, 0 },
- { VEX_C5_TABLE () },
+ { VEX_C5_TABLE (VEX_0F) },
+ },
+ {
+ /* MOD_C6_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C6_REG_7) },
+ },
+ {
+ /* MOD_C7_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C7_REG_7) },
+ },
+ {
+ /* MOD_FF_REG_3 */
+ { "{l|}call^", { indirEp }, 0 },
+ },
+ {
+ /* MOD_FF_REG_5 */
+ { "{l|}jmp^", { indirEp }, 0 },
},
{
/* MOD_0F01_REG_0 */
{ "invlpg", { Mb }, 0 },
{ RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
+ {
+ /* MOD_0F02 */
+ { "larS", { Gv, Mw }, 0 },
+ { "larS", { Gv, Ev }, 0 },
+ },
+ {
+ /* MOD_0F03 */
+ { "lslS", { Gv, Mw }, 0 },
+ { "lslS", { Gv, Ev }, 0 },
+ },
{
/* MOD_0F12_PREFIX_0 */
- { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
- { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
+ { "movlpX", { XM, EXq }, 0 },
+ { "movhlps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F12_PREFIX_2 */
+ { "movlpX", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F13 */
+ { "movlpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F16_PREFIX_0 */
- { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
- { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
+ { "movhpX", { XM, EXq }, 0 },
+ { "movlhps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F16_PREFIX_2 */
+ { "movhpX", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F17 */
+ { "movhpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F18_REG_0 */
{ "nopQ", { Ev }, PREFIX_IGNORED },
{ REG_TABLE (REG_0F1E_P_1_MOD_3) },
},
+ {
+ /* MOD_0F2B_PREFIX_0 */
+ {"movntps", { Mx, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_1 */
+ {"movntss", { Md, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_2 */
+ {"movntpd", { Mx, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F2B_PREFIX_3 */
+ {"movntsd", { Mq, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F50 */
+ { Bad_Opcode },
+ { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F71 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_0F71_MOD_0) },
+ },
+ {
+ /* MOD_0F72 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_0F72_MOD_0) },
+ },
+ {
+ /* MOD_0F73 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_0F73_MOD_0) },
+ },
{
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
{ RM_TABLE (RM_0FAE_REG_7_MOD_3) },
},
+ {
+ /* MOD_0FB2 */
+ { "lssS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FB4 */
+ { "lfsS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FB5 */
+ { "lgsS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FC3 */
+ { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0FC7_REG_3 */
+ { "xrstors", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_4 */
+ { "xsavec", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_5 */
+ { "xsaves", { FXSAVE }, 0 },
+ },
{
/* MOD_0FC7_REG_6 */
{ PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
{ "vmptrst", { Mq }, 0 },
{ PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
+ {
+ /* MOD_0FD7 */
+ { Bad_Opcode },
+ { "pmovmskb", { Gdq, MS }, 0 },
+ },
+ {
+ /* MOD_0FE7_PREFIX_2 */
+ { "movntdq", { Mx, XM }, 0 },
+ },
+ {
+ /* MOD_0FF0_PREFIX_3 */
+ { "lddqu", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F382A */
+ { "movntdqa", { XM, Mx }, PREFIX_DATA },
+ },
{
/* MOD_0F38DC_PREFIX_1 */
{ "aesenc128kl", { XM, M }, 0 },
{ "loadiwkey", { XM, EXx }, 0 },
},
+ {
+ /* MOD_0F38DD_PREFIX_1 */
+ { "aesdec128kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38DE_PREFIX_1 */
+ { "aesenc256kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38DF_PREFIX_1 */
+ { "aesdec256kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38F5 */
+ { "wrussK", { M, Gdq }, PREFIX_DATA },
+ },
+ {
+ /* MOD_0F38F6_PREFIX_0 */
+ { "wrssK", { M, Gdq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F8_PREFIX_1 */
+ { "enqcmds", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F8_PREFIX_2 */
+ { "movdir64b", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F8_PREFIX_3 */
+ { "enqcmd", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F9 */
+ { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38FA_PREFIX_1 */
+ { Bad_Opcode },
+ { "encodekey128", { Gd, Ed }, 0 },
+ },
+ {
+ /* MOD_0F38FB_PREFIX_1 */
+ { Bad_Opcode },
+ { "encodekey256", { Gd, Ed }, 0 },
+ },
+ {
+ /* MOD_0F3A0F_PREFIX_1 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
+ },
+ {
+ /* MOD_VEX_0F12_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F12_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F13 */
+ { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
+ },
+ {
+ /* MOD_VEX_0F16_PREFIX_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F16_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F17 */
+ { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
+ },
+ {
+ /* MOD_VEX_0F2B */
+ { "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_VEX_0F41_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F42_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F44_L_0 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F45_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F46_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F47_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F4A_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F4B_L_1 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
+ },
+ {
+ /* MOD_VEX_0F50 */
+ { Bad_Opcode },
+ { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_VEX_0F71 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_VEX_0F71_M_0) },
+ },
+ {
+ /* MOD_VEX_0F72 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_VEX_0F72_M_0) },
+ },
+ {
+ /* MOD_VEX_0F73 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_VEX_0F73_M_0) },
+ },
+ {
+ /* MOD_VEX_0F91_L_0 */
+ { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
+ },
+ {
+ /* MOD_VEX_0F92_L_0 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F93_L_0 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F98_L_0 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0F99_L_0 */
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
+ },
+ {
+ /* MOD_VEX_0FAE_REG_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0FAE_REG_3 */
+ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
+ },
+ {
+ /* MOD_VEX_0FD7 */
+ { Bad_Opcode },
+ { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0FE7 */
+ { "vmovntdq", { Mx, XM }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0FF0_PREFIX_3 */
+ { "vlddqu", { XM, M }, 0 },
+ },
+ {
+ /* MOD_VEX_0F381A */
+ { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382A */
+ { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F382C */
+ { VEX_W_TABLE (VEX_W_0F382C_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382D */
+ { VEX_W_TABLE (VEX_W_0F382D_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382E */
+ { VEX_W_TABLE (VEX_W_0F382E_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382F */
+ { VEX_W_TABLE (VEX_W_0F382F_M_0) },
+ },
{
/* MOD_VEX_0F3849_X86_64_L_0_W_0 */
{ PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
{ PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
},
+ {
+ /* MOD_VEX_0F384B_X86_64_L_0_W_0 */
+ { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0_M_0) },
+ },
+ {
+ /* MOD_VEX_0F385A */
+ { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
+ },
+ {
+ /* MOD_VEX_0F385C_X86_64 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_M_1) },
+ },
+ {
+ /* MOD_VEX_0F385E_X86_64 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_M_1) },
+ },
+ {
+ /* MOD_VEX_0F386C_X86_64 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64_M_1) },
+ },
+ {
+ /* MOD_VEX_0F388C */
+ { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F388E */
+ { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F3A30_L_0 */
+ { Bad_Opcode },
+ { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F3A31_L_0 */
+ { Bad_Opcode },
+ { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F3A32_L_0 */
+ { Bad_Opcode },
+ { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F3A33_L_0 */
+ { Bad_Opcode },
+ { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
+ },
+ {
+ /* MOD_XOP_09_12 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
+ },
#include "i386-dis-evex-mod.h"
};
{ "sfence", { Skip_MODRM }, 0 },
},
{
- /* RM_0F3A0F_P_1_R_0 */
+ /* RM_0F3A0F_P_1_MOD_3_REG_0 */
{ "hreset", { Skip_MODRM, Ib }, 0 },
},
{
ins->vex.prefix = REPNE_PREFIX_OPCODE;
break;
}
- ins->need_vex = 3;
+ ins->need_vex = true;
ins->codep++;
vindex = *ins->codep++;
dp = &xop_table[vex_table_index][vindex];
ins->vex.prefix = REPNE_PREFIX_OPCODE;
break;
}
- ins->need_vex = 3;
+ ins->need_vex = true;
ins->codep++;
vindex = *ins->codep++;
dp = &vex_table[vex_table_index][vindex];
ins->vex.prefix = REPNE_PREFIX_OPCODE;
break;
}
- ins->need_vex = 2;
+ ins->need_vex = true;
ins->codep++;
vindex = *ins->codep++;
- dp = &vex_table[VEX_0F][vindex];
+ dp = &vex_table[dp->op[1].bytemode][vindex];
ins->end_codep = ins->codep;
/* There is no MODRM byte for VEX 77. */
if (vindex != 0x77 && !fetch_modrm (ins))
ins->vex.r = true;
}
- ins->need_vex = 4;
+ ins->need_vex = true;
ins->codep++;
vindex = *ins->codep++;
dp = &evex_table[vex_table_index][vindex];
oappend (&ins, "{");
oappend_register (&ins, reg_name);
oappend (&ins, "}");
-
- if (ins.vex.zeroing)
- oappend (&ins, "{z}");
- }
- else if (ins.vex.zeroing)
- {
- oappend (&ins, "{bad}");
- continue;
}
-
- /* Instructions with a mask register destination allow for
- zeroing-masking only (if any masking at all), which is
- _not_ expressed by EVEX.z. */
- if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
- ins.illegal_masking = true;
+ if (ins.vex.zeroing)
+ oappend (&ins, "{z}");
/* S/G insns require a mask and don't allow
zeroing-masking. */
|| dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
&& (ins.vex.mask_register_specifier == 0
|| ins.vex.zeroing))
- ins.illegal_masking = true;
-
- if (ins.illegal_masking)
oappend (&ins, "/(bad)");
}
}
goto out;
}
+ /* If EVEX.z is set, there must be an actual mask register in use. */
+ if (ins.vex.zeroing && ins.vex.mask_register_specifier == 0)
+ {
+ i386_dis_printf (info, dis_style_text, "(bad)");
+ ret = ins.end_codep - priv.the_buffer;
+ goto out;
+ }
+
switch (dp->prefix_requirement)
{
case PREFIX_DATA:
ins->mnemonicendp += 2;
}
+static bool
+OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ ins->codep++;
+ return true;
+}
+
static bool
dofloat (instr_info *ins, int sizeflag)
{
break;
case 'V':
if (l == 0)
- {
- if (ins->need_vex)
- *ins->obufp++ = 'v';
- }
+ abort ();
else if (l == 1)
{
switch (last[0])
*ins->obufp++ = 's';
break;
case 'Y':
- if (l == 0)
- {
- if (ins->vex.mask_register_specifier)
- ins->illegal_masking = true;
- }
- else if (l == 1 && last[0] == 'X')
+ if (l == 1 && last[0] == 'X')
{
if (!ins->need_vex)
- break;
+ abort ();
if (ins->intel_syntax
|| ((ins->modrm.mod == 3 || ins->vex.b)
&& !(sizeflag & SUFFIX_ALWAYS)))
oappend_char (ins, ':');
}
+static bool
+OP_indirE (instr_info *ins, int bytemode, int sizeflag)
+{
+ if (!ins->intel_syntax)
+ oappend (ins, "*");
+ return OP_E (ins, bytemode, sizeflag);
+}
+
static void
print_operand_value (instr_info *ins, bfd_vma disp,
enum disassembler_style style)
case xmmq_mode:
case evex_half_bcst_xmmqh_mode:
case evex_half_bcst_xmmq_mode:
+ if (!ins->need_vex)
+ abort ();
+
switch (ins->vex.length)
{
- case 0:
case 128:
oappend (ins, "QWORD PTR ");
break;
{
const char (*names)[8];
- /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
- as the consumer will inspect it only for the destination operand. */
- if (bytemode != mask_mode && ins->vex.mask_register_specifier)
- ins->illegal_masking = true;
-
USED_REX (rexmask);
if (ins->rex & rexmask)
reg += 8;
/* Throw away prefixes and 1st. opcode byte. */
struct dis_private *priv = ins->info->private_data;
- ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
+ ins->codep = priv->the_buffer + ins->nr_prefixes + 1;
ins->obufp = stpcpy (ins->obufp, "(bad)");
return true;
}
-static bool
-OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- if (ins->modrm.mod != 3)
- return BadOp (ins);
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- ins->codep++;
- return true;
-}
-
static bool
OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
{
if (ins->vex.evex)
{
-
- /* Zeroing-masking is invalid for memory destinations. Set the flag
- uniformly, as the consumer will inspect it only for the destination
- operand. */
- if (ins->vex.zeroing)
- ins->illegal_masking = true;
-
switch (bytemode)
{
case dw_mode:
return true;
}
- /* Masking is invalid for insns with GPR-like memory destination. Set the
- flag uniformly, as the consumer will inspect it only for the destination
- operand. */
- if (ins->vex.mask_register_specifier)
- ins->illegal_masking = true;
-
return OP_E_memory (ins, bytemode, sizeflag);
}
-static bool
-OP_indirE (instr_info *ins, int bytemode, int sizeflag)
-{
- if (ins->modrm.mod == 3 && bytemode == f_mode)
- /* bad lcall/ljmp */
- return BadOp (ins);
- if (!ins->intel_syntax)
- oappend (ins, "*");
- return OP_E (ins, bytemode, sizeflag);
-}
-
static bool
OP_G (instr_info *ins, int bytemode, int sizeflag)
{
{
switch (ins->vex.length)
{
- case 0:
case 128:
case 256:
names = att_names_xmm;
}
static bool
-OP_R (instr_info *ins, int bytemode, int sizeflag)
+OP_MS (instr_info *ins, int bytemode, int sizeflag)
{
- if (ins->modrm.mod != 3)
- return BadOp (ins);
-
- switch (bytemode)
- {
- case d_mode:
- case dq_mode:
- case mask_mode:
- return OP_E (ins, bytemode, sizeflag);
- case q_mode:
- return OP_EM (ins, x_mode, sizeflag);
- case xmm_mode:
- if (ins->vex.length <= 128)
- break;
- return BadOp (ins);
- }
+ if (ins->modrm.mod == 3)
+ return OP_EM (ins, bytemode, sizeflag);
+ return BadOp (ins);
+}
- return OP_EX (ins, bytemode, sizeflag);
+static bool
+OP_XS (instr_info *ins, int bytemode, int sizeflag)
+{
+ if (ins->modrm.mod == 3)
+ return OP_EX (ins, bytemode, sizeflag);
+ return BadOp (ins);
}
static bool
OP_M (instr_info *ins, int bytemode, int sizeflag)
{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- ins->codep++;
-
if (ins->modrm.mod == 3)
/* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
return BadOp (ins);
-
- if (bytemode == x_mode)
- ins->vex.no_broadcast = true;
-
- return OP_E_memory (ins, bytemode, sizeflag);
+ return OP_E (ins, bytemode, sizeflag);
}
static bool
const char (*names)[8];
if (!ins->need_vex)
- return true;
+ abort ();
reg = ins->vex.register_specifier;
ins->vex.register_specifier = 0;
projects / thirdparty / binutils-gdb.git / blobdiff