aarch64: Add support for Armv8-R DFB alias

[thirdparty/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index b8a6dfc25c07daf58e3fd3c73ba617ccb7c55546..09ee615db1e67a292f2c287a8e07ef3d276a6734 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -889,6 +889,18 @@ typedef struct insn_template
 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
+/* Pseudo prefixes.  */
+#define Prefix_Disp8           0       /* {disp8} */
+#define Prefix_Disp16          1       /* {disp16} */
+#define Prefix_Disp32          2       /* {disp32} */
+#define Prefix_Load            3       /* {load} */
+#define Prefix_Store           4       /* {store} */
+#define Prefix_VEX             5       /* {vex} */
+#define Prefix_VEX3            6       /* {vex3} */
+#define Prefix_EVEX            7       /* {evex} */
+#define Prefix_REX             8       /* {rex} */
+#define Prefix_NoOptimize      9       /* {nooptimize} */
+
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.