/* ppc-dis.c -- Disassemble PowerPC instructions
- Copyright (C) 1994-2017 Free Software Foundation, Inc.
+ Copyright (C) 1994-2018 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of the GNU opcodes library.
#include "sysdep.h"
#include <stdio.h>
-#include "dis-asm.h"
+#include "disassemble.h"
#include "elf-bfd.h"
#include "elf/ppc.h"
#include "opintl.h"
{ "464", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_440
| PPC_OPCODE_ISEL | PPC_OPCODE_RFMCI),
0 },
- { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_440
- | PPC_OPCODE_476 | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
+ { "476", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_476
+ | PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5),
0 },
{ "601", PPC_OPCODE_PPC | PPC_OPCODE_601,
0 },
0 },
{ "750cl", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
, 0 },
+ { "gekko", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
+ , 0 },
+ { "broadway", PPC_OPCODE_PPC | PPC_OPCODE_750 | PPC_OPCODE_PPCPS
+ , 0 },
{ "821", PPC_OPCODE_PPC | PPC_OPCODE_860,
0 },
{ "850", PPC_OPCODE_PPC | PPC_OPCODE_860,
{ "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4),
+ | PPC_OPCODE_E500 | PPC_OPCODE_VLE | PPC_OPCODE_E200Z4
+ | PPC_OPCODE_EFS2 | PPC_OPCODE_LSP),
0 },
{ "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
0 },
{ "e5500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
- | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7),
+ | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
0 },
{ "e6500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_ISEL
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
| PPC_OPCODE_E500MC | PPC_OPCODE_64 | PPC_OPCODE_ALTIVEC
- | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_E6500 | PPC_OPCODE_POWER4
+ | PPC_OPCODE_E6500 | PPC_OPCODE_TMR | PPC_OPCODE_POWER4
| PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_POWER7),
0 },
{ "e500x2", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
0 },
{ "efs", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
0 },
+ { "efs2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2,
+ 0 },
{ "power4", PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4,
0 },
{ "power5", (PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_POWER4
0 },
{ "power8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
{ "power9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
- | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
- | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
{ "ppc", PPC_OPCODE_PPC,
0 },
0 },
{ "pwr8", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
- | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
- | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+ | PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
{ "pwr9", (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
- | PPC_OPCODE_HTM | PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2
- | PPC_OPCODE_VSX | PPC_OPCODE_VSX3 ),
+ | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
0 },
{ "pwrx", PPC_OPCODE_POWER | PPC_OPCODE_POWER2,
0 },
PPC_OPCODE_RAW },
{ "spe", PPC_OPCODE_PPC | PPC_OPCODE_EFS,
PPC_OPCODE_SPE },
+ { "spe2", PPC_OPCODE_PPC | PPC_OPCODE_EFS | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE,
+ PPC_OPCODE_SPE2 },
{ "titan", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
0 },
{ "vle", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
| PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
- | PPC_OPCODE_E500),
+ | PPC_OPCODE_LSP | PPC_OPCODE_EFS2 | PPC_OPCODE_SPE2),
PPC_OPCODE_VLE },
{ "vsx", PPC_OPCODE_PPC,
PPC_OPCODE_VSX },
- { "htm", PPC_OPCODE_PPC,
- PPC_OPCODE_HTM },
};
/* Switch between Booke and VLE dialects for interlinked dumps. */
case bfd_mach_ppc_601:
dialect = ppc_parse_cpu (dialect, &sticky, "601");
break;
+ case bfd_mach_ppc_750:
+ dialect = ppc_parse_cpu (dialect, &sticky, "750cl");
+ break;
case bfd_mach_ppc_a35:
case bfd_mach_ppc_rs64ii:
case bfd_mach_ppc_rs64iii:
dialect = ppc_parse_cpu (dialect, &sticky, "vle");
break;
default:
- dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
+ if (info->arch == bfd_arch_powerpc)
+ dialect = ppc_parse_cpu (dialect, &sticky, "power9") | PPC_OPCODE_ANY;
+ else
+ dialect = ppc_parse_cpu (dialect, &sticky, "pwr");
break;
}
else if ((new_cpu = ppc_parse_cpu (dialect, &sticky, opt)) != 0)
dialect = new_cpu;
else
- fprintf (stderr, _("warning: ignoring unknown -M%s option\n"), opt);
+ /* xgettext: c-format */
+ opcodes_error_handler (_("warning: ignoring unknown -M%s option"), opt);
}
info->private_data = priv;
POWERPC_DIALECT(info) = dialect;
}
-#define PPC_OPCD_SEGS 64
-static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS+1];
-#define VLE_OPCD_SEGS 32
-static unsigned short vle_opcd_indices[VLE_OPCD_SEGS+1];
+#define PPC_OPCD_SEGS (1 + PPC_OP (-1))
+static unsigned short powerpc_opcd_indices[PPC_OPCD_SEGS + 1];
+#define VLE_OPCD_SEGS (1 + VLE_OP_TO_SEG (VLE_OP (-1, 0xffff)))
+static unsigned short vle_opcd_indices[VLE_OPCD_SEGS + 1];
+#define SPE2_OPCD_SEGS (1 + SPE2_XOP_TO_SEG (SPE2_XOP (-1)))
+static unsigned short spe2_opcd_indices[SPE2_OPCD_SEGS + 1];
/* Calculate opcode table indices to speed up disassembly,
and init dialect. */
void
disassemble_init_powerpc (struct disassemble_info *info)
{
- int i;
- unsigned short last;
-
if (powerpc_opcd_indices[PPC_OPCD_SEGS] == 0)
{
+ unsigned seg, idx, op;
+
+ /* PPC opcodes */
+ for (seg = 0, idx = 0; seg <= PPC_OPCD_SEGS; seg++)
+ {
+ powerpc_opcd_indices[seg] = idx;
+ for (; idx < powerpc_num_opcodes; idx++)
+ if (seg < PPC_OP (powerpc_opcodes[idx].opcode))
+ break;
+ }
+
+ /* VLE opcodes */
+ for (seg = 0, idx = 0; seg <= VLE_OPCD_SEGS; seg++)
+ {
+ vle_opcd_indices[seg] = idx;
+ for (; idx < vle_num_opcodes; idx++)
+ {
+ op = VLE_OP (vle_opcodes[idx].opcode, vle_opcodes[idx].mask);
+ if (seg < VLE_OP_TO_SEG (op))
+ break;
+ }
+ }
- i = powerpc_num_opcodes;
- while (--i >= 0)
- {
- unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
-
- powerpc_opcd_indices[op] = i;
- }
-
- last = powerpc_num_opcodes;
- for (i = PPC_OPCD_SEGS; i > 0; --i)
- {
- if (powerpc_opcd_indices[i] == 0)
- powerpc_opcd_indices[i] = last;
- last = powerpc_opcd_indices[i];
- }
-
- i = vle_num_opcodes;
- while (--i >= 0)
- {
- unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
- unsigned seg = VLE_OP_TO_SEG (op);
-
- vle_opcd_indices[seg] = i;
- }
-
- last = vle_num_opcodes;
- for (i = VLE_OPCD_SEGS; i > 0; --i)
- {
- if (vle_opcd_indices[i] == 0)
- vle_opcd_indices[i] = last;
- last = vle_opcd_indices[i];
- }
+ /* SPE2 opcodes */
+ for (seg = 0, idx = 0; seg <= SPE2_OPCD_SEGS; seg++)
+ {
+ spe2_opcd_indices[seg] = idx;
+ for (; idx < spe2_num_opcodes; idx++)
+ {
+ op = SPE2_XOP (spe2_opcodes[idx].opcode);
+ if (seg < SPE2_XOP_TO_SEG (op))
+ break;
+ }
+ }
}
- if (info->arch == bfd_arch_powerpc)
- powerpc_init_dialect (info);
+ powerpc_init_dialect (info);
}
/* Print a big endian PowerPC instruction. */
return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
}
-/* Print a POWER (RS/6000) instruction. */
-
-int
-print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
-{
- return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
-}
-
/* Extract the operand value from the PowerPC or POWER instruction. */
-static long
+static int64_t
operand_value_powerpc (const struct powerpc_operand *operand,
- unsigned long insn, ppc_cpu_t dialect)
+ uint64_t insn, ppc_cpu_t dialect)
{
- long value;
+ int64_t value;
int invalid;
/* Extract the value from the instruction. */
if (operand->extract)
{
/* BITM is always some number of zeros followed by some
number of ones, followed by some number of zeros. */
- unsigned long top = operand->bitm;
+ uint64_t top = operand->bitm;
/* top & -top gives the rightmost 1 bit, so this
fills in any trailing zeros. */
top |= (top & -top) - 1;
static int
skip_optional_operands (const unsigned char *opindex,
- unsigned long insn, ppc_cpu_t dialect)
+ uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_operand *operand;
/* Find a match for INSN in the opcode table, given machine DIALECT. */
static const struct powerpc_opcode *
-lookup_powerpc (unsigned long insn, ppc_cpu_t dialect)
+lookup_powerpc (uint64_t insn, ppc_cpu_t dialect)
{
const struct powerpc_opcode *opcode, *opcode_end, *last;
unsigned long op;
/* Find a match for INSN in the VLE opcode table. */
static const struct powerpc_opcode *
-lookup_vle (unsigned long insn)
+lookup_vle (uint64_t insn)
{
const struct powerpc_opcode *opcode;
const struct powerpc_opcode *opcode_end;
opcode < opcode_end;
++opcode)
{
- unsigned long table_opcd = opcode->opcode;
- unsigned long table_mask = opcode->mask;
+ uint64_t table_opcd = opcode->opcode;
+ uint64_t table_mask = opcode->mask;
bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
- unsigned long insn2;
+ uint64_t insn2;
const unsigned char *opindex;
const struct powerpc_operand *operand;
int invalid;
return NULL;
}
+/* Find a match for INSN in the SPE2 opcode table. */
+
+static const struct powerpc_opcode *
+lookup_spe2 (uint64_t insn)
+{
+ const struct powerpc_opcode *opcode, *opcode_end;
+ unsigned op, xop, seg;
+
+ op = PPC_OP (insn);
+ if (op != 0x4)
+ {
+ /* This is not SPE2 insn.
+ * All SPE2 instructions have OP=4 and differs by XOP */
+ return NULL;
+ }
+ xop = SPE2_XOP (insn);
+ seg = SPE2_XOP_TO_SEG (xop);
+
+ /* Find the first match in the opcode table for this major opcode. */
+ opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
+ for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
+ opcode < opcode_end;
+ ++opcode)
+ {
+ uint64_t table_opcd = opcode->opcode;
+ uint64_t table_mask = opcode->mask;
+ uint64_t insn2;
+ const unsigned char *opindex;
+ const struct powerpc_operand *operand;
+ int invalid;
+
+ insn2 = insn;
+ if ((insn2 & table_mask) != table_opcd)
+ continue;
+
+ /* Check validity of operands. */
+ invalid = 0;
+ for (opindex = opcode->operands; *opindex != 0; ++opindex)
+ {
+ operand = powerpc_operands + *opindex;
+ if (operand->extract)
+ (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
+ }
+ if (invalid)
+ continue;
+
+ return opcode;
+ }
+
+ return NULL;
+}
+
/* Print a PowerPC or POWER instruction. */
static int
{
bfd_byte buffer[4];
int status;
- unsigned long insn;
+ uint64_t insn;
const struct powerpc_opcode *opcode;
- bfd_boolean insn_is_short;
+ int insn_length = 4; /* Assume we have a normal 4-byte instruction. */
status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+
+ /* The final instruction may be a 2-byte VLE insn. */
+ if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
+ {
+ /* Clear buffer so unused bytes will not have garbage in them. */
+ buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ }
+
if (status != 0)
{
- /* The final instruction may be a 2-byte VLE insn. */
- if ((dialect & PPC_OPCODE_VLE) != 0)
- {
- /* Clear buffer so unused bytes will not have garbage in them. */
- buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
- status = (*info->read_memory_func) (memaddr, buffer, 2, info);
- if (status != 0)
- {
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
- }
- }
- else
- {
- (*info->memory_error_func) (status, memaddr, info);
- return -1;
- }
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
}
if (bigendian)
/* Get the major opcode of the insn. */
opcode = NULL;
- insn_is_short = FALSE;
if ((dialect & PPC_OPCODE_VLE) != 0)
{
opcode = lookup_vle (insn);
- if (opcode != NULL)
- insn_is_short = PPC_OP_SE_VLE(opcode->mask);
+ if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
+ {
+ /* The operands will be fetched out of the 16-bit instruction. */
+ insn >>= 16;
+ insn_length = 2;
+ }
}
+ if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
+ opcode = lookup_spe2 (insn);
if (opcode == NULL)
opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
else
(*info->fprintf_func) (info->stream, "%s", opcode->name);
- if (insn_is_short)
- /* The operands will be fetched out of the 16-bit instruction. */
- insn >>= 16;
-
/* Now extract and print the operands. */
need_comma = 0;
need_paren = 0;
skip_optional = -1;
for (opindex = opcode->operands; *opindex != 0; opindex++)
{
- long value;
+ int64_t value;
operand = powerpc_operands + *opindex;
- /* Operands that are marked FAKE are simply ignored. We
- already made sure that the extract function considered
- the instruction to be valid. */
- if ((operand->flags & PPC_OPERAND_FAKE) != 0)
- continue;
-
/* If all of the optional operands have the value zero,
then don't print any of them. */
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
/* Print the operand as directed by the flags. */
if ((operand->flags & PPC_OPERAND_GPR) != 0
|| ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0))
- (*info->fprintf_func) (info->stream, "r%ld", value);
+ (*info->fprintf_func) (info->stream, "r%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_FPR) != 0)
- (*info->fprintf_func) (info->stream, "f%ld", value);
+ (*info->fprintf_func) (info->stream, "f%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_VR) != 0)
- (*info->fprintf_func) (info->stream, "v%ld", value);
+ (*info->fprintf_func) (info->stream, "v%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_VSR) != 0)
- (*info->fprintf_func) (info->stream, "vs%ld", value);
+ (*info->fprintf_func) (info->stream, "vs%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0)
(*info->print_address_func) (memaddr + value, info);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
(*info->print_address_func) ((bfd_vma) value & 0xffffffff, info);
else if ((operand->flags & PPC_OPERAND_FSL) != 0)
- (*info->fprintf_func) (info->stream, "fsl%ld", value);
+ (*info->fprintf_func) (info->stream, "fsl%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_FCR) != 0)
- (*info->fprintf_func) (info->stream, "fcr%ld", value);
+ (*info->fprintf_func) (info->stream, "fcr%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_UDI) != 0)
- (*info->fprintf_func) (info->stream, "%ld", value);
+ (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
- (*info->fprintf_func) (info->stream, "cr%ld", value);
+ (*info->fprintf_func) (info->stream, "cr%" PPC_INT_FMT "d", value);
else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
(*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
}
else
- (*info->fprintf_func) (info->stream, "%d", (int) value);
+ (*info->fprintf_func) (info->stream, "%" PPC_INT_FMT "d", value);
if (need_paren)
{
}
}
- /* We have found and printed an instruction.
- If it was a short VLE instruction we have more to do. */
- if (insn_is_short)
- {
- memaddr += 2;
- return 2;
- }
- else
- /* Otherwise, return. */
- return 4;
+ /* We have found and printed an instruction. */
+ return insn_length;
}
/* We could not find a match. */
- (*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
+ (*info->fprintf_func) (info->stream, ".long 0x%" PPC_INT_FMT "x", insn);
return 4;
}
-const disasm_options_t *
+const disasm_options_and_args_t *
disassembler_options_powerpc (void)
{
- static disasm_options_t *opts = NULL;
+ static disasm_options_and_args_t *opts_and_args;
- if (opts == NULL)
+ if (opts_and_args == NULL)
{
size_t i, num_options = ARRAY_SIZE (ppc_opts);
- opts = XNEW (disasm_options_t);
+ disasm_options_t *opts;
+
+ opts_and_args = XNEW (disasm_options_and_args_t);
+ opts_and_args->args = NULL;
+
+ opts = &opts_and_args->options;
opts->name = XNEWVEC (const char *, num_options + 1);
+ opts->description = NULL;
+ opts->arg = NULL;
for (i = 0; i < num_options; i++)
opts->name[i] = ppc_opts[i].opt;
/* The array we return must be NULL terminated. */
opts->name[i] = NULL;
- opts->description = NULL;
}
- return opts;
+ return opts_and_args;
}
void
projects / thirdparty / binutils-gdb.git / blobdiff