+Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Apr 18 16:26:41 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_resume): Deliver SIGILL.
+ (lookup_hash): Do not print SIGILL message.
+
+Tue Feb 22 18:24:56 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_EXTRA_CFLAGS): Define SIM_HAVE_ENVIRONMENT.
+ * interp.c (sim_set_trace): Replace sim_trace. Enable tracing.
+
+Tue Feb 8 17:41:12 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (SIG_D10V_BUS): Define.
+
+ * simops.c (address_exception): Delete function.
+ (OP_30000000, OP_6401, OP_6001, OP_6000, OP_32010000, OP_31000000,
+ OP_6601, OP_6201, OP_6200, OP_33010000, OP_34000000, OP_6800,
+ OP_6C1F, OP_6801, OP_6C01, OP_36010000, OP_35000000, OP_6A00,
+ OP_6E1F, OP_6A01, OP_6E01, OP_37010000): Replace call to
+ address_exception with code that sets SIG_D10V_BUS.
+
+ * interp.c (sim_resume): When SIGBUS or SIGSEGV, deliver a bus
+ error to the simulator before resuming execution.
+ (sim_trace): Check stop reason and use that to determine sim_trace
+ return value.
+ (sim_stop_reason): For SIG_D10V_BUS return a SIGBUS / SIGSEGV
+ sigrc.
+
+Tue Jan 18 16:07:42 MST 2000 Diego Novillo <dnovillo@cygnus.com>
+
+ * interp.c (sim_create_inferior): Change internal initial value for
+ DMAP2 to 0x2000.
+
+Mon Jan 3 02:06:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (lookup_hash): Stop the update of the PC when there was
+ an illegal instruction exception.
+
+Mon Jan 3 00:14:33 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (address_exception): New function.
+ (OP_30000000, OP_6401, OP_6001, OP_6000, OP_32010000, OP_31000000,
+ OP_6601, OP_6201, OP_6200, OP_33010000, OP_34000000, OP_6800,
+ OP_6C1F, OP_6801, OP_6C01, OP_36010000, OP_35000000, OP_6A00,
+ OP_6E1F, OP_6A01, OP_6E01, OP_37010000): For "ld", "ld2w", "st"
+ and "st2w" check that the address is aligned.
+
+1999-12-30 Chandra Chavva <cchavva@cygnus.com>
+
+ * d10v_sim.h (INC_ADDR): Added code to assign
+ proper address for loads with predec operations.
+
+1999-11-25 Nick Clifton <nickc@cygnus.com>
+
+ * simops.c (OP_4E0F): New function: Simulate new bit pattern for
+ cpfg instruction.
+
+Fri Oct 29 18:34:28 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (move_to_cr): Don't allow user to set PSW.DM in either
+ DPSW and BPSW.
+
+Thu Oct 28 01:26:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5F20): Use SET_HW_PSW when updating PSW.
+ (PSW_HW_MASK): Declare.
+
+ * d10v_sim.h (move_to_cr): Add ``psw_hw_p'' parameter.
+ (SET_CREG, SET_PSW_BIT): Update.
+ (SET_HW_CREG, SET_HW_PSW): Define.
+
+Sun Oct 24 21:38:04 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_dmap_addr): Fix extraction of IOSP
+ for DMAP3.
+
+Sun Oct 24 16:04:16 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_addr): New function.
+ (xfer_mem): Rewrite. Use sim_d10v_translate_addr.
+ (map_memory): Make INLINE.
+
+Sun Oct 24 13:45:19 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_dmap_addr): New function.
+ (dmem_addr): Rewrite. Use sim_d10v_translate_dmap_addr. Change
+ offset parameter to type uint16.
+ * d10v_sim.h (dmem_addr): Update declaration.
+
+Sun Oct 24 13:07:31 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (imap_register, set_imap_register, dmap_register,
+ set_imap_register): Use map_memory.
+ (DMAP): Update.
+ (sim_create_inferior): Initialize all DMAP registers. NOTE that
+ DMAP2, in internal memory mode, is set to 0x0000 and NOT
+ 0x2000. This is consistent with the older d10v boards.
+
+Sun Oct 24 11:22:12 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_d10v_translate_imap_addr): New function.
+ (imem_addr): Rewrite. Use sim_d10v_translate_imap_addr.
+ (last_from, last_to): Declare.
+
+Sun Oct 24 01:21:56 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (struct d10v_memory): Define. Support very long
+ memories.
+ (struct _state): Replace imem, dmem and umem by mem.
+ (IMAP_BLOCK_SIZE, DMAP_BLOCK_SIZE, SEGMENT_SIZE, IMEM_SEGMENTS,
+ DMEM_SEGMENTS, UMEM_SEGMENTS): Define.
+
+ * interp.c (map_memory): New function.
+ (sim_size, xfer_memory, imem_addr, dmem_addr): Update.
+ (UMEM_SEGMENTS): Moveed to "d10v_sim.h".
+ (IMEM_SIZEDMEM_SIZE): Delete.
+
+Sat Oct 23 20:06:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c: Include "sim-d10v.h".
+ (imap_register, set_imap_register, dmap_register,
+ set_dmap_register, spi_register, spu_register, set_spi_register,
+ set_spu_register): New functions.
+ (sim_create_inferior): Update.
+ (sim_fetch_register, sim_store_register): Rewrite. Use enums
+ defined in sim-d10v.h.
+
+ * d10v_sim.h (DEBUG_MEMORY): Define.
+ (IMAP0, IMAP1, DMAP, SET_IMAP0, SET_IMAP1, SET_DMAP): Delete.
+
+Sat Oct 23 18:41:18 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Allow a debug value to be passed to the -t
+ option.
+ (lookup_hash): Don't exit on an illegal instruction.
+ (do_long, do_2_short, do_parallel): Check for failed instruction
+ lookup.
+
+Mon Oct 18 18:03:24 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
+
+ * simops.c (OP_3220): Fix trace output for illegal accumulator
+ message.
+
+1999-09-14 Nick Clifton <nickc@cygnus.com>
+
+ * simops.c: Disable setting of DM bit in PSW.
+
+Wed Sep 8 19:34:55 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
+
+ * simops.c (op_types): Added new memory indirect type OP_MEMREF3.
+ (trace_input_func): Added support for OP_MEMREF3.
+ (OP_32010000): New instruction ld.
+ (OP_33010000): New instruction ld2w.
+ (OP_5209): New instruction sac.
+ (OP_4209): New instruction sachi.
+ (OP_3220): New instruction slae.
+ (OP_36010000): New instruction st.
+ (OP_37010000): New instruction st2w.
+
+1999-09-09 Stan Shebs <shebs@andros.cygnus.com>
+
+ * interp.c (old_segment_mapping): New global.
+ (xfer_mem): Change the default segment mapping to be the way
+ that Mitsubishi prefers, but use the previous mapping if
+ old_segment_mapping is true.
+ (sim_open): Add an option -oldseg to get the old mapping.
+ (sim_create_inferior): Init mapping registers based on the
+ value of old_segment_mapping.
+
+1999-09-07 Nick Clifton <nickc@cygnus.com>
+
+ * simops.c (OP_6601): Do not write back decremented address if
+ either of the destination registers was the same as the address
+ register.
+ (OP_6201): Do not write back incremented address if either of the
+ destination registers was the same as the address register.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-04-02 Keith Seitz <keiths@cygnus.com>
+
+ * interp.c (ui_loop_hook_counter): New global (when NEED_UI_LOOP_HOOK
+ defined).
+ (sim_resume): If the counter has expired, call the ui_loop_hook,
+ if defined.
+ (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the frequency of
+ ui_loop_hook calls.
+ * Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK.
+
+Wed Mar 10 19:32:13 1999 Nick Clifton <nickc@cygnus.com>
+
+ * simops.c: If load instruction with auto increment/decrement
+ addressing is used when the destination register is the same as
+ the address register, then ignore the auto increment/decrement.
+
+Wed Mar 10 19:32:13 1999 Martin M. Hunt <hunt@cygnus.com>
+
+ * simops.c (OP_5F00): Ifdef SYS_stat case because
+ not all systems have it defined.
+
+1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)
+
+ * simops.c (OP_5607): Correct saturation comparison/assignment.
+ (OP_1201, OP_1203, OP_17001200, OP_17001202,
+ OP_2A00, OP_2800, OP_2C00, OP_3200, OP_3201,
+ OP_1001, OP_1003, OP_17001000, OP_17001002): Ditto.
+
+1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)
+
+ * simops.c (OP_5605): Sign extend MIN32 and MAX32 before saturation
+ comparison.
+ (OP_5607): Ditto.
+ (OP_2A00): Ditto.
+ (OP_2800): Ditto.
+
+1999-01-13 Jason Molenda (jsm@bugshack.cygnus.com)
+
+ * simops.c (OP_1223): Sign extend MIN32 and MAX32 before saturation
+ comparison.
+
+Tue Nov 24 17:04:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (sys/syscall.h): Include targ-vals.h instead.
+ (SYS_*): Replace with TARGET_SYS_*.
+
+ * Makefile.in: Add dependency on targ-vals.h.
+ (NL_TARGET): Define as NL_TARGET_d10v.
+
+Wed Sep 30 00:06:32 1998 Andrew Cagney <cagney@amy.cygnus.com>
+
+ * interp.c (xfer_mem): Missing break, instruction memory case
+ flowed into unified memory case.
+
+Wed Sep 30 10:14:18 1998 Nick Clifton <nickc@cygnus.com>
+
+ * simops.c: If load instruction with auto increment/decrement
+ addressing is used when the destination register is the same as
+ the address register, then ignore the auto increment/decrement.
+
+Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:20:23 1998 Tom Tromey <tromey@cygnus.com>
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:20:06 1998 Tom Tromey <tromey@cygnus.com>
+
+ * configure.in: Don't call sinclude.
+
+Fri Apr 24 11:04:46 1998 Andrew Cagney <cagney@chook.cygnus.com>
+
+ * interp.c (struct hash_entry): OPCODE and MASK are unsigned.
+
+ * d10v_sim.h (remote-sim.h, sim-config.h): Include.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 1 12:59:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (trace_input_func): Use move_from_cr / CREGS to obtain
+ up-to-date CR value.
+ (OP_OP_1000000, add3): Trace inputs before performing add.
+ (OP_5F00, <*>): Trace input registers before making system call.
+ (OP_5F00, <kill>): Trace R0, R1 not REGn.
+ (OP_5F00, <getpid>): Always return 47.
+
+ * d10v_sim.h (SLOT, SLOT_NR, SLOT_PEND_MASK, SLOT_PEND,
+ SLOT_DISCARD, SLOT_FLUSH): Define. An implementation of write
+ back slots.
+ (struct _state): Add struct slot slot to global state variable.
+ (struct _state): Delete fields SM, EA, DB, DM, IE, RP, MD, FX, ST,
+ F0, F1, C from global State variable.
+ (struct _state): Add struct trace to global State variable.
+ (GPR, SET_GPR): Define. SET_GPR uses SLOT_PEND.
+ (PSW*, SET_PSW*): Define. SET_PSW* uses SET_CREG.
+ (CREG, SET_CREG, SET_*): Define. SET_CREG uses func move_to_cr.
+ (INC_ADDR): Re-implement. Use SET_GPR to update registers.
+ (JMP): Re-implement. Use SET_* to update registers.
+
+ * interp.c: Use new SET_* et.al. macros to fetch / store
+ registers.
+ (get_operands): Squirrel away trace values at start of each
+ operand decode.
+ (do_2_short): Flush pending writes before issuing second
+ instruction.
+ (sim_resume): Flush pending writes at end of instruction cycle.
+ (sim_fetch_register, sim_store_register, sim_create_inferior):
+ After scheduling updates to registers using SET_*, flush updates.
+ (sim_resume): Re-order handling of RPT/repeat and IBA/hbreak so
+ that each sets pc using SET_* and last SET_* eventually winds out.
+
+ * simops.c: Use new SET_* et.al. macros to fetch / store
+ registers.
+ (move_to_cr): Add MASK argument for selective update of CREG bits.
+ Re-implement using new SET_* macros.
+ (trace_output_func, trace_output): Delete. Replace with.
+ (do_trace_output_flush, trace_output_finish, trace_output_40,
+ trace_output_32, trace_output_16, trace_output_void,
+ trace_output_flag): New functions. Handle specific trace cases.
+ (OP_*): Re-write tracing to use new trace_output_* functions.
+ (OP_*): Re-write to use new SET_* et.al. macros.
+ (FUNC, PARM[1-4], RETVAL, RETVAL32): Redo definition.
+ (RETVAL_HIGH, RETVAL_LOW): Delete, use RETVAL32.
+
+Wed Apr 1 12:55:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (SIM_AC_OPTION_WARNINGS): Add.
+ configure: Re-generate.
+
+Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Feb 17 12:38:42 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_store_register, sim_fetch_register): Pass in
+ length parameter. Return -1.
+
+Mon Oct 27 14:43:33 1997 Fred Fish <fnf@cygnus.com>
+
+ * (dmem_addr): If address is illegal or in I/O space, signal a bus
+ error. Allocate unified memory on demand. Fix DMEM address
+ calculations.
+
+Mon Feb 16 10:27:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5F20): Implement "dbt".
+ (OP_5F60): Implement "rtd".
+
+ * d10v_sim.h (DPC_CR): Define enum.
+ (DBT_VECTOR_START): Define
+ (DPSW, DPC): Define.
+
+Fri Feb 13 15:15:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (move_to_cr): Sync regs[SP_IDX] with State.sp according
+ to PSW:SM.
+
+ * d10v_sim.h (struct _state): Add sp, as holding area for SPI/SPU.
+ (SP_IDX): Define.
+
+Wed Feb 11 16:53:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5F00): Call error instead of abort for unknown
+ syscalls.
+
+ * d10v_sim.h (enum): Define DPSW_CR.
+
+ * simops.c (move_to_cr): Mask out hardwired zero bits in DPSW.
+
+Tue Feb 10 18:28:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_write_phys): Delete.
+ (sim_load): Call sim_load_file with sim_write and LMA.
+
+Mon Feb 9 12:05:01 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c: Rewrite xfer_mem so that it translates addresses as -
+ 0x00... - DMAP translated memory, 0x01... IMAP translated memory,
+ 0x10... - on-chip data, 0x11... - on-chip insn, 0x12... - unified
+ memory.
+ (pc_addr): Delete.
+ (imem_addr): New function - translate IMEM address.
+ (sim_resume): Use imem_addr to translate insn address, abort if
+ translation failed.
+ (sim_create_inferior): Write ARGV to memory using sim_write. Pass
+ argc/argv using r0/r1 not r2/r3.
+ (sim_size): Do not initialize IMAP/DMAP here.
+ (sim_open): Call sim_create_inferior and sim_size to initialize
+ the system.
+ (sim_create_inferior): Initialize IMAP/DMAP to hardware reset
+ defaults.
+ (init_system): Delete.
+ (xfer_mem, sim_fetch_register, sim_store_register): Do not call
+ init_system.
+ (decode_pc): Check prog_bfd is defined before looking up .text
+ section.
+
+Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Jan 25 22:23:01 1998 Michael Meissner <meissner@cygnus.com>
+
+ * interp.c (sim_stop_reason): Exit status is now in r0, not r2.
+
+Sat Jan 24 19:00:30 1998 Michael Meissner <meissner@cygnus.com>
+
+ * d10v_sim.h (DEBUG_TRAP): New debug flag.
+
+ * simops.c (OP_5F00): If DEBUG_TRAP is on, turn traps 0-14 into
+ printing the registers.
+
+Thu Jan 22 17:54:01 1998 Michael Meissner <meissner@cygnus.com>
+
+ * simops.c (op_types): New ABI, args are r0..r3, system call # is
+ in r4.
+ (trace_{in,out}put_func): Ditto.
+ (OP_4900): Ditto.
+ (OP_24800000): Ditto.
+ (OP_4D00): Ditto.
+ (OP_5F00): Ditto.
+
+Thu Jan 22 14:30:36 1998 Fred Fish <fnf@cygnus.com>
+
+ * interp.c (UMEM_SEGMENTS): New define, set to 128.
+ (sim_size): Use UMEM_SEGMENTS rather than hardwired constant.
+ (sim_close): Reset prog_bfd to NULL after closing it. Also
+ reset prog_bfd_was_opened_p after closing prog_bfd.
+ (sim_load): Reset prog_bfd_was_opened_p after closing prog_bfd.
+ (sim_create_inferior): Get start address from abfd not prog_bfd.
+ (xfer_mem): Do bounds checking on addresses and return zero length
+ read/write on bad addresses, rather than aborting. Prepare to
+ be able to handle xfers that cross segment boundaries, but not
+ yet implemented. Only emit debug message when d10v_debug is
+ set as well as DEBUG being defined.
+
+Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Tue Dec 9 10:28:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (RPT_S): Index cregs with RPT_S_CR not RPT_E_CR.
+ (BPSW): Ditto for BPSW_CR and not PSW_CR.
+
+ * simops.c (OP_5F40): JMP to BPC instead of assigning PC directly.
+
+Mon Dec 8 12:58:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5F00): From Martin Hunt <hunt@cygnus.com>. Change
+ reserved trap from 0 to 15. Add trap emulation code for 0-14.
+
+ * interp.c (sim_resume): From Martin Hunt <hunt@cygnus.com>. Check
+ IBA for SDBT.
+
+ * d10v_sim.h (AE_VECTOR_START, RIE_VECTOR_START,
+ SDBT_VECTOR_START, TRAP_VECTOR_START): Define.
+
+ * simops.c (OP_5F00): For "trap", mask out all but SM bit in PSW,
+ use move_to_cr.
+ (OP_5F00): For "trap", update BPSW with move_to_cr.
+
+Fri Dec 5 15:31:17 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (enum): Enumerate CR register names.
+ (enum): Enumerate PSW bit values.
+ (PSW): Obtain value uing move_from_cr.
+ (MOD_S, MOD_E, BPSW): Make r-values.
+ (move_from_cr, move_to_cr): Declare functions.
+
+ * interp.c (sim_fetch_register, sim_store_register): Use
+ move_from_cr and move_to_cr for CR register transfers.
+
+ * simops.c (move_from_cr, move_to_cr): New functions.
+ (OP_5F40): Move BPSW to PSW using move_to_cr and move_from_cr.
+ (OP_5600): For "mvtc", use function move_to_cr.
+ (OP_5200): For "mvfc", use function move_from_cr.
+
+Fri Dec 5 13:33:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_5600): For "mvtc" MOD_E and MOD_S, ensure that the
+ LSbit is zero.
+
+Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Thu Dec 4 16:51:02 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (struct _state): Add DM - PSW debug mask.
+
+ * simops.c (OP_5600): For "mvtc", save PSW.DM.
+ (OP_5200): Ditto for "mvfc".
+
+Wed Dec 3 17:27:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h (SEXT56): Define.
+
+ * simops.c (OP_4201): For "rac", sign extend 56 bit value before
+ it is shifted.
+
+ * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
+ SIGNED64 macro.
+
+Tue Dec 2 15:38:34 1997 Fred Fish <fnf@cygnus.com>
+
+ * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or
+ RIGHT_FIRST, as appropriate, instead of hardcoded ints that
+ don't match enum values.
+
+Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_3A00): For "macu", perform multiply stage using 32
+ bit rather than 16 bit precision.
+ (OP_3C00): For "mulxu", store unsigned product in ACC.
+ (OP_3800): For "msbu", subtract unsigned product from ACC,
+ (OP_0): For "sub", compute carry by comparing inputs.
+
+Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_1000): For "sub2w", compute carry by comparing
+ inputs.
+
+Mon Nov 17 20:57:21 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_1): Use 32 bit unsigned arithmetic for subtract,
+ carry indicated by value > 0xffff.
+
+Fri Nov 14 12:51:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_resume): Don't set up SIGINT handler using signal,
+ handled by client.
+ (sim_resume): Fix race condition of a direct assignment to
+ stop_simulator, conditionally call sim_stop.
+ (sim_stop_reason): Check stop_simulator returning SIGINT. Clear
+ stop_simulator ready for next sim_resume call.
+ (sim_ctrl_c): Delete function.
+
+Thu Nov 13 19:29:34 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_resume): For "REP", only check/update the PC when
+ a branch instruction has not been executed.
+
+Mon Nov 10 17:50:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign
+ extend bit 44 all constants.
+ (OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro.
+
+Fri Oct 24 10:26:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * d10v_sim.h: Include sim-types.h.
+ (uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef
+ using unsigned8 et.al. from sim-types.h.
+ (SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with
+ SIGNED64 macro.
+
+Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_write_phys): New function, write to physical
+ instead of virtual memory.
+
+ * interp.c (sim_load): Pass lma_p and sim_write_phys to
+ sim_load_file.
+
+Mon Oct 13 10:55:07 1997 Fred Fish <cygnus.com>
+
+ * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
+ exception generation code to OP_6E01.
+ (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception
+ generation code.
+
+Sat Oct 11 09:02:08 1997 Fred Fish <fnf@cygnus.com>
+
+ * simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
+ (OP_6601): Ditto.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Sep 27 12:51:34 1997 Fred Fish <fnf@cygnus.com>
+
+ * interp.c (pc_addr): Discard upper bit(s) of PC in case
+ IMAP1 selects unified memory.
+ * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing
+ for end condition.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
Wed Sep 10 22:30:24 1997 Martin M. Hunt <hunt@cygnus.com>
* interp.c (sim_resume): Increment PC at end of rep