[powerpc] add 'volatile' to asm

[thirdparty/glibc.git] / sysdeps / powerpc / fpu / fenv_libc.h

diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index 0a4a57da6813a000d8850b71048a1abfa97edb40..f66bf246cb89c2b53b5ceae0a8c2ca4c6d1cd54e 100644 (file)
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -1,5 +1,5 @@
 /* Internal libc stuff for floating point environment routines.
-   Copyright (C) 1997, 2006, 2008, 2009 Free Software Foundation, Inc.
+   Copyright (C) 1997-2019 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -13,9 +13,8 @@
    Lesser General Public License for more details.
 
    You should have received a copy of the GNU Lesser General Public
-   License along with the GNU C Library; if not, write to the Free
-   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
-   02111-1307 USA.  */
+   License along with the GNU C Library; if not, see
+   <http://www.gnu.org/licenses/>.  */
 
 #ifndef _FENV_LIBC_H
 #define _FENV_LIBC_H   1
@@ -24,15 +23,16 @@
 #include <ldsodefs.h>
 #include <sysdep.h>
 
-libm_hidden_proto (__fe_nomask_env)
+extern const fenv_t *__fe_nomask_env_priv (void);
+
+extern const fenv_t *__fe_mask_env (void) attribute_hidden;
 
 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
 
 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
    pointer.  */
-#define fegetenv_register() \
-        ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
+#define fegetenv_register() __builtin_mffs()
 
 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
 #define fesetenv_register(env) \
@@ -44,7 +44,7 @@ libm_hidden_proto (__fe_nomask_env)
                          "mtfsf 0xff,%0,1,0; " \
                          ".machine pop" : : "f" (d)); \
          else \
-           asm volatile ("mtfsf 0xff,%0" : : "f" (d)); \
+           __builtin_mtfsf (0xff, d); \
        } while(0)
 
 /* This very handy macro:
@@ -56,9 +56,9 @@ libm_hidden_proto (__fe_nomask_env)
 #define relax_fenv_state() \
        do { \
           if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
-            asm (".machine push; .machine \"power6\"; " \
+            asm volatile (".machine push; .machine \"power6\"; " \
                  "mtfsfi 7,0,1; .machine pop"); \
-          asm ("mtfsfi 7,0"); \
+          asm volatile ("mtfsfi 7,0"); \
        } while(0)
 
 /* Set/clear a particular FPSCR bit (for instance,
@@ -70,22 +70,12 @@ libm_hidden_proto (__fe_nomask_env)
 typedef union
 {
   fenv_t fenv;
-  unsigned int l[2];
+  unsigned long long l;
 } fenv_union_t;
 
 
 static inline int
-__fegetround (void)
-{
-  int result;
-  asm volatile ("mcrfs 7,7\n\t"
-               "mfcr  %0" : "=r"(result) : : "cr7");
-  return result & 3;
-}
-#define fegetround() __fegetround()
-
-static inline int
-__fesetround (int round)
+__fesetround_inline (int round)
 {
   if ((unsigned int) round < 2)
     {
@@ -106,7 +96,14 @@ __fesetround (int round)
 
   return 0;
 }
-#define fesetround(mode) __fesetround(mode)
+
+/* Same as __fesetround_inline, however without runtime check to use DFP
+   mtfsfi syntax (as relax_fenv_state) or if round value is valid.  */
+static inline void
+__fesetround_inline_nocheck (const int round)
+{
+  asm volatile ("mtfsfi 7,%0" : : "i" (round));
+}
 
 /* Definitions of all the FPSCR bit numbers */
 enum {
@@ -117,7 +114,7 @@ enum {
   FPSCR_UX,        /* underflow */
   FPSCR_ZX,        /* zero divide */
   FPSCR_XX,        /* inexact */
-  FPSCR_VXSNAN,    /* invalid operation for SNaN */
+  FPSCR_VXSNAN,    /* invalid operation for sNaN */
   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
@@ -147,13 +144,30 @@ enum {
   /* the remaining two least-significant bits keep the rounding mode */
 };
 
+static inline int
+fenv_reg_to_exceptions (unsigned long long l)
+{
+  int result = 0;
+  if (l & (1 << (31 - FPSCR_XE)))
+    result |= FE_INEXACT;
+  if (l & (1 << (31 - FPSCR_ZE)))
+    result |= FE_DIVBYZERO;
+  if (l & (1 << (31 - FPSCR_UE)))
+    result |= FE_UNDERFLOW;
+  if (l & (1 << (31 - FPSCR_OE)))
+    result |= FE_OVERFLOW;
+  if (l & (1 << (31 - FPSCR_VE)))
+    result |= FE_INVALID;
+  return result;
+}
+
 #ifdef _ARCH_PWR6
   /* Not supported in ISA 2.05.  Provided for source compat only.  */
 # define FPSCR_NI 29
 #endif /* _ARCH_PWR6 */
 
 /* This operation (i) sets the appropriate FPSCR bits for its
-   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
+   parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
    otherwise passes its parameter through unchanged (in particular, -0
    and +0 stay as they were).  The `obvious' way to do this is optimised
    out by gcc.  */