/* Internal libc stuff for floating point environment routines.
- Copyright (C) 1997 Free Software Foundation, Inc.
+ Copyright (C) 1997-2019 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, write to the Free
- Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- 02111-1307 USA. */
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
#ifndef _FENV_LIBC_H
#define _FENV_LIBC_H 1
#include <fenv.h>
+#include <ldsodefs.h>
+#include <sysdep.h>
+
+extern const fenv_t *__fe_nomask_env_priv (void);
+
+extern const fenv_t *__fe_mask_env (void) attribute_hidden;
/* The sticky bits in the FPSCR indicating exceptions have occurred. */
#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
/* Equivalent to fegetenv, but returns a fenv_t instead of taking a
pointer. */
-#define fegetenv_register() \
- ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
+#define fegetenv_register() __builtin_mffs()
/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer. */
#define fesetenv_register(env) \
- ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
+ do { \
+ double d = (env); \
+ if(GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
+ asm volatile (".machine push; " \
+ ".machine \"power6\"; " \
+ "mtfsf 0xff,%0,1,0; " \
+ ".machine pop" : : "f" (d)); \
+ else \
+ __builtin_mtfsf (0xff, d); \
+ } while(0)
/* This very handy macro:
- Sets the rounding mode to 'round to nearest';
- Prevents exceptions from being raised for inexact results.
These things happen to be exactly what you need for typical elementary
functions. */
-#define relax_fenv_state() asm ("mtfsfi 7,0")
+#define relax_fenv_state() \
+ do { \
+ if (GLRO(dl_hwcap) & PPC_FEATURE_HAS_DFP) \
+ asm volatile (".machine push; .machine \"power6\"; " \
+ "mtfsfi 7,0,1; .machine pop"); \
+ asm volatile ("mtfsfi 7,0"); \
+ } while(0)
/* Set/clear a particular FPSCR bit (for instance,
reset_fpscr_bit(FPSCR_VE);
typedef union
{
fenv_t fenv;
- unsigned int l[2];
+ unsigned long long l;
} fenv_union_t;
+
+static inline int
+__fesetround_inline (int round)
+{
+ if ((unsigned int) round < 2)
+ {
+ asm volatile ("mtfsb0 30");
+ if ((unsigned int) round == 0)
+ asm volatile ("mtfsb0 31");
+ else
+ asm volatile ("mtfsb1 31");
+ }
+ else
+ {
+ asm volatile ("mtfsb1 30");
+ if ((unsigned int) round == 2)
+ asm volatile ("mtfsb0 31");
+ else
+ asm volatile ("mtfsb1 31");
+ }
+
+ return 0;
+}
+
+/* Same as __fesetround_inline, however without runtime check to use DFP
+ mtfsfi syntax (as relax_fenv_state) or if round value is valid. */
+static inline void
+__fesetround_inline_nocheck (const int round)
+{
+ asm volatile ("mtfsfi 7,%0" : : "i" (round));
+}
+
/* Definitions of all the FPSCR bit numbers */
enum {
FPSCR_FX = 0, /* exception summary */
FPSCR_UX, /* underflow */
FPSCR_ZX, /* zero divide */
FPSCR_XX, /* inexact */
- FPSCR_VXSNAN, /* invalid operation for SNaN */
+ FPSCR_VXSNAN, /* invalid operation for sNaN */
FPSCR_VXISI, /* invalid operation for Inf-Inf */
FPSCR_VXIDI, /* invalid operation for Inf/Inf */
FPSCR_VXZDZ, /* invalid operation for 0/0 */
FPSCR_UE, /* underflow exception enable */
FPSCR_ZE, /* zero divide exception enable */
FPSCR_XE, /* inexact exception enable */
+#ifdef _ARCH_PWR6
+ FPSCR_29, /* Reserved in ISA 2.05 */
+#else
FPSCR_NI /* non-IEEE mode (typically, no denormalised numbers) */
+#endif /* _ARCH_PWR6 */
/* the remaining two least-significant bits keep the rounding mode */
};
+static inline int
+fenv_reg_to_exceptions (unsigned long long l)
+{
+ int result = 0;
+ if (l & (1 << (31 - FPSCR_XE)))
+ result |= FE_INEXACT;
+ if (l & (1 << (31 - FPSCR_ZE)))
+ result |= FE_DIVBYZERO;
+ if (l & (1 << (31 - FPSCR_UE)))
+ result |= FE_UNDERFLOW;
+ if (l & (1 << (31 - FPSCR_OE)))
+ result |= FE_OVERFLOW;
+ if (l & (1 << (31 - FPSCR_VE)))
+ result |= FE_INVALID;
+ return result;
+}
+
+#ifdef _ARCH_PWR6
+ /* Not supported in ISA 2.05. Provided for source compat only. */
+# define FPSCR_NI 29
+#endif /* _ARCH_PWR6 */
+
/* This operation (i) sets the appropriate FPSCR bits for its
- parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
+ parameter, (ii) converts sNaN to the corresponding qNaN, and (iii)
otherwise passes its parameter through unchanged (in particular, -0
and +0 stay as they were). The `obvious' way to do this is optimised
out by gcc. */
({ float f; asm volatile ("fmuls %0,%1,%2" \
: "=f"(f) \
: "f" (x), "f"((float)1.0)); f; })
-
+
#endif /* fenv_libc.h */